JPH01302457A - Data transferring system - Google Patents

Abstract

PURPOSE:To facilitate the editing of the byte position of the transfer data of a microprocessor by byte-swapping a data block read out of a buffer memory based on the address information of a main memory, and applying them to the FIFO circuit between an internal bus data and a system bus control circuit. CONSTITUTION:Serial data received from a communication line 40 by a communication control device 10 are stored from an odd-number address 2n of a buffer memory 12 through a serial/parallel exchange circuit 11 as a data block in units of a byte. Further, a microprocessor 14 notifies a central processor 20 of the reception completing interruption of the received data block, obtains the address information to transfer the data block to a main memory 30 from the device 20, and sets a FIFO circuit 15 at the same data width from a memory 12 through an internal data bus 13 at 2Xk bytes. The data block set at the circuit 15 is shifted to a register 17 in a system bus control circuit 16, and transferred from a system bus 50 to the memory 30.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for the data transfer method of a communication control apparatus.

In particular, it relates to a data transfer method that requires conversion of data bytes.

〔overview〕

In a data transfer method, the present invention provides a FIFO circuit between an internal data bus and a system bus control circuit that can be accessed in byte units and has the same byte width as the internal data bus, and converts received data blocks stored in a buffer memory into words. After reading in units and byte-swapping based on the address information of the main memory, it is repeatedly stored in this FIFO circuit, and based on the address information, the output of the FIFO circuit is set to the system bus control circuit and transferred to the main memory. This makes it easier to edit the byte position of the microprocessor's transfer data.

[Conventional technology]

FIG. 4 is a block diagram of a conventional data transfer device. FIG. 5 is a data arrangement diagram of a conventional data transfer device. FIG. 6 is a flowchart showing the processing of a microprocessor in a conventional data transfer device.

Conventionally, a data transfer method of a communication control device has a configuration as shown in FIG. Note that in this example, k and l are set to "1", and the internal data bus 13 and system bus 5
An example is shown in which the data width of 0 is 2 bytes. Communication line 4
The data received from 0 is stored from the even number byte address of the buffer memory 12 with a data width of 2 bytes, and the microprocessor 14 notifies the central processing unit 20 of a reception completion interrupt of the received data block,
0 to obtain the address information of the main memory 30 for transferring the received data block to the main memory 30, set the data from the buffer memory 12 to the system bus control circuit 16 via the internal data bus 13, and then perform system bus control. Circuit 16 sequentially transferred the received data blocks to main memory 30 via system bus 50.

As shown in FIG. 5, the data transfer method of the communication control device 10 having the internal data bus 13 of 2-byte width in the conventional example described above is based on the even-numbered byte address 2n (
data byte block (hereinafter 8
An example of a data block consisting of byte data DO to D7 is shown. ) to odd number byte address 2 of main memory 30
When sequentially transferring to an area starting from m+1 (an integer where m≧0), the following will occur. That is, as shown in the flowchart of FIG.
Read 1D1 in word units 5IOI, S102)
, after performing the byte swap (3103), save the data D1 to a register in the microprocessor 14 or an empty area of the buffer memory 12 (3104),
After data DO is written to the upper byte side register 17 of the 2-byte register in the system bus control circuit 16 (S105), it is written from the system bus control circuit 16 to byte address 2m+1 in the area of the main memory 30.

Next, the microprocessor 14 reads the next data D2 and D3 in word units from the word address n+l of the buffer memory 12 (3106, 3107), performs a byte swap (3108), and then saves the data D3 (3109). ), the saved data Di and data D2 were written into a 2-byte register in the system bus control circuit 16 in word units (S110.5ill).

[Problem that the invention seeks to solve]

However, in such a conventional data transfer method, the processing performed when sequentially transferring data byte blocks starting from even numbered byte address 20 of the buffer memory 12 to the memory starting from odd numbered byte address 2m+1 of the main memory 30 is as follows. , the data byte block from the even byte address 2n of the buffer memory 12 is transferred to the main memory 30.
When sequentially transferring data to an area starting from even-numbered byte address 2m of In comparison, the processing of the microprocessor 14 becomes more complicated, and the speed at which data blocks are transferred becomes significantly slower.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide a data transfer method that allows easy editing of the byte position of transfer data of a microprocessor.

[Means for solving problems]

The present invention relates to a buffer memory that is connected to an internal data bus with a width of 2 x k (k is an integer greater than or equal to 1) bytes and stores data blocks in units of bytes received from a communication line, and this internal data bus and a central processing a system bus control circuit connected to the device and the main memory and inserted between a system bus having a width of 2xl (1 is an integer greater than or equal to) bytes;
Means for setting the contents of the buffer memory to this system bus control circuit via the internal data bus based on address information of this main memory from the central processing unit, and output of the system bus control circuit based on this address information. and a processor including means for transferring data to this main memory via this system bus, the 2× The setting means includes a k-byte wide FIFO circuit, and the setting means byte-swaps the data block read from the buffer memory based on the address information and supplies the data block to the FIFO circuit, and sends the output of the FIFO circuit to the system bus. It is characterized in that it includes means for applying to the control circuit.

[Effect]

A 2.times.k byte wide FIFO circuit that can be accessed in byte units is provided between the internal data bus and the system bus control circuit. The microprocessor byte-swaps the data block read from the buffer memory based on the address information of the main memory and supplies it to the FIFO circuit.
The output of the IFO circuit is given to the system bus control circuit. The above operation makes it easy to edit the byte position of the microprocessor's transfer data.

For example, if the buffer memory and main memory have a data width of 2 bytes and data byte blocks are sequentially transferred from an even numbered byte address in the buffer memory to an area starting from an odd numbered byte address in the main memory, the lower byte data and the upper byte data are The data is byte swapped and given to the FIFO circuit, and the first upper byte data is first transferred from the FIFO circuit to the main memory, and then transferred in units of words.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a data transfer device according to an embodiment of the present invention. In FIG. 1, a data transfer device is provided in a communication control device 10, connected to an internal data bus 13 having a width of 2×k (k is an integer of 1 or more) bytes, and connected from a communication line 40 to a serial-to-parallel conversion circuit 11. a buffer memory 12 for storing data blocks in bytes received via the
is connected to the internal data bus 13, the central processing unit 20, and the main memory 30, and is connected to the internal data bus 13, the central processing unit 20, and the main memory 30.
The system bus control circuit 16 inserted between the byte-wide system bus 50 and the buffer memory 1 based on the address information of the main memory 30 from the central processing unit 20
2 is sent to the register 17.2 of the system bus control circuit 16 via the internal data bus 13. ．． 172 and means for transferring the output of the system bus control circuit 16 to the main memory 30 via the system bus 50 based on this address information.

Here, the feature of the present invention is that the internal data bus 1
3 and the system bus control circuit 16, the FIFO circuit 1 has a 2× byte width and can be accessed in byte units.
5, the setting means byte-swaps the data block read from the buffer memory 12 based on the address information and supplies it to the FIFO circuit 15.
It includes means for providing the output of the O circuit 15 to the system bus control circuit 16.

The operation of the data transfer device having such a configuration will be explained. FIG. 2 shows a data arrangement diagram of the data transfer device of the present invention. FIG. 3 is a flowchart showing the processing of the microprocessor of the data transfer device of the present invention.

In FIG. 1, a communication control device 10 stores serial data received from a communication line 40 through a serial-parallel switching circuit 11 as a byte-based data block from an even address 2n (an integer where n≧0) in a buffer memory 12. do.

The microprocessor 14 notifies the central processing unit 20 of a reception completion interrupt for the received data block, obtains address information of the main memory 30 from the central processing unit 20 for transferring the received data block to the main memory 30, and transfers the received data block to the main memory 30, and transfers the received data block to the main memory 30. The data is set from the memory 12 to the FIFO circuit 15 having the same data width as the internal data bus 13 via the internal data bus 13 of 2×k (k>00 integer) bytes. The data block set in the FIFO circuit 15 is transferred to the register 17 in the system bus control circuit 16 and transferred to the system bus 5.
0 to the main memory 30.

In FIG. 2, with k=1=1, buffer memory 1
An example will be shown in which 8-byte data blocks DO to D7 from 2 even-numbered byte addresses 2n are sequentially transferred to an area starting from odd-numbered byte addresses 2m+1 (m≧0, an integer) of the main memory 30.

In FIG. 3, the microprocessor 14 first starts with data DO1D1 from the word address n of the buffer memory 12.
is read in word units (S11.512), after byte swapping (S13), F I F○ circuit 1
5 in word units (S14), then write the next data D2 from word address n+l of the buffer memory 12,
After reading D3 in word units (S16.512) and byte swapping (313), FIFO circuit 1
5 in word units (314).

By repeating the same process, an 8-byte data block is set in the FIFO circuit 15 with the upper and lower bytes interchanged.

When transferring to the register 17 in the system bus control circuit 16, first, only the first byte data DO is transferred to the register 17 in the system bus control circuit 16 as upper byte data.
from the system bus control circuit 16 to the byte address 2m+1 in the area of the main memory 30 via the system bus 50. By reading only the byte data DO, the data block in the FIFO circuit 15 will have only the upper byte string shifted, and from then on, the FIFO will be read in word units.
The data is read from the circuit 15 and set in a 2-byte register 17 in the system bus control circuit 16, and the system bus control circuit 16 transfers it to the area of the main memory 30 via the system bus 50.

If the number of data blocks to be transferred is an even number such as 8 bytes, the final data transfer will be the transfer of only the lower byte, and if the number of data blocks to be transferred is an odd number, the final data transfer will also be in word units. Become.

Similarly, k>l, Jul even number byte address of memory 12 2×kxn
Receive data block from address main memory 300 bytes address 2xIXm+P (0≦P less 21 integers)
When transferring data to an area starting from , the microprocessor 14 shifts the word-by-word data read from the buffer memory 12 by the remaining bytes of P/(2×k) to the upper byte side, and then transfers the data to the area starting from F I F O[F15j, :JQ
[The next time the data block set in the FIFO circuit 15 is transferred to the 21-byte wide register 17 in the system bus control circuit 16, the FIFO
The upper (remainder of P/(2×k)) bytes of the FO circuit 15 are transferred, the arrangement of data blocks in the FIFO circuit 15 is shifted, and from now on, transfer is performed sequentially in word units.

〔Effect of the invention〕

As described above, the present invention allows the microprocessor to easily edit the byte position of transfer data even when a received data block stored from an even byte address in a buffer memory is transferred to the main memory starting from an odd byte address. It has great effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention. FIG. 2 is a data arrangement diagram of the data transfer device of the present invention. FIG. 3 is a flowchart showing the processing of the microprocessor of the data transfer device of the present invention. FIG. 4 is a block diagram of a conventional data transfer device. FIG. 5 is a data arrangement diagram of a conventional data transfer device. FIG. 6 is a flowchart showing the processing of a microprocessor in a conventional data transfer device. DESCRIPTION OF SYMBOLS 10... Communication control device, 11... Serial-parallel conversion circuit, 12... Buffer memory, 13... Internal data bus, 14... Microprocessor, 15...
・FIFO circuit, 16...System lotus control 1 time L
17. ．． 172...Register in system bus control circuit, 20...Central processing unit, 30...Main memory, 40...Communication line, 50...System bus. Patent issuer's agent,

Claims (1)

[Claims] A buffer memory (12) connected to an internal data bus with a width of 1, 2×k (k is an integer of 1 or more) bytes and storing data blocks in bytes received from a communication line; A system bus control circuit (16) inserted between the data bus and a 2×l (l is an integer greater than or equal to k) byte wide system bus connected to the central processing unit and main memory.
a means for setting the contents of the buffer memory in the system bus control circuit via the internal data bus based on the address information of the main memory from the central processing unit; and a system bus control circuit based on the address information. and a processor (14) including means for transferring the output of a processor (14) to the main memory via the system bus, the processor (14) being inserted between the internal data bus and the system bus control circuit in units of bytes. Accessible 2 x k byte wide FIFO circuit (15)
The setting means is configured to byte-swap the data block read from the buffer memory based on the address information and provide the data block to the FIFO circuit.
A data transfer system comprising means for providing the output of the FO circuit to the system bus control circuit.