JPH01298888A - Screen split control circuit - Google Patents

Abstract

PURPOSE:To obtain a split picture with accurate color reproduction even if a composite color video signal (composite signal) is stored in a memory means without any conversion by providing a write system and readout system color subcarrier phase correction means. CONSTITUTION:The phase of a small picture data is corrected so that the color subcarrier between the small screens is consecutive by a write system color phase correction means 14 before the data is stored in a memory means 16. Moreover, the split picture data stored in the memory means 16 is picture data by one field and it is read in common for 1st and 2nd fields and displayed on the television screen, then since the phase pattern of the color subcarrier of the 1st and 2nd fields is deviated mutually by a half period, color inversion is caused on the entire screen for each transfer from the 1st field to the 2nd field. Then the phase of the picture data is corrected in the unit of fields by the readout system color phase correction means 20. Thus, the composite signal is stored in the memory without any conversion and the split picture is generated and processed.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to television broadcasting, LV (laser vision disc), 'VTR (video tape recorder), CDV (
Regarding a screen division control circuit for creating a divided image on a television receiver based on a composite color video signal such as a compact disc with images, the system stores the composite color video signal in memory as a composite signal and performs screen division control. In this case, discontinuity in the color subcarrier phase is prevented and stable color images can be obtained.

[Conventional technology]

Split screen playback is a special playback of composite color video signals such as television broadcasting, LV, VTR, CDV, etc. This is to divide the TV screen 1 into four parts, for example as shown in Figure 2, and apply an arbitrary field image to each car screen 1-1 to 1-4. (In the specification, it is referred to as a small image, and the entire image that is a combination of small images is referred to as a divided image.) Specifically, for example, each car screen 1
-1 to 1-4, respectively, by applying small images obtained by reducing (or trimming) the input image of an arbitrary field to create one still image that combines four different small images, or for each car. Screens 1-1 to 1-4
A series of actions (for example, a golf swing) are created by sequentially overlaying small images obtained by reducing the input image at predetermined field intervals.
It is possible to create still images that are broken down over time.

Such split images are stored in a memory corresponding to the TV screen (for example, called field memory).
It is created by memorizing.

For example, if you want to create one still image by combining arbitrary reduced-node screens, one divided area of memory (for example, the second
Reduced image data of the input composite color video signal (data obtained by thinning out sample points in the horizontal direction and data in which scanning lines are thinned out in the vertical direction) is sequentially overwritten and stored in the area corresponding to small screen 1-1 on the screen shown in the figure. Then, read out that image in real time and project it on the corresponding position 1-1 on the TV screen 1,
When a desired image is found, writing to the memory is stopped by a key operation or the like, and the reduced image of that field is held in the memory. Subsequently, similar operations are sequentially performed on other small screens 1-2 to 1-4, and reduced image data of an arbitrary field is held in each divided area of the memory, thereby creating a set of divided image data.

When performing such split-screen reproduction, conventionally, a composite color video signal is separated into Y-C components, that is, component signals of a luminance signal and a color signal, and then stored in a memory.

[Problem to be solved by the invention]

In devices such as the above-mentioned conventional device, which separate component signals and perform divided image generation processing, there is a structure for separating luminance signals and chrominance signals, and a memory for storing each component signal, and a memory for separately reading out from these memories. This requires a configuration that combines both signals again to produce a composite signal, which has the disadvantage that the configuration for reproducing the image becomes complicated and complicated.

The present invention solves these shortcomings in conventional devices and provides a screen splitting system that can store luminance signals and color signals in memory as composite signals without dividing them, and generate and process divided images. It is intended to provide a control circuit.

[Means to solve the problem]

This invention comprises an A/D conversion means for sampling and A/D converting an input composite color video signal with a clock synchronized in frequency with its color subcarrier, a memory means, and output data of the A/D conversion means. a divided image generation control means for generating divided image data for each field and storing it in the memory means, and reading out the stored divided image data for both the first field and the second field, and storing the divided image data in the memory means. writing system color phase correction means for correcting the phase of the divided image data for each small image so that the phase of the color subcarrier of the divided image data is continuous between each small image; and a first feed from the memory means; ,
A readout system color phase correction means is provided for correcting the phase of the divided image data on a field-by-field basis so that the phase of the color subcarrier of the divided image data commonly read out in the second field is continuous between each field. This is what happens.

[For production]

According to the invention, the input composite color video signal is A
/D conversion means to sample and digitize,
The writing system color phase correction means corrects the phase in small image units and stores it in the memory means, and the divided image data read out from the memory means has the phase corrected in field units by the reading system color phase correction means. The signal is returned to an analog signal by the D/A conversion means. The divided images are reproduced by supplying this analog signal to a television receiver.

By the way, the writing system and reading system color phase correction means are for ensuring continuity of color subcarriers when a color video signal is stored as a composite signal in a memory means to generate divided images. That is, if the small image data are simply connected and stored in the memory means, the color subcarriers between the small images become discontinuous, making it impossible to reproduce colors. Therefore, before storing it in the memory means, the phase of the small image data is corrected by the writing system color phase correction means so that the color subcarriers between the small screens are continuous. Further, the divided image data stored in the memory means is image data for one field, and when this is read out in common for the first field and the second field and displayed on the television screen, the color of the first field and the second field is Since the phase patterns of the subcarriers are shifted by half a period from each other, the entire screen undergoes color inversion every time it shifts from the first field to the second field. The phase of the image data is corrected.

〔Example〕

An embodiment of this invention will be described below. Here, a case will be described in which the LV reproduction signal is subjected to screen division control. First, the principle of screen division control in this embodiment will be explained.

Screen division control is performed by writing small image data in each divided area of the field memory and sequentially reading out the entire field memory.

By the way, in the NTSC color television signal, one screen (one frame) consists of 525 scanning lines, and these are standardized to be displayed on the television screen using interlaced scanning of 2 fields of 262.5 lines each. . Also, the color subcarrier of a color television signal has a frequency fsc
is normalized to fh: horizontal scanning frequency = 15.734263k) [z. As a result of this standardization, the third
As shown in the figure, in each field, the phase of the color subcarrier is inverted for each scanning line. Also, when viewed in field units, the phase pattern of the color subcarrier is reversed when transitioning from the first field to the second field, and the combination of fields and phase patterns is as shown in Figure 3 for 2 frames and 4 fields. The color fields I to IV (these are called color frames) are repeated every time.

In this embodiment, the screen division control is such that the television screen 1 is divided into two vertically and horizontally, respectively, to make a total of four divisions, as shown in FIG. At the time of writing, it is important that the phase pattern of the color subcarrier of each of the four divided car screens 1-1 to 1-4 is continuous at the boundary between adjacent small screens as shown in the same figure, and the image data When writing into the field memory, it is determined whether or not to perform writing-related color phase correction based on the color subcarrier phase pattern of this small image itself.

When applying reduced images in which one field is reduced to 1/4 of the size to each of the four divided screens, the scanning lines are thinned out to 172 in the vertical direction, and the samples are thinned out to 1/2 in the horizontal direction. In this case, if the horizontal direction is thinned out every other sample, colors cannot be reproduced, so the thinning is done in units of one wavelength of the color subcarrier.

Alternatively, instead of thinning out the wavelengths, the average of two adjacent wavelengths may be taken. Furthermore, if the data is thinned out every l scanning lines in the vertical direction, the phase of the color subcarrier of the data will not be inverted twice for each scanning line, so when displayed on a television screen, color inversion will occur for each scanning line. Therefore, every two scanning lines are thinned out by two scanning lines. FIG. 5 shows the process of thinning out in the vertical and horizontal directions, in which the white portions of the waveform of the color subcarrier are thinned out while leaving the blacked-out portions. As a result, reduced image data is generated in which colors can be reproduced and the phase of color subcarriers is inverted for each scanning line.

Furthermore, when trimming a specific area of a field to form a divided image, the color subcarrier phase pattern of the field itself matches the color subcarrier phase pattern of the area to be trimmed, as shown in Figure 6. The area to be trimmed is determined as follows.

In this embodiment, phase correction of image data is performed by delaying the image data. That is, in the writing system, the reference phase pattern of the color subcarrier is determined (
For example, the color subcarrier phase pattern of the small image data first stored in the field memory divided area corresponding to any of the small screens 1-1 to 1-4 is set as the reference phase pattern. ), when storing small image data of a color subcarrier different from this reference phase pattern, this small image data is delayed by the phase difference and sent to the field memory. As a result, the phase difference writing is shifted and stored. As a result, during continuous readout, the color subcarriers are continuous between each small image data.

In addition, 1. In the readout system, the phase pattern of the reference color subcarrier on the output side is compared with the color subcarrier phase pattern of the divided image data read out from the field memory, and if the phases are different, the phase pattern of the reference color subcarrier on the output side is read out from the field memory. The divided image data is delayed by the phase difference and output.

As a result, the reproduced image has continuous color subcarriers between each field.

FIG. 1 showing an embodiment of the present invention will be described.

The input composite color video signal (N'T'SC signal obtained by video demodulating the disc playback signal) is A/D converted by the A/D converter 12. The A/D conversion output is input to a writing system color phase correction circuit 14.

The writing system color phase correction circuit 14 corrects the phase of the image data of the field whose phase pattern is different from the color subcarrier phase pattern of the reference field when generating divided images, and adjusts the color subcarrier between each small image data. This is to ensure that the phase is continuous. The A/D conversion output is output as is except when generating divided images. The output image data of the writing system color phase correction circuit 14 is input to the field memory 16.

The field memory 16 is composed of a RAM and has a capacity to store approximately one field's worth of image data. In the continuous playback mode (normal playback mode), input image data is sequentially overwritten and stored in positions corresponding to the first field and the second field alternately, and read out. The data storage areas of the first field and the second field are shared, and the data storage areas of the first to 262nd scanning lines of the first field are the same as the data storage areas of the 264th to 52nd scanning lines of the second field.
It is also a storage area for each data of five scanning lines.

Note that the field memory 16 does not necessarily have a capacity to store all the image data for one field; for example, the vertical and horizontal synchronizing signal portions can be separately added to the image data read from the field memory 16 later. In that case, it is not necessary to store all of these in the memory, which allows the memory capacity to be reduced.

The F7read memory 16 is commonly used in all playback modes such as continuous playback mode, divided image playback mode, and strobe playback mode (a mode in which still images are generated at predetermined time intervals). These various playback modes are realized by write control of the field memory 16. Read control is always constant regardless of the type of playback mode, and data in the entire memory is read out in order field by field.

The data read from the field memory 16 is input to the video special effect processing circuit 18. Here, input data is processed as a video special effect to create special image data such as mosaic art (video expression like a mosaic painting) or graphic art (video expression like an oil painting). When no video special effects are added, the input data is output as is. The output data of the video special effect processing circuit 18 is input to a readout system color phase correction circuit 20.

The readout system color phase correction circuit 20 is connected to the field memory 16.
The color subcarrier phase of the divided image data is corrected field by field so that the color subcarrier phase of the divided image data read from the field is continuous between fields. In other words, the divided image data for one field stored in the field memory 16 is read out in common for the first field and the second field, but the color subcarrier phase patterns of the first field and the second field are mutually similar to each other. Since there is a shift by the period, the divided image data is shifted by 180° of the color subcarrier each time the first field shifts to the second field. Also, even during continuous playback, the field memory 16
Since the color subcarrier phase of the output data and the phase of the reference color subcarrier SC may be servo-locked in a state where they are in opposite phases to each other, in that case, the read data of the field memory 16 is continuously Shift by half a cycle.

The output data of the readout color phase correction circuit 20 is subjected to D/A conversion by a D/A converter 22, and then sent to a television receiver and displayed on a television screen.

In FIG. 1, the system clock oscillator 10 oscillates a clock MCK for controlling the entire LV player. When the 0 rotation servo and TBC (time base correct) servo are locked, the system clock oscillator 10 generates an input signal as shown in FIG. The color subcarriers of the composite color video signal are frequency synchronized with this master clock MCK. Note that frequency synchronization here means that it is sufficient to be synchronized in terms of frequency, and there is no problem even if they are not completely synchronized in terms of phase. In other words, a predetermined phase difference may be present. The frequency of master clock MCK is set to 2N-fsc (N is a positive integer), where fsc is the color subcarrier frequency, and in this embodiment, it is set to N=2, that is, 4 fsc. The A/D converter 12 uses this master clock MCK to sample the input NTSC composite video signal at a frequency four times that of the color subcarrier. The sampling timing is, for example, 0+α', 90+α", 180+α", 270 of the color subcarrier as shown in FIG.
The timing can be +α0 (α is any value between 0 and less than 90).

The reference timing control circuit 24 outputs the following various reference timing signals based on the master clock MCK.

The reference synchronization signal (reference vertical synchronization signal and reference horizontal synchronization signal) is an output system synchronization signal.

The reference color subcarrier SC is a signal obtained by dividing the master clock MCK by 1/4 as shown in FIG.
It becomes the color subcarrier of the output signal and is used in the color phase correction circuit 14.20 to detect the color subcarrier phase pattern of the write field and the subsequent field.

The write/read switching timing signal is field memory 1
A signal for switching 6 to write mode and read mode.
For example, it is output so that the master clock MCK switches to write mode at the falling edge and to read mode at the rising edge.

Note that the frequency synchronization state between the color subcarrier of the input composite color video signal and the master clock MCK or the reference color subcarrier SC is as described above.
This can be realized by using the master clock MCK as a reference clock for the rotation servo system and the TBC servo system and servo-locking these servo systems.

The successive address signal is a signal that instructs the successive address.
It is given as a value obtained by counting the master clock MCK using the reference synchronization signal as a reference.

The special effect control timing signal is a control signal for applying special effects.

The determination timing signal C is generated by detecting the reference color subcarrier phase pattern of the output system and using this and the field memory 1.
This is a signal that provides judgment timing for comparing the color subcarrier phase pattern of the data read from 6, and is output at a predetermined timing for each field (for example, immediately after the reference vertical synchronization signal and before the start of screen display). Ru.

The write-related timing control circuit 26 is a circuit that outputs determination timing signals A and B and a write address signal. The determination timing signal B is a signal that provides determination timing for detecting the color subcarrier phase pattern of input data. This judgment timing signal B is based on the master clock MCK with reference to the synchronization signal in the input signal.
is counted and output at a predetermined timing within the field (for example, immediately after the reproduced vertical synchronization signal and before the start of screen display).

The determination timing signal A is a signal that provides timing for determining a reference color subcarrier phase pattern when generating divided image data. This determination timing signal A is output at a predetermined timing of the image data (at the same time as the timing signal B), for example, when writing the first small image data into the field memory 16.

Once the determination timing signal A is output, it is not output until the small image data is written in all the divided areas of the field memory 16 and one set of divided image data is completed.

Note that the determination timing signal A is always output simultaneously with the determination timing signal B except when generating divided images. - The write address signal is a signal that indicates the write address of the field memory 16, and these various playback modes are realized by changing the way this write address signal is given in accordance with various playback mode commands. For example, in continuous playback mode, that is, during normal playback, the master clock MCK is counted based on the playback synchronization signal, and the count value is sequentially given as a write address, and this is repeated every time the playback synchronization signal is given.

In strobe reproduction, the master clock MCK is counted based on the reproduction synchronization signal, the counted value is given as a write address for one field, and then the write command is stopped for a predetermined time and this operation is repeated intermittently.

In the divided image reproduction, in the case of a divided image of a reduced image, the write address of the designated divided area of the field memory 16 is given at predetermined scanning line intervals based on the synchronization signal, and at predetermined clock intervals. In the case of a divided image of a trimmed image, the write address of the designated divided area in the field memory 16 is given at each timing of the area to be trimmed based on the synchronization signal.

The RAM control circuit 28 is connected to the field memory 16
It gives write/read commands and address commands to the . The write/read command is given based on a write/read switching timing signal from the reference timing control circuit 24, the mode of the field memory 16 is switched, and an address signal corresponding to the mode is given to the field memory 16. A write or read is performed.

Note that the divided image generation control means is composed of a reference timing control circuit 24, a write system timing control circuit 26, and an Ft AM control circuit 28.

An example of the configuration of the writing system color phase correction circuit 14 is shown in FIG. 8, where the input data is branched into a path 29 through which it passes as is and a path 30 where it is delayed by a half cycle of the color subcarrier (140 ns).

The delay path 30 can be configured with a shift register 32 that shifts input data by N clocks (for example, if the sampling frequency is 4fsc, shifts by 2 clocks) with a sampling frequency of 2N·fsc. These two paths 29, 30 are switched by a switch 34.

The FIP flag generation circuit 36 detects the phase pattern of the color subcarrier of the input field data, and latches the reference color subcarrier SC with the determination timing signal B for each field of input data and outputs the FI
As mentioned above, the 0 judgment timing B output as the P flag is a specific timing within the input data field (for example, the timing immediately after the vertical synchronization signal and before the screen display starts).
The value latched at the same timing is “1”.
' or "On", the color subcarrier phase pattern of that field can be determined.

The FMP flag generation circuit 38 determines the reference phase pattern of the color subcarrier of the divided image data to be stored in the field memory 16 when generating divided images. For example, when storing the first small image data in the field memory 16, the FMP flag generation circuit 38 Reference subcarrier SC is determined by determination timing signal A output at the same timing as timing signal B.
is latched and used as a reference phase pattern of the color subcarrier of the divided image data when writing the small image data to the field memory 16. When the reference subcarrier SC is latched, the output of the determination timing signal A is thereafter stopped until writing of all small screen data is completed.

An exclusive OR circuit 40 compares the outputs of the flag generation circuits 36 and 38, and if they match (that is, if the phase pattern of the color subcarrier of the currently input field data is the same as the reference phase pattern), 0", and if there is a mismatch (i.e., the phase pattern of the color subcarrier of the currently input field data is shifted by half a cycle from the reference phase pattern), it outputs "1".
” is output.

The shift command circuit 42 is configured so that the output of the exclusive OR circuit 40 is “
0”, the switch 34 is connected to the path 29 side, and the
'', the phase correction is performed by connecting to the path 30 side.As a result, the phase of the color subcarrier of the divided image data stored in the field memory 16 becomes continuous between the small images.

An example of the configuration of the readout color phase correction circuit 20 is shown in FIG. 9, which includes a path 49 through which the input data passes as is, and a path 5 in which the input data is delayed by half a cycle (140 ns) of the color subcarrier.
Branched to 0. The delay path 50 can be configured with a shift register 52 that shifts the input data by N clocks (for example, if the sampling frequency is 4fsc, by 2 clocks) with a sampling frequency of 2N-fsc.

These two paths 49, 50 are switched by a switch 54.

The FRP flag generation circuit 56 detects the phase pattern of the reference color subcarrier in the output system, latches the reference color subcarrier SC using the determination timing signal C, and outputs the FRP flag.

The determination timing signal C is a signal that provides the determination timing for detecting the reference color subcarrier phase pattern of the output system, and is determined at a predetermined timing for each field (for example, immediately after the reference vertical synchronization signal and before the start of screen display). Output. The value latched at the same timing is “
The reference color subcarrier phase pattern of the output system can be determined depending on whether it is 1'' or 0.

The exclusive OR circuit 58 compares the FRP flag and the FMP flag (the phase pattern of the color subcarrier of the data stored in the field memory 16), and if they match (that is, the phase pattern of the color subcarrier of the data stored in the field memory 16), If the color subcarrier phase pattern (FMP flag) of the current data is the same as the reference subcarrier phase pattern (FRP flag) of the output system, "0" is output, and if they do not match (that is, the current field memory 1.
If the phase pattern of the color subcarrier of the data being read from 6 is shifted by 180° from the reference subcarrier phase pattern of the output signal), 1'' is output.

The shift command circuit 60 is configured so that the output of the exclusive OR circuit 58 is “
When it is 0'', connect the switch 54 to the path 49 side, and when it is 1''
In this case, it is connected to the path 50 side to perform phase correction. As a result, the color subcarriers of the output data are continuous between fields.

The operation of the embodiment of FIG. 1 is shown in FIGS. 10 to 12. Note that the phase correction circuits 14 and 20 are shown in FIG.
It is assumed that the configuration is as shown in FIG. Figure 10 is the operation during continuous playback, Figure 11 is the operation during strobe playback, and Figure 12 is the operation during continuous playback.
The figure shows the operation when reproducing divided images. In both cases, the rotation servo and TBC servo are locked. At this time, in each operation, the FMP flag, ie, the color subcarrier reference phase pattern of the field memory 16, is determined at the timing of the start position of the field of the input signal (immediately after the vertical synchronization signal and before the start of screen display).

In the continuous reproduction mode of FIG. 11, the FMP flag is synchronized with changes in the color subcarrier phase pattern of the input signal.

A shift command in the readout color phase correction circuit 20 is determined for each field. Judgment timing is FRP
At the same time as the judgment of

That is, after determining the FRP, the FMP flag and the FRP flag are compared. If they match, the read data from the field memory 16 is output as is; however, if they do not match, color reversal will occur if it is output as is, so it is output after being delayed by a half-wave of the color subcarrier. Furthermore, the color subcarrier phase pattern of the output signal with respect to the input signal may be ``■'' or ``■''. In the case of ■, the shift command is no shift, and in the case of ■, it is a constant shift.

During continuous playback, if the input (write) field and the output (read) field do not match the odd-even (first and second), the vertical relationship of the scanning lines will be reversed, so always check the odd-even of the input and output fields. If there is a mismatch, it is immediately corrected so that they match, so an odd-even match is always achieved. (however,
There is a delay of less than one field. ) The strobe playback mode shown in FIG. 12 differs from the continuous playback mode shown in FIG. 11 in that the write field of the field memory 16 is discontinuous. The FMP flag is copied from the FIP flag of the field to be written in the field memory 16, that is, the color subcarrier phase pattern discrimination flag of the input signal, and is held until the next writing.

When the FMP flag and the FRP flag do not match (determined based on the start position of the output signal field), a shift command is issued by the readout system color phase correction circuit 20.

In this case as well, there are cases of ■ and ■ as described above.

Furthermore, since this strobe reproduction mode is an operation in which a specific field is repeatedly reproduced, the input and output fields do not necessarily have to be even or odd, but the figure shows a case where they are.

Actually, no problem occurs because the input fields are limited to either odd or even fields.

In the divided image reproduction mode shown in FIG. 13, a shift command is also issued during writing. That is, first field memory 1
A reference phase pattern of six color subcarriers is determined. As this reference phase pattern, the color subcarrier phase pattern of the small image data written into the field memory 16 first after the generation of divided image data is started is selected.

The determined reference phase pattern (FMP flag) is held until the writing of all small image data is completed, and if the color subcarrier phase pattern of the small image data to be written is different from the reference phase pattern, this small image data is The data is shifted and written into the field memory 16. As a result, the phases of the color subcarriers of all the small image data stored in the field memory 16 become continuous.

A shift command on the read side is issued when the FMP flag and the FRP flag do not match, as in the continuous playback mode and strobe playback mode, regardless of the write side.

This figure also shows the cases of ■ and ■.

Just 1. As will be described later, there may be other cases of different odd-even states, but they are not particularly illustrated here.

This divided image playback mode is also basically a mode in which a specific field is taken in and read out multiple times.The small screens of the 0 divided image are not related to each other in interlaced scanning, so the input and output fields are No odd-even check will be performed. Although the figure shows an odd-even coincidence state, even if a track jump or the like occurs during handling and the odd-even mismatch occurs, no correction is made each time so that the tracks match.

[Example of change]

In the above embodiment, the case of a four-split screen was shown, but the present invention can be applied to the reproduction of divided images with various numbers of divisions. Also,
The number of samples is not limited to 4 samples/1 color subcarrier period, but can be set to various numbers of samples.

In addition, in the music example, the case where the screen division control is performed on the LV playback signal was explained, but in the case of TV broadcasting, V'I''R,
It is also possible to perform screen division control for playback signals such as CDV.

In that case, in addition to incorporating the screen division control circuit into each playback device, it is also possible to configure it as an independent device and perform common screen division control on the playback signals from each playback device.

〔Effect of the invention〕

As explained above, according to the present invention, since the writing system and reading system color subcarrier phase correction means are provided,
Even if the composite color video signal (composite signal) is stored as it is in the memory means, divided images can be obtained with accurate color reproduction.

In particular, in the present invention, sampling is performed using a clock synchronized in frequency with the color subcarrier of the input signal, so phase correction can be performed by data shifting, etc., and phase correction can be performed easily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is an explanatory diagram of divided image reproduction, showing a state in which a television screen is divided into small screens. FIG. 31 is a diagram showing a color frame in the NTSC system. FIG. 4 is a diagram showing an example of screen division positions. FIG. 5 is a diagram showing an example of a method for creating divided images of a reduced image. FIG. 6 is a diagram showing an example of a method for creating divided images of a trimmed image. FIG. 7 is a waveform diagram showing the phase relationship of signals in the embodiments of FIGS. 1, 8, and 9. FIG. 8 shows the writing system color phase correction circuit 1 in FIG.
FIG. 4 is a block diagram showing a specific example of No. 4; FIG. 9 shows the readout system color phase correction circuit 2 in FIG.
0 is a block diagram showing a specific example of 0. FIG. 10 to 12 are time charts showing the operation of the embodiment shown in FIG. 1, respectively, and FIG. 10 is a continuous playback mode,
FIG. 11 shows the strobe playback mode, and FIG. 12 shows the divided image playback mode. 12... A/D converter, 14... Writing system color phase correction circuit, 16... Field memory, 20... Reading system color phase correction circuit, 22... D/A converter, 2
4.26.28...Divided image generation control means, 24...
・Reference timing control circuit, 26...
・Writing system timing control circuit, 28...RA
M control circuit.

Claims (2)

[Claims] (1) A/D by sampling the input composite color video signal with a clock synchronized in frequency with its color subcarrier.
A/D conversion means for converting; memory means; generating approximately one field's worth of divided image data from the output data of the A/D conversion means and storing it in the memory means; divided image generation control means for reading the divided image data in common for the first field and the second field; and dividing the divided image data in units of small images so that the phases of the color subcarriers of the divided image data stored in the memory means are continuous between each small image. A writing system color phase correction means for correcting the phase of the image data, and a phase of the color subcarrier of the divided image data commonly read out from the memory means for the first feed and the second field are continuous between each field. A screen division control circuit comprising readout system color phase correction means for correcting the phase of the divided image data on a field-by-field basis. (2) The sampling frequency in the A/D conversion means is 2N times the frequency of the color subcarrier (N is a positive integer), and the writing system and reading system color phase correction means each shift the data by N clocks. 2. The screen division control circuit according to claim 1, wherein the screen division control circuit performs phase correction by using the phase correction circuit.