JPH01298743A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01298743A JPH01298743A JP12839888A JP12839888A JPH01298743A JP H01298743 A JPH01298743 A JP H01298743A JP 12839888 A JP12839888 A JP 12839888A JP 12839888 A JP12839888 A JP 12839888A JP H01298743 A JPH01298743 A JP H01298743A
- Authority
- JP
- Japan
- Prior art keywords
- alloy
- layer
- wiring
- alloy layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000654 additive Substances 0.000 claims 1
- 230000000996 additive effect Effects 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 abstract description 26
- 239000000956 alloy Substances 0.000 abstract description 26
- 239000000758 substrate Substances 0.000 abstract description 10
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 238000002161 passivation Methods 0.000 abstract description 2
- 229910021074 Pd—Si Inorganic materials 0.000 abstract 3
- 238000013329 compounding Methods 0.000 abstract 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910021364 Al-Si alloy Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 36
- 238000013508 migration Methods 0.000 description 7
- 230000005012 migration Effects 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910001020 Au alloy Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000003353 gold alloy Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229920000742 Cotton Polymers 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 210000003734 kidney Anatomy 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に半導体集積回路用Ａ
ｌ配線の信頼性向上に適用して有効な技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular to an A for semiconductor integrated circuit.
This invention relates to a technique that is effective when applied to improving the reliability of l-wiring.
従来より、半導体基板上に形成される集積回路の配線材
料には、電気抵抗が低い、シリコン（Ｓｌ）酸化膜との
密着性が良い、加工が容易である、などの理由からアル
ミニウム（八りが用いられてきたが、集積回路の高密度
化に伴う配線パターンの微細化とともに、エレクトロマ
イグレーションやストレスマイグレーンヨンに起因する
Ａｌ配線の信頼性低下が顕著になってきた。Traditionally, aluminum has been used as a wiring material for integrated circuits formed on semiconductor substrates due to its low electrical resistance, good adhesion to silicon (Sl) oxide films, and ease of processing. However, as interconnect patterns become finer due to higher density integrated circuits, the reliability of Al interconnects due to electromigration and stress migration has become noticeably lowered.
その対策として、例えば株式会社サイエンスフォーラム
、昭和５８年１１月２８日発行、「超ＬＳＩハンドブッ
クＪＰ１２３〜Ｐ１３０などに記載があるように、Ａｌ
にＳｌやＣｕなどを添加した配線構造や、タングステン
（Ｗ）などの高融点金属またはそのシリサイドとＡｌと
を積層した配線構造などが提案されている。As a countermeasure, for example, as described in the "Very LSI Handbook JP123-P130" published by Science Forum Co., Ltd. on November 28, 1980,
A wiring structure in which Sl, Cu, or the like is added to the metal, and a wiring structure in which a high-melting point metal such as tungsten (W) or its silicide and Al are stacked have been proposed.
本発明者は、上記Ａｌｌ綿線耐エレクトロマイグレーン
ヨン特性や耐ストレスマイグレーション特性について検
討し、Ａｌ−３ｉ合金に約１〜３％程度のパラジウム（
Ｐｄ）を添加した合金を用いることにより、Ａｌ配線の
耐エレクトロマイグレーション特性や耐ストレスマイグ
レーション特性が顕著に向上する、という知見を得た。The present inventor studied the electromigration resistance properties and stress migration resistance properties of the All cotton wire, and determined that approximately 1 to 3% palladium (
We have found that by using an alloy containing Pd), the electromigration resistance and stress migration resistance of Al wiring can be significantly improved.
ところが、その反面、上記Ａβ−Ｐｄ−３ｉ合金は、そ
のボンダビリティが低いために、ＡＲ、ＡｕあるいはＣ
ｕなどからなるワイヤを電極パッドにボンディングする
と、電極パッドとワイヤとの間における接続の信頼性が
低下してしまうという欠点がある。However, on the other hand, the above Aβ-Pd-3i alloy has low bondability, so it cannot be used in AR, Au or C.
Bonding a wire made of U or the like to an electrode pad has the disadvantage that the reliability of the connection between the electrode pad and the wire decreases.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、′電極パッドのボンダビリティを低下
させず、しかも、配線の耐エレクトロマイグレーション
特性や耐ストレスマイグレーション特性を向上させるこ
とのできる技術を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to 'improve the electromigration resistance and stress migration resistance of wiring without reducing the bondability of electrode pads. Our goal is to provide technology that enables
本発明の前記並びにその他の目的と新規な特徴とは、本
明細書の記述および添付図面かろ明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なもののＪｌ
要を簡単に説明すれば、次の通りである。Jl of representative inventions disclosed in this application
A brief explanation of the main points is as follows.
すなわち、下層をＡＲ−Ｐｄ−５ｉからなる第１のΔ１
合金で、また上層をＡｌ−３ｉからなる第２の合金でそ
れぞれ構成した配線構造、または上記第１のＡｌ合金層
と第２のＡβ合金層との間にシリサイド層を介在させた
配線構造を備えた半導体装置である。That is, the lower layer is the first Δ1 made of AR-Pd-5i.
A wiring structure in which the upper layer is made of a second alloy made of Al-3i, or a wiring structure in which a silicide layer is interposed between the first Al alloy layer and the second Aβ alloy layer. This is a semiconductor device equipped with
配線の下層をＡｊ！−Ｐｄ−３ｉ合金で構成することに
より、配線の耐エレクトロマイグレーション特性や耐ス
トレスマイグレーション特性が向上し、上層をＡｌ−３
ｉ合金で構成することにより、ボンダビリティの低下が
防止される。Aj the lower layer of wiring! - By using Pd-3i alloy, the electromigration resistance and stress migration resistance of the wiring are improved, and the upper layer is made of Al-3i.
By using the i-alloy, deterioration in bondability is prevented.
また、上記Ａｌ−Ｐｄ−３ｉ合金層とＡＲ−５１合金層
との間にシリサイド層を介在させることにより、アニー
ル処理の際などに、Ａ Ｊ −Ｐ ｄ −Ｓ１合余生の
ＰｄがＡＲ−３ｉ合金中に拡散してボンダビリティを低
下させるのを防止することができる。In addition, by interposing a silicide layer between the Al-Pd-3i alloy layer and the AR-51 alloy layer, during annealing treatment, the remaining Pd of the AJ-Pd-S1 bond is transferred to the AR-3i It can prevent diffusion into the alloy and deterioration of bondability.
第１図は、本発明の一実施例である半導体装置を示す半
導体基板の要部断面図、第２図は、この半導体基板上に
形成された配線の拡大断面図である。FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged sectional view of wiring formed on this semiconductor substrate.
第１図に示すように、ｐ形シリコン単結晶からなる基板
ｌの主面には、Ｓｉｎ、からなるフィールド＠縁膜２が
形成され、このフィールド絶縁膜２で囲まれた領域には
、ソース・ドレイン電極を構成するｎ形拡散層３と、ポ
リシリコンなどからなるキャパシタ電極４と、同じくポ
リノリコンなどからなるゲート電画５とからなるメモリ
セルが形成されている。As shown in FIG. 1, a field@edge film 2 made of Sin is formed on the main surface of a substrate l made of a p-type silicon single crystal, and a region surrounded by this field insulating film 2 has a source A memory cell is formed of an n-type diffusion layer 3 constituting a drain electrode, a capacitor electrode 4 made of polysilicon or the like, and a gate electrode 5 also made of polysilicon or the like.
上記フィールド絶縁膜２およびメモリセルは、リンケイ
酸ガラス（ＰＳＧ）やホウ素リンケイ酸ガラス（ＢＰＳ
Ｇ）などからなる層間絶縁膜６によって被覆され、この
層間絶縁膜６の表面には、Ａｐ金合金らなる配線７がパ
ターン形成されている。The field insulating film 2 and memory cells are made of phosphosilicate glass (PSG) or boron phosphosilicate glass (BPS).
The surface of the interlayer insulating film 6 is covered with an interlayer insulating film 6 made of G), etc., and wiring 7 made of Ap gold alloy is patterned on the surface of this interlayer insulating film 6.
基板１の最上層には、ＰＳＧやＳ １ｚＮｔかろなるバ
ッ／ベーンヨン膜８が被着され、その一部を開孔して形
成された電極パッド９には、八β１．へＵあるいはＣｕ
などからなるワイヤ１０がボンディングされている。A bag/vein film 8 made of PSG or S1zNt is deposited on the uppermost layer of the substrate 1, and an electrode pad 9 formed by opening a part of the film has 8β1. to U or Cu
A wire 10 consisting of the like is bonded.
上記Ａｆ金合金らなる配線７は、第２図に示すように、
その下層がＡＲに約１％のＳｉと、約１〜３％のＰｄと
を添加したＡｅ−Ｐｄ−３ｉ合金層１１で構成され、上
層がＡｊ＋に約１％のＳｉを添加したＡｌ２−３ｉ合金
層１２で構成された二層構造を有。ている。The wiring 7 made of the Af gold alloy is, as shown in FIG.
The lower layer is composed of an Ae-Pd-3i alloy layer 11 in which approximately 1% Si and approximately 1 to 3% Pd are added to AR, and the upper layer is Al2-3i in which approximately 1% Si is added to Aj+. It has a two-layer structure composed of an alloy layer 12. ing.
このように、配線７の一部をＡＲ−Ｐｄ−５ｉ合金層１
１で構成することにより、配線７の耐エレクトロマイグ
レーション特性や耐ストレスマイグレーション特性が向
上する、という効果が得られる。In this way, a part of the wiring 7 is connected to the AR-Pd-5i alloy layer 1.
1, it is possible to obtain the effect that the electromigration resistance and stress migration resistance of the wiring 7 are improved.
また、このＡＲ−Ｐｄ−３ｉ合金層１１は、上記したＡ
ｊ＋、ＡｕあるいはＣｕなどからなるワイヤ１０に対す
るボンダビリティが低い、という欠点を有しているが、
その上、腎にＡｌ７−５ｉ合金層１２を積層することに
より、１屑パッド９のボンダビリティの低下を防止でき
る、という効果が１１）られる。Further, this AR-Pd-3i alloy layer 11 is made of the above-mentioned A
Although it has the disadvantage of low bondability to the wire 10 made of j+, Au or Cu,
Furthermore, by laminating the Al7-5i alloy layer 12 on the kidney, there is an effect (11) in that deterioration in bondability of the single scrap pad 9 can be prevented.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は、前記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say.
例えば、前記実施例の配線７は、Ａｌ１−Ｐｄ−８】合
金層１１とＡＡ−３ｉ合金層１２との二層構造であるが
、第３図に示すように、ＡＡ−Ｐｄ−３ｉ合金層１１と
、Ａｌ−３ｉ合金層１２との間にＷ Ｓ ｌ １１やＭ
ｏＳｉ、などからなるシリサイド層１３を介在させた三
層構造とすることもできる。For example, the wiring 7 in the above embodiment has a two-layer structure of an Al1-Pd-8 alloy layer 11 and an AA-3i alloy layer 12, but as shown in FIG. 11 and the Al-3i alloy layer 12, W S l 11 and M
A three-layer structure with a silicide layer 13 made of oSi, etc. interposed may also be used.
このようにすると、半導体ウェハのアニール処理の際な
どにＡＡ−Ｐｄ−３ｉ合金層ｌｌ中のＰｄがＡｊ！−５
ｉ合金層１２中に拡散するのを防止することができるた
め、電極パッド９のボンダビリティの低下をより確実に
防止できる、という効果が得られる。In this way, during the annealing process of a semiconductor wafer, the Pd in the AA-Pd-3i alloy layer ll becomes Aj! -5
Since diffusion into the i-alloy layer 12 can be prevented, deterioration in bondability of the electrode pad 9 can be more reliably prevented.
本願において開示される発明のうち代表的なものによっ
て得ちれる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、下層をＡｌ−Ｐｄ−３ｉからなる第１のＡｆ
金合金、また上層をΔ１−３ｉからなる第２のＡＡ金合
金それぞれ構成した配線構造とすることにより、電極パ
ッドのボンダビリティを低下させず、しかも、配線の耐
エレクトロマイグレーション特性や耐ストレスマイグレ
ーション特性を向上させることができる。That is, the lower layer is the first Af made of Al-Pd-3i.
By creating a wiring structure consisting of a gold alloy and a second AA gold alloy consisting of Δ1-3i as the upper layer, bondability of the electrode pad is not reduced, and the electromigration resistance and stress migration resistance of the wiring are improved. can be improved.
また、その際、Δ１−Ｐｄ−３ｉ合金層とＡＡ−５ｉ合
金層との間にシリサイド層を介在させることにより、電
極パッドのボンダビリティの低下をより確実に防止する
ことができる。Further, in this case, by interposing a silicide layer between the Δ1-Pd-3i alloy layer and the AA-5i alloy layer, deterioration in bondability of the electrode pad can be more reliably prevented.
第１図は本発明の一実施例である半導体装置を示す半導
体基板の要部断面図、
第２図はこの半導体基板上に形成された配線の拡大断面
図、
第３図は本発明の他の実施例における半導体基板上に形
成された配線の拡大断面図である。
１・・・半導体基板、２・・・フィールド絶措膜、３・
・・ｎ形拡散層、４・・・キャパンタ電極、５・・・ゲ
ート電極、６・・・層間絶縁膜、７・・・配置１．８・
・・パッシベーション膜、９・・・電極パッド、１０・
・・ワイヤ、１１・・・、へ１−Ｐｄ−３ｉ合金居、１
２・・・ＡＡ−８１合金層、１３・・・シリサイド層。
代理人 弁理士 小 川 勝 男
第１図
第２３ 第３図FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a semiconductor device which is an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view of wiring formed on this semiconductor substrate, and FIG. FIG. 2 is an enlarged cross-sectional view of wiring formed on a semiconductor substrate in Example. 1... Semiconductor substrate, 2... Field safety film, 3.
... N-type diffusion layer, 4... Capantor electrode, 5... Gate electrode, 6... Interlayer insulating film, 7... Arrangement 1.8.
... Passivation film, 9... Electrode pad, 10.
...Wire, 11..., to 1-Pd-3i alloy alloy, 1
2...AA-81 alloy layer, 13... Silicide layer. Agent: Patent Attorney Katsoo Ogawa Figure 1 Figure 23 Figure 3
Claims (1)
であって、前記Ａｌ合金からなる配線の下層を第１のＡ
ｌ合金で、また上層を前記第１のＡｌ合金と異なる添加
元素を用いた第２のＡｌ合金でそれぞれ構成したことを
特徴とする半導体装置。 ２、第１のＡｌ合金層と第２のＡｌ合金層との間にシリ
サイド層を介在させたことを特徴とする請求項１記載の
半導体装置。[Claims] 1. A semiconductor device using an Al alloy as a wiring material of an integrated circuit, wherein the lower layer of the wiring made of the Al alloy is
1. A semiconductor device characterized in that the upper layer is made of a second Al alloy using an additive element different from that of the first Al alloy. 2. The semiconductor device according to claim 1, further comprising a silicide layer interposed between the first Al alloy layer and the second Al alloy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12839888A JPH01298743A (en) | 1988-05-27 | 1988-05-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12839888A JPH01298743A (en) | 1988-05-27 | 1988-05-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01298743A true JPH01298743A (en) | 1989-12-01 |
Family
ID=14983815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12839888A Pending JPH01298743A (en) | 1988-05-27 | 1988-05-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01298743A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100333573B1 (en) * | 1997-02-21 | 2002-06-20 | 가네꼬 히사시 | Semiconductor device having metal alloy for electrodes |
| US7656045B2 (en) * | 2006-02-23 | 2010-02-02 | Freescale Semiconductor, Inc. | Cap layer for an aluminum copper bond pad |
-
1988
- 1988-05-27 JP JP12839888A patent/JPH01298743A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100333573B1 (en) * | 1997-02-21 | 2002-06-20 | 가네꼬 히사시 | Semiconductor device having metal alloy for electrodes |
| US7656045B2 (en) * | 2006-02-23 | 2010-02-02 | Freescale Semiconductor, Inc. | Cap layer for an aluminum copper bond pad |
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