JPH01296870A - Video information reproducing device - Google Patents

Abstract

PURPOSE:To simplify the constitution of the title device and to make it inexpensive by detecting a vertical synchronizing signal in front of and behind a variable delay line with a single equalizing pulse detector and two vertical synchronization detectors. CONSTITUTION:A signal recorded on a high density recording disk 41 is converted into an electric signal by a pickup 42, and its output is produced through a demodulator 43 and a CCD 45 as the variable delay line to eliminate a jitter component. The signals in front of and behind the CCD 45 are respectively inputted to first and second synchronization separators 44 and 46, and thus, the separated synchronizing signals are respectively inputted to first and second vertical synchronization detectors 53 and 58. In addition, the outputs of a first synchronization separator 44 and a first horizontal synchronization extractor 47 are inputted to an equalizing pulse detector 52, and the outputs are inputted to the first and second vertical synchronization detectors 53 and 58. The vertical synchronization signals in front of and behind the CCD 45 are outputted from the first and second vertical synchronization detectors 53 and 58.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reproducing device for reproducing a record carrier on which a video signal is recorded, such as a video disc or a VTR.

2. Description of the Related Art In recent years, playback devices for recording carriers on which video signals are recorded, such as video disc players and VTRs, have become widespread.

In particular, as one of them, laser vision C and below,
(simply referred to as LV) is capable of high-quality playback, and COD
A TBC (time base collector) using a variable delay line such as the above realizes reproduced video with less jitter.

In LT/, which uses TBC to remove jitter, the optical beam is generally jumped during trick play at the vertical synchronization timing before the TBC, and the suit (-imposed) is used at the horizontal and vertical synchronization signals after the TBC. Controls character generation timing.

Therefore, vertical synchronization signals are required before and after the TBC.

An example of the conventional playback device described above will be described below with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of a conventional video information reproducing device. In the figure, 1 is a high-density recording disk, 2 is a pickup, 3 is a demodulator, 4 is a first sync separator, 6 is a COD (variable delay line), 6 is a second sync separator, and 7 is a first sync separator. horizontal synchronization extractor, 8 a first phase comparator, 9 a first servo circuit, 1o a spindle driver, 11 a spindle motor, 12 a first equalization pulse detector, 13
is the first vertical synchronization detector, 14 is the second synchronization separator, 1
5 is a second phase comparator, 16 is a second servo circuit, 17
is a VCO (variable frequency oscillator), 18 is a second equalization pulse detector, 19 is a second vertical synchronization detector, 2Q, 21
．． 22 is a terminal.

FIG. 5 is a detailed diagram of the configuration of an equalization pulse detector and a vertical synchronization detector in a conventional video information reproducing apparatus.

In the figure, 23 is a counter, 24 is a first decoder, 2
5 is the 29th decoder, 26 is the first RS flip 70 block, 27 is the first OR gate, 28 is the second OR gate, 29 is the second RS flip-flop, 3o is the third P
R gate, 31 is monostable multi, 32 is inverter, 3
3 is a fourth OR gate, and 34 is a fifth OR gate.

The operation of the conventional video information reproducing apparatus configured as described above will be explained below.

An FM-modulated video signal is recorded on the high-density recording disk. In FIG. 4, a pickup 2 converts signals recorded on a high-density recording disk 1 into electrical signals. The output FM modulated video signal is input to the demodulator 3. The reproduced signal converted into a video signal by the demodulator 3 is CC
At the same time as being input to D5, it is input to the first sync separator 4.

The output of the first sync separator 4 is a composite sync signal, which is input to the first horizontal sync extractor 7 , the first equalization pulse detector 12 , and the first vertical sync detector 13 .

The first horizontal synchronization extractor 7 extracts only the horizontal synchronization signal from the input composite sync signal and inputs it to the first phase comparator 8 . A reference synchronization signal is input to the other input of the first phase comparator 8, and the phase comparator 8
The output is input to the first servo circuit 9. The output of the first servo circuit 9 is power amplified by a spindle driver 10 to rotate a spindle motor 11.

That is, the spindle motor 11 is controlled so that the frequency and phase of the output signal of the first horizontal synchronization extractor 7 are equal to the frequency and phase of the reference synchronization signal. but,
Due to the characteristics of motors, etc., jitter with high frequency components remains, and that! Until then, high-quality playback output cannot be expected.

The video signal input to the CCD 5 is delayed by about one horizontal time in the CCD 5 and input to the second sync separator 6. The output of the second sync separator 6 is a composite sync signal, which is input to the second horizontal sync extractor 14 , the second equalization pulse detector 18 , and the second vertical sync detector 19 .

The second horizontal synchronization extractor 14 extracts only the horizontal synchronization signal from the input composite sync signal and inputs it to the second phase comparator 16 . The reference synchronization signal is input to the other input of the second phase comparator 15, and the output of the second phase comparator 16 is input to the second servo circuit 16. The output of the second servo circuit 16 causes the VCO 17 to
The oscillation frequency of the CCD 5 changes, and the delay time of the CCD 5 is controlled. That is, the delay time of C1CD5 is controlled so that the frequency and phase of the output signal of the second horizontal synchronization extractor 14 are equal to the frequency and phase of the reference synchronization signal, and as a result, jitter with high frequency components is removed. .

The video signal from which the jitter has been removed is output from the terminal 22. The vertical synchronization signal of the first synchronization separator output detected by the first equalization pulse detector 12 and the first vertical synchronization detector 13 is outputted from the terminal 20 and used for timing control of an external microcomputer, etc. It will be done. The vertical synchronization signal of the second synchronization separator output detected by the second equalization pulse detector 18 and the second vertical synchronization detector 19 is output from the terminal 21, and is used for external timing control such as superimposition. used for.

First equalization pulse detector 12 and first vertical synchronization detector 1
The detailed operation of No. 3 will be explained using FIGS. 5 and 6.

FIG. 6 shows the state of each signal in a conventional video information reproducing device. In FIG. 6, a is a composite sync signal, b is a horizontal sync signal, C is a 25-delay horizontal sync signal, d is a 76-delay horizontal sync signal, e is a first Rs flip-flop output signal, and r is a second RS flip-flop output signal. , g is a vertical synchronization detection output, and h is a monostable multi-output.

In FIG. 5, two blocks surrounded by dotted lines correspond to the first equalization pulse detector 12 and the first vertical synchronization detector 13Vc, respectively.

In FIG. 5, the operation of the counter 23 starts using the horizontal synchronization signal as a trigger. The output of the counter 23 is
The decoder 24 and the second decoder 25 decode the signal and generate pulses (negative polarity) delayed by 26% and 76% with respect to the horizontal synchronizing signal, respectively. (FIG. 6c, d) The first and second decoder outputs are connected to the first RS flip 70.
It is input to the knob 26 and the sixth OR game) 34. Therefore, the output of the first RS flip-flop 2θ becomes as shown in FIG. 6O. The equalization pulse is detected by detecting that the composite sync signal becomes LO while the output of the first RS flip-flop 26 is LO. That is, the output of the second OR gate 2B is the equalization pulse detection output. The first OR gate 27 is a gate for inhibiting this equalization pulse detection. Second RS flip 70
The knob 29 becomes Lo due to the equalization pulse detection output and becomes the third
is input to the OR gate 30 of 3rd OR game) 30
The output of the fourth OR gate 33 is connected to the other input. The composite sync signal and the output of the fifth OR gate 34 are connected to the input of the fourth OR gate 33 . Therefore, the fourth OR gate 33 detects the level of the composite sync signal at times 26t4 and 75t of horizontal synchronization. When the output of the fourth OR gate 33 is 500, it is detected as a vertical synchronization signal, and a vertical synchronization detection signal (negative polarity) is output. The output of the monostable multi 31 is reset by the vertical synchronization detection output and remains at Lo for a certain period of time, as shown in Figure 6. During this period, the second RS7 U-tube flop 29 is set, so its output becomes Hi, and vertical synchronization detection is prohibited, and equalization pulse detection is also prohibited by the first OR gate 27. This is to prevent equalization pulse detection from malfunctioning during the equalization pulse immediately after vertical synchronization (period shown in FIG. 6i).

Second equalization pulse detector 18 and second vertical synchronization detector 1
The same applies to the detailed operation of 9.

Problems to be Solved by the Invention However, in a video information reproducing device having such a configuration,
Since two equalization pulse detectors and two vertical synchronization detectors are required, there is a drawback that the reproducing device cannot be manufactured at low cost.

Means for Solving the Problems In order to solve the above problems, the video information reproducing apparatus of the present invention includes a pickup means for converting a signal recorded on a record carrier into an electrical signal, and a pickup means for reproducing the record carrier. a control means for controlling the speed; a demodulator for demodulating the modulated video signal; a first synchronization extraction circuit for extracting a synchronization signal from the output of the demodulator; a variable delay line that removes jitter components from the output of the variable delay line, a second synchronization extraction circuit that extracts a synchronization signal from the output of the variable delay line, and an output of the first synchronization extraction circuit that The outputs of the equalization period detection circuit that detects something and the second synchronization extraction circuit are set by the outputs of the vertical synchronization period detection circuit that detects that it is a vertical synchronization period and the output of the equalization period detection circuit. It includes a flip-flop that is reset by the output of the synchronization period detection circuit, and a gate circuit that stops the operation of the vertical synchronization period detection circuit while the flip 70 is being reset.

Operation The present invention, with the above-described configuration, can perform the same operation as the conventional example with one equalization pulse detector and two vertical synchronization detectors, and can reduce the number of equalization pulse detectors by one. This makes it possible to provide a cheaper video information reproducing device.

Embodiment Hereinafter, a video information reproducing device according to an embodiment of the present invention will be described.
This will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a video information reproducing apparatus according to an embodiment of the present invention. In the figure, 41 is a high-density recording disk, 42 is a pickup, 43 is a demodulator, 44 is a first sync separator, 46 is a C0D (variable delay line), 46 is a second sync separator, and 47 is a first sync separator. horizontal sync extractor, 48
49 is a first phase comparator, 49 is a first servo circuit, 50 is a spindle driver, 51 is a spindle motor, 62 is an equalization pulse detector, 63 is a first vertical synchronization detector, 64
is a second synchronous separator, 55 is a second phase comparator, 56 is a second o-t-ho circuit, 57 is a vCO (variable frequency oscillator circuit), 58 is a second vertical synchronization detector, 59, 60
．． 61 is a terminal.

FIG. 2 is a detailed diagram of the configuration of an equalization pulse detector, a first vertical synchronization detector, and a second vertical synchronization detector of a video information reproducing apparatus according to an embodiment of the present invention.

In the figure, 62 is a first counter, 63 is a first decoder, 64 is a second decoder, 65 is a first RS flip-flop, 66 is a first OR gate, and 67 is a second OR gate.
R gate, 68 is the second RS flip-flop, 69 is the third OR gate, 7o is the monostable multi, R1 is the inverter, 72 is the fourth OR gate, 73 is the sixth OR gate, 74 is the third OR gate. 2 counter, 75 is the third decoder, 7
6 is a fourth decoder, 77 is a sixth OR gate, 78 is a seventh OR gate, 79 is a third RS flip-flop, and 80 is an eighth OR gate.

The operation of the reproducing apparatus according to one embodiment of the present invention configured as described above will be described below.

An FM-modulated video signal is recorded on the high-density recording disk. In FIG. 1, a pickup 42 converts signals recorded on a high-density recording disk 41 into electrical signals. The output FM modulated video signal is input to the demodulator 43. The reproduced signal converted into a video signal by the demodulator 43 is input to the C0D4s and simultaneously input to the first sync separator 44. The output of the first sync separator 44 is a composite sync signal, and the output of the first horizontal sync extractor 47
is input to the first equalization pulse detector 62 and the first vertical synchronization detector 63. The first horizontal synchronization extractor 47 is
Only the horizontal synchronization signal is extracted from the input composite sync signal and input to the first phase comparator 48. A reference synchronization signal is input to the other input of the first phase comparator 48 , and the output of the first phase comparator 48 is input to the first servo circuit 49 . The output of the first servo circuit 49 is power amplified by the spindle driver 6o and rotates the spindle motor 51. That is, the spindle motor 51 is controlled so that the frequency and phase of the output signal of the first horizontal synchronization extractor 47 are equal to the frequency and phase of the reference synchronization signal.

However, due to the characteristics of the motor, etc., jitter with high frequency components remains, and high-quality reproduction output cannot be expected as it is.

The video signal input to the CCD 45 is delayed by about one horizontal time in the CCD 46 and input to the second sync separator 46 . The output of the second sync separator 46 is a composite sync signal and is input to a second horizontal sync extractor 64 and a second vertical sync detector 58. Second horizontal sync extractor 64
extracts only the horizontal synchronization signal from the input composite sync signal and inputs it to the second phase comparator 66. The reference synchronization signal is input to the other input of the second phase comparator 66, and the output of the second phase comparator 55 is
The signal is input to the second servo circuit 66. The output of the second servo circuit 56 changes the oscillation frequency of the VCO 67,
The delay time of ccnas is controlled. That is, the COD is
45 delay times are controlled, resulting in the removal of high frequency jitter.

The video signal that passes through the CCD 45 and has the jitter removed is
It is output from the terminal 61. The vertical synchronization signal output from the first synchronization separator detected by the equalization pulse detector 62 and the first vertical synchronization detector 63 is output from the terminal 59 and used for timing control of an external microcomputer or the like. The vertical synchronization signal of the second synchronization separator output detected by the equalization pulse detector 62 and the second vertical synchronization detector 68 is outputted from the terminal 6o, and is used for external timing control such as superimposition. .

First equalization pulse detector 12 and first vertical synchronization detector 1
The detailed operation of No. 3 will be explained using FIGS. 2 and 3.

FIG. 3 shows the state of each signal in a video information reproducing apparatus according to an embodiment of the present invention. In FIG. 3, j is the first composite sync signal, k is the second composite sync signal, 1 is the first RS flip-flop output signal, and m is the second composite sync signal.
R87! J tube flop output signal, n is the first vertical synchronization detection signal, 0 is the monostable multi-output wafer p is the third RS flip 70 tube output, and q is the second vertical synchronization detection signal.

In FIG. 2, the three blocks surrounded by dotted lines are the equalization pulse detector 48 and the first vertical synchronization detector 53, respectively.
This corresponds to the second vertical synchronization detector 58.

In FIG. 2, using the first horizontal synchronization signal as a trigger,
The operation of the first counter 62 begins. first counter 6
The output of 2 is sent to a first decoder 63 and a second decoder 64.
decodes, respectively, 26% for the horizontal sync signal.
A pulse (negative polarity) delayed by 76% is generated. The first and second decoder outputs are connected to the first RS flip 70
The signal is input to the knob 66 and the sixth OR gate 73. Therefore, the output of the first RS flip 70 knob 65 is as shown in FIG.
It will look like this. Detection of the equalization pulse is performed using this first RS.
This is done by detecting that the first composite sync signal becomes LO while the output of the flip-flop 66 is LO. That is, the output of the second OR gate 67 is the equalization pulse detection output. The first OR gate 66 is a gate that prohibits this equalization pulse detection. The output of the second RS flip-flop 68 is low due to the equalization pulse detection output.
0 and is input to the third OR gate 69. third o
The other input of the R gate 69 is connected to the output of the fourth OR gate 72 . The input of the fourth OR gate 72 includes the first composite sync signal and the sixth OR gate 72.
The output of gate T3 is connected. Therefore, the fourth O
The R gate 72 detects the level of the composite sync signal at the 25% and 75th horizontal synchronization times.

When the output of the fourth OR gate 72 is Lo, it is detected as a vertical synchronization signal, and the first vertical synchronization detection signal (negative polarity) (
Figure 3 n) is output. The output of the monostable multi-To is reset by the vertical synchronization detection output, as shown in FIG. 3, and remains LO for a certain period of time. Since the RS flip 70 knob 68 of the period tube 2 is set, it becomes Hi, and vertical synchronization detection is prohibited, and equalization pulse detection is also prohibited by the first OR gate 66. This is to prevent equalization pulse detection from malfunctioning during the equalization pulse immediately after vertical synchronization (period shown in FIG. 3r).

At the same time, the output of the third R87 lip-flop 79 becomes Lo due to the equalization pulse detection output, and the output of the eighth OR gate 8
0 (Figure 3 p). The output of the seventh OR gate 78 is connected to the other input of the eighth OR gate 80. The input of the seventh OR gate 78 includes the second
The composite sync signal and the output of the sixth OR gate 77 are connected. On the other hand, the second horizontal synchronization signal is used as a trigger to start the operation of the second counter 4, and the output of the second counter 74 is decoded by the third decoder 76 and the fourth decoder 76, and the respective horizontal synchronization signals are output. In contrast, pulses (negative polarity) delayed by 25 and 76 days are generated. The third and fourth decoder outputs are input to a sixth OR gate 77. Therefore, the seventh OR gate 78 detects the level of the composite sync signal at the 26th and 75th horizontal synchronization times. 7th OR gate 7
When the output of 8 is Lo, it is detected as a vertical synchronization signal and outputs a second vertical synchronization detection signal (negative polarity) (Fig. 3q). Second. The third RS flip-flop 79 is set by the vertical synchronization detection signal, and vertical synchronization detection is prohibited.

As described above, the video information reproducing apparatus according to the embodiment of the present invention includes a pickup, a demodulator, a first sync separator, and a C
OD (variable delay line), a second synchronous separator, a first horizontal synchronous extractor, a first phase comparator, a first servo circuit, a spindle driver, a spindle motor,
an equalization pulse detector, a first vertical synchronization detector, a second synchronization separator, a second phase comparator, a second servo circuit, a VCO (variable frequency oscillator), and a second and a terminal, and the equalization pulse detector further includes a first counter, a first decoder, a second decoder, a first RS flip-flop, and a first OR gate. a second RS flip-flop, a third OR gate, a monostable multi, an inverter, a fourth OR gate, and a sixth The second vertical synchronization detector includes a second counter, a third decoder, a fourth decoder, a sixth OR gate, a seventh OR gate, and a third R of
The S flip-flop, detector, and two vertical synchronization detectors can perform the same operation as the conventional example, and by reducing the number of equalization pulse detectors by one, it is possible to provide a cheaper reproducing device. It becomes possible.

Effects of the Invention As described above, according to the video information reproducing apparatus of the present invention, the pick amplifier means for converting the signal recorded on the record carrier into an electrical signal and the pink up means control the speed at which the record carrier is reproduced. a control means for demodulating the modulated video signal; a first synchronization extraction circuit for extracting a synchronization signal from the output of the demodulator; A variable delay line that removes the synchronization signal, a second synchronization extraction circuit that extracts a synchronization signal from the output of the variable delay line, and an output of the first synchronization extraction circuit that is in the equalization period before the vertical synchronization period. The outputs of the equalization period detection circuit to detect and the second synchronization extraction circuit are set by the outputs of the vertical synchronization period detection circuit and the equalization period detection circuit to detect that it is a vertical synchronization period, and the vertical synchronization period is detected. By providing a flip-flop that is reset by the output of the circuit and a gate circuit that stops the operation of the vertical synchronization period detection circuit while the flip-flop is being reset, one equalization pulse detector and two vertical synchronization detection circuits are provided. The device can detect vertical synchronization signals before and after the variable delay line, making it possible to provide a cheaper video information reproducing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a video information reproducing device according to an embodiment of the present invention, and FIG. 2 is an equalization pulse detector and a first vertical synchronization detector of the video information reproducing device according to an embodiment of the present invention. FIG. 3 is a waveform diagram showing the state of each signal in the video information reproducing device according to the embodiment of the present invention, and FIG. A block diagram showing the configuration of a video information reproducing device, FIG. 5 is a circuit diagram showing details of the configuration of an equalization pulse detector and a vertical synchronization detector in a conventional video information reproducing device, and FIG. 6 is a block diagram showing the configuration of a conventional video information reproducing device. FIG. 3 is a waveform diagram showing the state of each signal in the information reproducing device. 41...High-density recording disk, 42...Pickup, 43...Demodulator, 44...
・First synchronous separator, 45...CCrJ (variable delay line), 46・Second synchronous separator, 47...
...First horizontal synchronization extractor, 48...First phase comparator, 49...First servo circuit, 5o...
... Spindle driver, 51 ... Spindle motor, 62 ... Equalization pulse detector, 63
...First vertical synchronization detector, 64...
Second synchronous separator, 56... Second phase comparator, 56... Second servo circuit, 67...
- VCO (variable frequency oscillator), 58... second vertical synchronization detector, 62... first counter, 63... first decoder, 64...・・・・・・
Second decoder, 65... First RS flip-flop, 66... First OR gate, 67...
...Second OR gate, 68 River...Second RS flip 70 Tsubu, 69...Third OR gate, T
o... Monostable multi, 1... Inverter, 72... Fourth OR gate, 73...
・Fifth OR gate, 4... Second counter, 75... Third decoder, 76...
Fourth decoder, 77...Sixth OR gate,
78...7th OR gate, 79...
3rd RS flip-flop, 8o... 8th O
R gate. Name of agent: Patent attorney Toshio Nakao and 1 other person'
Kui - Poba Q (,

Claims (1)

[Claims] A video information reproducing apparatus for reproducing a record carrier on which a video signal is modulated and recorded, includes a pickup means for converting the signal recorded on the record carrier into an electrical signal, and a speed at which the pickup means reproduces the record carrier. a control means for controlling; a demodulator for demodulating the modulated video signal;
a first synchronization extraction circuit that extracts a synchronization signal from the output of the demodulator; a variable delay line that removes jitter components included in the output of the demodulator; and a first synchronization extraction circuit that extracts a synchronization signal from the output of the variable delay line. an equalization period detection circuit for detecting that the output of the first synchronization extraction circuit is an equalization period before the vertical synchronization period, and an output of the second synchronization extraction circuit , a vertical synchronization period detection circuit that detects that it is a vertical synchronization period, a flip-flop that is set by the output of the equalization period detection circuit and set by the output of the vertical synchronization period detection circuit, and the flip-flop that is reset. a gate circuit that stops the operation of the vertical synchronization period detection circuit while the vertical synchronization period detection circuit is in operation.