JPH01293790A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain satisfactory noise reducing effect with simple circuit constitution by detecting correlation between the adjacent horizontal lines of a carrier chrominance signal and controlling the multiplication coefficient of a multiplier in a noise reducer circuit with the output of this detection. CONSTITUTION:A noise reducer circuit 3 inputs the carrier chrominance signal from a band pass filter 2 and obtains difference between the carrier chrominance signal and a delay signal before 1H by a 1H delaying device 6 and a subtracter 7. Then, a noise component is detected. A multiplication coefficient K is multiplied to this noise component by a multiplier 8 and added with the input chrominance signal. Then, a noise is reduced. On the other hand, the chrominance signal of the filter 2 is supplied to a 1H delaying device 21 of a line correlation detecting circuit 20 and the output signal of the delaying device and the chrominance signal are added. Then, the correlation between the adjacent horizontal lines is detected. The output of an adder 22 is supplied through an amplitude detecting circuit 23 to the circuit 3 and the value of the multiplication coefficient K is controlled. Thus, the noise is satisfactorily reduced with the simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit that reduces noise components in a carrier color signal.

(Prior Art) FIG. 6 is a block diagram showing a conventional video signal processing circuit.

In FIG. 6, for example, an NTS signal coming into input terminal 1
The C-type frequency interleaved composite video signal is supplied to a bandpass filter 2. The bandpass filter 2 is a filter that passes the frequency band of the C signal (carrier color signal) centered on 3.58M clothes. The output signal of the bandpass filter 2 is transmitted to a noise reducer circuit 3.
is supplied to input terminal 4 of.

The noise reducer circuit 3 is a cyclic noise reduction circuit, and an input signal is input to its input terminal 4, and an output signal is taken out from an output terminal 5.
A signal from one day ago is obtained through a 1H delay device 6 that delays it by a horizontal period, and the output of a subtracter 7 that subtracts the input signal from this signal is zero in the case of a correlated C signal.
There is only uncorrelated noise. Multiplier 8
The multiplication coefficient K is multiplied by the multiplication coefficient K, and the adder 9 adds it to the input signal, thereby operating to cancel out the noise component.

Regarding the operating principle of these noise reducers, for example, as described in Takahiko Fukunuki [Digital Signal Processing of Images J (P115-P118) published by Nikkan Kogyo Shimbun, the unit delay operator corresponding to the delay of 1H] Z H
-', the transfer function of the recursive noise resolver is as follows.

H(Z)-(1-K)/(1-KZH-')...
(1) This characteristic is a vertical (IHB) low pass filter.

However, if the phase, color saturation, etc. of the C signal change drastically in the vertical direction, there will be no or very little correlation in the vertical direction, and components other than noise will appear in the output of the subtractor 7. Therefore, it is desirable to set the value of the multiplication coefficient of the multiplier 8 to zero or a small value. Therefore, it is necessary to optimally change the multiplication coefficient K of the multiplier 8 within the range of O≦ and ≦1.

That is, if there is a correlation in the vertical direction, noise is reduced by setting K→1, and if there is no or very little correlation in the vertical direction, noise reduction is given up by setting K→0.

In the case of the noise reducer circuit 3, the value of the multiplication coefficient of the multiplier 8 is set to &1ml by the control signal input to the control signal input terminal 10.

The output signal of the noise reducer circuit 3 is supplied to a color signal processing circuit 11.

The color signal processing circuit 11 includes, for example, a color signal demodulation circuit, a burst gate circuit necessary therefor, an Ace circuit, an APC circuit, a 3.58M power generation circuit, and the like. This color signal processing circuit 11 demodulates the input C signal to obtain a color difference signal (
For example, R-Y and B-Y) are output to the video output circuit.

Further, the frequency-interleaved composite video signal of, for example, the NTSC system, which enters the input terminal 1, is input to a 1-to-1 delay device 12. Subtractor 13. The signal is supplied to a well-known YC separation circuit using a comb filter formed by an adder 14. The output signal of the 1HM extender 12 and the composite video signal input to the input terminal 1 (i.e., the input signal of the 1HN extender 12) are supplied to a subtracter 13, where they undergo subtraction processing, and are converted to C as is well known. A signal (carrier color signal) is obtained.

Further, the output signal of the 1H delay device 12 and the input terminal 1
The incoming composite video signal (i.e., the input signal of the one-day delay unit 12) is supplied to the adder 14 and subjected to addition processing,
As is well known, a Y signal (II times signal) is obtained.

The C signal, which is the output signal of the subtracter 13, is supplied to a low-pass filter 15. The low pass filter 15 has 3
．． 58M)1. This is a filter that passes a frequency band lower than the frequency band of the C signal (carrier color signal) centered on .

Therefore, normally, the output signal of the low-pass filter 15 is zero. However, if there is no or very little vertical correlation of the C signals, cross-color interference from the Y signal to the C signal will occur and an output will appear.

The output signal of the low-pass filter 15 is supplied to an amplitude detection circuit 16. In the amplitude detection circuit 16, amplitude detection is performed using, for example, a diode, and a detection output is obtained.

The Y signal, which is the output signal of the adder 14, is supplied to a band pass filter 17. The band pass filter 17 has 3
．． This is a filter that passes the frequency band of the C signal (l#2 color sending signal) centered around 58 MH.

Therefore, normally, the output signal of the bandpass filter 17 is zero. However, if there is no or very little correlation in the vertical direction of the Y signal, dot interference from the C signal to the Y signal will occur and an output will appear.

The output signal of the bandpass filter 17 is supplied to an amplitude detection circuit 18. In the amplitude detection circuit 18, amplitude detection is performed using, for example, a diode, and a detection output is obtained.

The output signals of the amplitude detection circuit 16 and the amplitude detection circuit 18 are respectively supplied to an adder 19 and subjected to addition processing.

The output signal of the adder 19 is supplied to the control signal input terminal 10 of the noise resolution user circuit 3 and the output signal of the adder 19 is supplied to the control signal input terminal 10 of the noise resolution user circuit 3.
The value of the multiplication factor is controlled.

The output signal of the adder 19 appears when cross color interference, dot interference, etc. exist, that is, when there is no or very little correlation in the vertical direction of the C signal and Y signal. , the value of the multiplication coefficient of the multiplier 8 is controlled to be zero or small, so that an optimum noise reduction effect can be obtained.

(Problem to be Solved by the Invention) However, the conventional video signal processing circuit shown in FIG.
If the signal is a vertical line signal of approximately 3.58MH, Y
Since the signal always outputs 3.58 MI (Z component), the output of the amplitude detection circuit 18 is obtained, so the multiplier 8 malfunctions as if there were no correlation in the vertical direction of the C signal. There was a problem in that the value of the multiplication coefficient was controlled.

The present invention has been made with attention to the above points, and Y
Even if the signal is a vertical line signal of approximately 3.58MHz,
The correlation between adjacent horizontal lines of the carrier color signal can be detected without causing any problems, and the multiplication coefficient of the multiplier of the noise reducer circuit can be controlled using this detection output to optimize the reduction of noise components. Therefore, it is an object of the present invention to provide a video signal processing circuit that can obtain a good noise reduction effect and can be realized with a relatively simple circuit configuration.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides: (1) a video signal processing circuit that separates and processes a luminance signal and a carrier color signal from a frequency interleaved composite video signal; A line correlation detection circuit detects the correlation between adjacent horizontal lines of the carrier color signal, and a noise component is detected by inputting the carrier color signal and obtaining a difference between the signal delayed by the delay device in horizontal period units. a noise reducer circuit that detects the noise component, multiplies the noise component by a multiplication coefficient by a multiplier, and reduces the noise by adding it to the carrier color signal, and the output signal of the line correlation detection circuit Provided is a video signal processing circuit characterized in that the multiplication coefficient of the multiplier of the noise reducer circuit is controlled so that the reduction of noise components is optimized, and the circuit further comprises: A video signal processing circuit that separates and processes a luminance signal and a carrier color signal, respectively, includes a line correlation detection circuit that detects correlation between adjacent horizontal lines of the carrier color signal, and a color subcarrier included in the luminance signal. The frequency component attenuation is 1iq111, and the carrier color signal is inputted to the adaptive processing circuit, which detects the noise component by obtaining the difference from the delayed signal by the delay device with the intermediate horizontal period, and multiplies this noise component. a noise resolution user circuit that reduces noise by multiplying by a multiplication coefficient by a multiplication factor and adding it to the carrier color signal; The amount of attenuation of the color subcarrier frequency component included in the luminance signal is controlled to be optimal, and at the same time, the multiplication coefficient of the multiplier of the noise reducer circuit is controlled by the output signal of the line correlation detection circuit. The present invention provides a video signal processing circuit characterized in that it is configured to include a video signal processing circuit characterized in that it controls m-i so that reduction of noise components is optimal.

(Embodiment) FIGS. 1 to 5 are block diagrams showing embodiments of the video signal processing circuit of the present invention. In the figure, the same components as in FIG. 6 are given the same reference numerals and will be explained.

In FIG. 1, for example, an NTS signal coming into input terminal 1
The C-type frequency interleaved composite video signal is supplied to a bandpass filter 2. The band pass filter 2 is a filter that passes a frequency band of the C signal (carrier color signal) centered at 3.58 MH. The output signal of the bandpass filter 2 is supplied to the input terminal 4 of the noise resolution user circuit 3.

The noise resolution user circuit 3 is a cyclic noise reducer circuit, and an input signal is input to its input terminal 4, and an output signal is taken out from an output terminal 5.
The output of the subtractor 7, which obtains a signal from one day ago via the paper container 6 and subtracts the input signal from this signal, will be zero in the case of a correlated C signal. There is only uncorrelated noise. This noise is multiplied by a multiplication coefficient K in a multiplier 8, and added to the input signal in an adder 9, thereby operating to cancel out the noise component.

Note that this cyclic noise reducer circuit inputs the C signal, detects the noise component by calculating the difference from the immediately preceding delayed signal by 17, multiplies this noise component by a multiplication coefficient by the multiplier, and then inputs the C signal. Although the circuit operates to reduce noise by adding 1' to the signal, a modified version of this circuit or another configuration may be used as long as it performs substantially the same operation.

In the case of the noise reducer circuit 3, the value of the multiplication coefficient of the multiplier 8 is controlled by a control signal input to the ill@signal input terminal 10.

This means that the cyclic coefficient of the cyclic noise reducer circuit is controlled.

The output signal of the noise reducer circuit 3 is supplied to a color signal processing circuit 11.

At the same time, the C signal, which is the output of the bandpass filter 2, is supplied to the one-day delay unit 21 in the line correlation detection circuit 20.

The line correlation detection circuit 20 is a circuit for detecting the correlation between adjacent horizontal lines of the C signal, and includes the 1F-1 delay device 21. Adder 22. It is composed of an amplitude detection circuit 23.

The output signal of the 1H delayer 21 and the output signal of the bandpass filter 2 (II, the input signal of the 1H delayer 21) are supplied to an adder 22 and subjected to addition processing.

Normally, the C signals have opposite phases between adjacent lines, and the output signals of the adder 22 are canceled out and become zero. In this state, there is a correlation between C signals between adjacent lines.

If the phase of the C signal suddenly changes in the vertical direction, there will be no correlation between the C signals between adjacent lines, so even if they are added, they will not become zero, and the output signal of the adder 22 will appear. Become.

The output signal of the adder 22 is supplied to an amplitude detection circuit 23. In the amplitude detection circuit 23, amplitude detection is performed using, for example, a diode, and the detected output is 11.

The output signal of the amplitude detection circuit 23 is supplied to the control 2Il signal input terminal 10 of the Soizredue 9 circuit 3,
The value of the multiplication coefficient of the multiplier 8 is controlled.

Therefore, when the phase of the C signal suddenly changes, there is no correlation between the C signals between adjacent lines, so the detection output of the amplitude detection circuit 23 is obtained, and the multiplier 80
It operates so that a good noise reduction effect can be obtained by controlling the value of the multiplication coefficient to be zero or small.

In the case of the embodiment of the present invention shown in FIG. 1, even if the Y signal is a vertical line signal of approximately 3.58 MH, this does not pose a problem because it is detected using the C signal.

FIG. 2 is a block diagram showing another embodiment of the video signal processing circuit of the present invention. In the figure, the same components as in FIG. 1 are given the same reference numerals and will be explained.

In FIG. 2, for example, an NTS signal coming into input terminal 1
The C-system frequency interleaved composite video signal is processed by the YC separation circuit 24 into a Y signal (Xi degree multiplied signal and C
They are separated into signals (carrier color signals). The C signal output from the YC separation circuit 24 is supplied to the bandpass filter 2.

Thereafter, the output signal of the amplitude detection circuit 23 operates in the same manner as shown in FIG.
The value of the multiplication coefficient of the multiplier 8 is controlled. The output signal of the amplitude detection circuit 23 is affected when there is no or very little correlation in the vertical direction of the C signal, so in this case, the value of the multiplication coefficient of the multiplier 8 is set to zero or a small value. It is controlled so that

On the other hand, the Y signal output from the YC separation circuit 24 is supplied to a luminance signal processing circuit 25.

The output signal of the luminance signal processing circuit 25 is supplied to a video output circuit 27 via an adaptive processing circuit 26 whose operation will be described later. The video output circuit 27 includes the color signal processing circuit 11
The incoming color difference signals and Y signals are matrix-synthesized to produce three primary color signals R and G.

B is generated, amplified, and output to the CRT 28.

Here, the output signal of the amplitude detection circuit 23 is also supplied to an adaptive processing circuit 26. The adaptive processing circuit 26 is a circuit that inserts a trap of, for example, 3.58 MH into the Y signal only during the period when the output signal of the amplitude detection circuit 23 exists.

Therefore, when the phase of the C signal suddenly changes, since there is no correlation between the C signals between adjacent lines, the detection output of the amplitude detection circuit 23 is obtained, and a trap of 3.58 MH is inserted. Ru. As a result, the color subcarrier frequency component of 3.58 MH mixed in the Y signal is attenuated, and the dot interference is removed. In addition, the other Y signal components are
Since the signal is not affected and is supplied to the video output circuit 5, there is no deterioration in resolution.

Therefore, according to the embodiment of the video signal processing circuit of the present invention shown in FIG. 2, optimal noise reduction can be performed on the C signal, and at the same time, dot interference on the Y signal can also be removed.

FIG. 3 is a block diagram showing another embodiment of the video signal processing circuit of the present invention. In the figure, the same components as in FIGS. 1 and 2 are given the same reference numerals and will be explained.

In FIG. 3, the difference from FIGS. 1 and 2 is the line correlation detection circuit 29, which detects the line correlation of the Y signal instead of the C signal.

When the vertical correlation of the C signal disappears, the vertical correlation of the Y signal also disappears in most cases, so there is no problem even if the Y signal is used for detection.

The Y signal output from the YC separation circuit 24 is supplied to a luminance signal processing circuit 25 and, at the same time, to a bandpass filter 30 in a line correlation detection circuit 29. The bandpass filter 30 is a filter that passes the frequency band of the C signal centered at 3.58 MH.

The line correlation detection circuit 29 includes a bandpass filter 30 .
1H delay device 21. Subtractor 31. It is composed of an amplitude detection circuit 23.

The output signal of the bandpass filter 30 is transmitted to the 1H delay device 2.
1. The output signal of the one-day delay device 21 and the output signal of the bandpass filter 3o (i.e., the IHn
The input signal @) of the extender 21 is supplied to the subtracter 31 and subjected to subtraction processing.

Normally, the Y signals are in phase between adjacent lines, and the output signal of the subtracter 31 is canceled out and becomes zero.

If the phase of the C signal suddenly changes in the vertical direction, the Y
The line correlation of the signals also disappears, and the signal does not become zero even after subtraction, and the output signal of the subtracter 31 appears.

The output signal of the subtracter 31 is supplied to the amplitude detection circuit 23. In the amplitude detection circuit 23, amplitude detection is performed using, for example, a diode, and a detection output is obtained.

As in the case of FIGS. 1 and 2, the amplitude detection circuit 23
The output signal is supplied to the control signal input terminal 10 of the noise reducer circuit 3, and operates to control the value of the multiplication coefficient of the multiplier 8 to obtain a good noise reduction effect.

In the case of the embodiment of the present invention shown in FIG. 3, even if the Y signal is a vertical line signal of approximately 3.58 MH, the subtracter 31 is in phase with the Y signal between adjacent horizontal lines. The output of is canceled and does not appear, and there is no malfunction.

Furthermore, in the embodiment shown in FIG. 3, the Y signal is used instead of the C signal.
Since it is detected using a signal, it can be used even when it is integrated into an IC and there is no outlet for the C signal.

FIG. 4 is a block diagram showing another embodiment of the video signal processing circuit of the present invention. In the figure, the same components as in FIGS. 1, 2, and 3 are given the same reference numerals and will be explained.

In Figure 4, the differences from Figures 1, 2, and 3 are as follows:
This is a part of the line correlation detection circuit 32.

A frequency-interleaved composite video signal of, for example, the NTSC system, which enters the input terminal 1, is supplied to a 1H delay device 21 in a line correlation detection circuit 32.

The line correlation detection circuit 32 detects 1 to 1'! 5 extension device 33°21, subtractor 31. Bandpass filter 30. Adder 22
．． It is composed of an amplitude detection circuit 23.

The output signal of the 1-day delay device 33 and the composite video signal input to the input terminal 1 (i.e., the input signal of the 1-day delay device 33) are supplied to a subtractor 31, where they are subjected to subtraction processing, and the well-known The C signal can be obtained as shown below.

The C signal, which is the output signal of the cylinder reducer 31, is supplied to a band pass filter 30. The bandpass filter 30 includes 3
．． This is a filter that passes the frequency band of the C signal centered around 58MH2.

The output signal of the bandpass filter 30 is supplied to a delay device 21. an output signal of the 1H delay device 21;
The output signal of the bandpass filter 30 (i.e., the input signal of the 1T delay device 21) is supplied to an adder 22,
Addition processing is performed.

Normally, C(LiM) has opposite phases between adjacent lines, and the output signals of the adder 22 are canceled and become zero.

In this state, there is a correlation between C signals between adjacent lines.

If the phase of the C signal suddenly changes in the vertical direction, there will be no correlation between the C signals between adjacent lines, so even if they are added, they will not become zero, and the output signal of the adder 22 will appear. .

The output signal of the adder 22 is supplied to an amplitude detection circuit 23. In the amplitude detection circuit 23, amplitude detection is performed using, for example, a diode, and a detection output is obtained.

In the first embodiment shown in FIG. 4, since the detection is performed using a composite video signal instead of a C signal, it can be applied to an IC circuit, and a good noise reduction operation can be performed.

Furthermore, in FIG. 4, it goes without saying that the positions of the bandpass filter 30, the 1H delay device 33 and the subtracter 31, the 1H delay device 21, and the adder 22 may be interchanged.

Here, the 1H delay device 33 and subtractor 31 in FIG.
The transfer function Z1 of the circuit composed of
As is well known, ω) is expressed as follows.

Z+(ω)=1-Z-1...■ Z 2 (ω) = 1 +Z'
-(3) Therefore, the overall transfer function ZA(ω) is 2^(ω)=71(ω
)・Z2(ω) =1−Z'2...G1) It can be seen that this is the transfer function of a circuit composed of a two-day delay device and a subtractor.

Based on this principle, the embodiment of FIG. 5 is realized.

To explain only the parts in Fig. 5 that are different from Fig. 4,
The composite video signal coming into the input terminal 1 is fed to a bandpass filter 30 in a line correlation detection circuit 32. The bandpass filter 30 is a filter that passes the frequency band of the C signal centered at 3.58 MH.

The line correlation detection circuit 34 includes a bandpass filter 30 .
2H delay device 35. Subtractor 31. It is composed of an amplitude detection circuit 23.

The C signal, which is the output signal of the bandpass filter 30, is
2+-1711 is supplied to the spreader 35.

Said 2Hi! ! The output signal of the extender 35 and the output signal of the bandpass filter 30 (ie, the input signal of the 2H'8 extender 35) are supplied to a subtracter 31 and subjected to tube reduction processing.

As explained above, since the output signal of the subtracter 31 in FIG. 5 is the same as the output signal of the adder 22 in FIG. 4, the output signal of the subtracter 31 in FIG. It becomes zero when the signals are correlated.

If the phase of the C signal suddenly changes in the vertical direction, there will be no correlation between the C signals between adjacent lines, so that the output signal of the subtracter 31 will appear.

The output signal of the subtracter 31 is supplied to the amplitude detection circuit 23. In the amplitude detection circuit 23, amplitude detection is performed using, for example, a diode, and a detection output is obtained.

In the embodiment shown in FIG. 5 as well, since the detection is performed using a composite video signal instead of a C signal, it can also be applied to an IC circuit, and it is possible to perform a good dot interference removal operation.

The embodiment shown in FIG. 5 does not require an adder compared to the embodiment shown in FIG. 4, has a simpler circuit configuration, and can be realized at lower cost.

Further, in FIG. 5, the positions of the bandpass filter 30, 2H delay device 35, and subtractor 31 may be exchanged.

Note that the line correlation detection circuit 20 in FIG. 2 is replaced by the line correlation detection circuits 29 and 32 in the embodiments in FIGS.
．． Of course, it may be used interchangeably with No. 34.

Note that the noise reducer circuit according to the present invention is not limited to the circuit shown in FIG. 1, and may have another configuration that operates substantially in the same way.

Furthermore, it goes without saying that the 1-day delay device in the noise resolution user circuit in the embodiments of FIGS. 1 to 5 may in principle be a horizontal period unit delay device such as a 2-day delay device. .

Further, the line correlation detection circuit according to the present invention is illustrated in FIGS.
The present invention is not limited to the one shown in the embodiment of FIG. 5, and other configurations may be used as long as the correlation between substantially adjacent horizontal lines is detected.

Further, although the above embodiment is a case in which the present invention is applied to an analog video signal processing circuit, the present invention can also be applied to a video signal processing circuit using digital signal processing.

(Effects of the Invention) The video signal processing circuit of the present invention has the above-described configuration, and even when the Y signal is a vertical line signal of approximately 3.58 M, it can perform the above-mentioned processing without causing any trouble. The correlation between adjacent horizontal lines of the carrier color signal can be detected, and the multiplier coefficient of the noise reduction circuit can be controlled using this detection output to optimize the reduction of noise components, resulting in good noise reduction. This has extremely excellent practical effects, such as the reduction effect, the ability to remove dot-I disturbances in the Y signal as needed, and the fact that it can be realized with a relatively simple circuit configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 5 are block diagrams showing embodiments of the video signal processing circuit of the present invention, and FIG. 6 is a block diagram of the conventional video signal processing circuit. 1... Composite video signal input terminal, 2, 17.30...
Bandpass filter, 3... Noise reducer circuit, 4
... Input terminal of noise reducer circuit, 5 ... Output terminal of noise resolver circuit, 6.12.21゜33.
...1 to 1 delay device, 7.13.31...subtractor, 8.
・Multiplying device, 9.14.19.22... Addition device, 10
...Noise reducer circuit control signal input terminal, 11
...color signal processing circuit, 15...low-pass filter,
16.18.23...Amplitude detection circuit, 20.29°3
2.34...Line correlation detection circuit, 24...YC
Separation circuit, 25... Luminance signal processing circuit, 26... Adaptive processing circuit, 27... Video output circuit, 28... C
RT, 35...2H delay device, K...multiplication coefficient. Patent applicant Representative of Victor Japan Co., Ltd.

Claims (2)

[Claims] (1) In a video signal processing circuit that separates and processes a luminance signal and a carrier color signal from a frequency interleaved composite video signal, line correlation detection detects the correlation between adjacent horizontal lines of the carrier color signal. The circuit inputs the carrier color signal, detects a noise component by obtaining a difference between the signal delayed by the delay device in horizontal period units, multiplies this noise component by a multiplication coefficient by a multiplier, and then outputs the carrier color signal. and a noise reducer circuit that reduces noise by adding the line correlation detection circuit, and the output signal of the line correlation detection circuit adjusts the multiplication coefficient of the multiplier of the noise reducer circuit to optimize the reduction of noise components. A video signal processing circuit characterized in that it is controlled as follows. (2) In a video signal processing circuit that separates and processes a luminance signal and a carrier color signal from a frequency interleaved composite video signal, line correlation detection detects the correlation between adjacent horizontal lines of the carrier color signal. an adaptive processing circuit that controls the amount of attenuation of a color subcarrier frequency component included in the luminance signal; and an adaptive processing circuit that inputs the carrier color signal and obtains a difference between the carrier color signal and the signal delayed by the delay device in horizontal period units. a noise reducer circuit that detects a noise component, multiplies the noise component by a multiplication coefficient by a multiplier, and reduces the noise by adding it to the carrier color signal, and the output of the line correlation detection circuit The attenuation amount of the color subcarrier frequency component included in the luminance signal of the adaptive processing circuit is controlled to be optimum by the signal, and at the same time, the multiplication of the noise reducer circuit is controlled by the output signal of the line correlation detection circuit. A video signal processing circuit characterized in that a multiplication coefficient of a multiplier is controlled to optimally reduce noise components.