JPH01293418A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the driving load of a bus driver included in a function module by providing a selection gate between a function module and a common bus. CONSTITUTION:Respective types of function modules like a microprocessor 1, a DMAC2, a RAM 3 and a ROM 4 are connected through selection gates Gd1-Gd4 and Ga1-Ga4 to a common bus like an internal data bus DB and an internal address bus AB. The selection gates Gd1-Gd4 and Ga1-Ga4 are opened and closed and controlled in accordance with the action selecting condition of a function module corresponding to respective ones. Consequently, since the action-selected function module only is selected and controlled to conduction toward a common bus, a bus driver included in the action-selected function module does not need to drive the signal wiring and the input gate capacity in the function module in which the action is not selected then. Thus, the driving load of the bus driver included in the function module can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit and a technique for reducing the signal load of a common bus therein. be.

[Prior art]

In a semiconductor integrated circuit, such as a single-tube microcomputer, in which a large number of functional modules are formed on one semiconductor substrate, each functional module connected to a common bus has a bus driver and a bus receiver. When an operation is selected, the included bus driver drives a predetermined signal line included in the common bus, and this drive level is taken in by the bus receiver in the other functional module.

An example of a document describing a single-chip microcomputer is "rHD64180 User's Manual" published by Nisjun Seisakusho in March 1985.

[Problem to be solved by the invention]

Incidentally, the signal wiring within each functional module coupled to the common bus, the input capacitance of the bus receiver, etc. constitute an undesirable load for various bus drivers.

Therefore, the bus driver included in a predetermined function module whose output operation to the common bus is selected will be affected by the capacitance and resistance components of the signal wiring included in other function modules whose operation is not selected, as well as the bus driver. It is also necessary to drive the input capacitance of the receiver, causing a delay in data input/output operations between each functional module.

To solve this problem, it is possible to increase the transistor size of the bus driver to improve its drivability. However, this increases the chip area and increases the power consumption required for charging and discharging when driving the load. In addition, there was a problem in that the relatively large charging/discharging current flowing through the signal wiring caused noise and electromigration. Such problems become more prominent as the degree of integration of LSI increases.

An object of the present invention is to provide a semiconductor integrated circuit that can reduce the driving load of a bus driver included in a functional module.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit formed by connecting a plurality of functional modules including a bus driver and a bus receiver to a common bus, there is an opening/closing control between the functional module and the common bus depending on the operation selection state of the functional module. In this case, a selection gate is provided.

[For production]

According to the above means, only the functional module selected for operation is selectively controlled to be conductive to the common bus, so that the bus driver included in the functional module selected for operation is not selected for operation at that time. It is no longer necessary to drive the signal wiring and input gate capacitance inside the functional module, which reduces the driving load on the bus driver included in the functional module, thereby reducing the size of bus driver transistors. This reduces the current flowing through the signal wiring, thereby achieving low power consumption and prevention of noise and electromigration.

〔Example〕

FIG. 1 shows a block diagram of a single-chip microcomputer that is an embodiment of the present invention. The single-chip microcomputer shown in the figure is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

The single-chip microcomputer shown in FIG. 1 includes, although not particularly limited to, a microprocessor 1, a DMAC (direct memory access controller) 2, and a RAM (random access memory) 3.
, and peripheral function modules such as ROM (read-only memory) 4, which are coupled to an internal data bus DB and an internal address bus AB, which are typically shown as a common bus. processor 1,
Bidirectional selection gates G are provided between the data input/output terminals of DMAC2 and RAM3 and the internal data bus DB, respectively.
d1. A unidirectional selection gate Gd is interposed between the data output terminal of the ROM 4 and the internal data bus DB. Similarly, a unidirectional selection gate Ga□ is provided between the address output terminals of the microprocessor 1 and DMAC 2 and the internal address bus AB.

Furthermore, unidirectional selection gates Ga, Ga4 are interposed between the address input terminals of the ROM3 and RAM4 and the internal address bus AB.

Note that the internal data bus DB and internal address bus AB
can be interfaced with the outside through a port not shown.

The above various selection gates Gd~Gd4 and Ga~Ga,
The opening/closing control is controlled according to the operation selection state of the functional module to which it is coupled, and the opening/closing control is not particularly limited, but it is controlled by the output of the address decoder 5, which forms the selection signal for the bus slave module. , based on the output of the bus arbiter 6 for arbitration of bus rights between bus master modules.

That is, the bus arbiter 6 receives the bus request signal BREQz output from the DMAC 2 and the bus request signal BREQ output from the microprocessor 1, and determines whether these signals are asserted to high level early or late. Arbitration for bus usage requests is performed based on the following information. When the bus right is given to the microprocessor 1, the bus acknowledge signal BACK is asserted to a high level during that period, and when the bus right is given to the DMAC 2, the bus acknowledge signal BACK2 is asserted to a high level during that period. At this time, the bus acknowledge signal BACK also serves as a control signal for the selection gates Gd, Ga, for the microprocessor 1, and controls the selection gates Gd, Ga1 only while it is asserted at a high level. Switch control to on state.

Therefore, when the microprocessor 1 has acquired the bus right, the data input/output terminal of the microprocessor 1 is connected to the internal data bus DB, and the address output terminal of the microprocessor 1 is connected to the internal address AB. . Similarly, the bus acknowledge signal BACK also serves as a control signal for the selection gates Gd, . . . Ga, coupled to the DMAC2, and switches the selection gates Gd, . do.

Therefore, when DMAC2 has acquired the bus right, the data input/output terminal of DMAC2 is connected to the internal data bus DB.
The address output terminal of DMAC2 is made conductive to the internal address AB.

The address decoder 5 decodes the address signal output from the microprocessor 1 or DMAC 2 which has acquired the bus right, and forms chip selection signals C8I and C32 for the RAM 3, ROM 4, etc. The chip selection signal C5I is R due to its asserted high level.
It instructs the operation of AM3, thereby controlling the inside of RAM3 to be in an operable state. The above chip selection signal C32
is the high level that is the assert level.
, thereby controlling the inside of the ROM 4 to be in an operable state. At this time, the chip selection signal C
3I are selection gates G d, , Ga for RAM3
, and serves as a control signal for these selection gates Gd3tG only during the period when this signal is asserted at a high level.
Control the switch to turn on a3. therefore,
RAM by microprocessor 1 or DMAC:2
3 is accessed, the data input/output terminal of RAM3 is made conductive to the internal data bus DB, and
The address input terminal of is made conductive to internal address AB. Similarly, the chip selection signal C82 is applied to the selection gate Gd4. Also serves as a control signal for G a4,
These selection gates G d4. Control the switch to turn on G a4. Therefore, microprocessor 1 or DM
When ROM4 is accessed by AC2, R
The data output terminal of OM4 is made conductive to internal data bus DB, and the address input terminal of ROM4 is made conductive to internal address AB.

be made into

Here, inside each of the functional modules 1 to 4, there are internal signal wirings connected to the internal address bus AB and internal data bus DB via the selection gates, and a bus driver and a bus receiver are connected to these wirings. There is. For example, a functional module 1 regarding predetermined common signal lines CLd and CLa included in internal data bus DB and internal address bus AB.
, 3゜4 where an example of the connection relationship is representatively shown.
As shown in the figure, the internal signal wiring IL of the microprocessor 1
d□ has a bus driver 1 such as a data output buffer.
0, a bus receiver 11 such as a data manual buffer, and a bus driver/receiver 12 such as a data input/output buffer, respectively.

In addition, the internal signal wiring lLa0 of the microprocessor 1 includes a bus driver 13 such as an address output buffer.
are combined. Similarly, internal signal arrangement I of RAM3
A bus driver/receiver 14 such as a data input/output buffer is coupled to Ld, and a bus receiver 15 such as an address input buffer is coupled to the internal signal line ILa of the RAM 3. Similarly, a bus driver 16 such as a data output buffer is coupled to the internal signal line ILd4 of the ROM4, and a bus receiver 17 such as an address input buffer is coupled to the internal signal line lLa4 of the ROM4. .

Next, an example of the operation of the single-chip microcomputer in this embodiment will be explained.

For example, when the microprocessor 1 accesses the ROM 4, the bus acknowledge signal BAC is asserted in response to the microprocessor 1 acquiring the bus right.
K1 controls selection gates Gd1 and Ga1 to be in the on state. In this state, microprocessor 1 is in ROM4
When an address signal for accessing is output to the internal address bus AB, the address decoder 5 decodes this and sets the chip selection signal C82 to high level.
Cert. This high level chip selection signal C82 controls the selection gates Gd4 and Ga for the ROM4 to be on.

When the microprocessor 1 accesses the ROM 4, the selection gates Gd, GC2°Gd5pGaz for other functional modules whose operation is not selected, ie, according to this embodiment, the DMAC2 and the RAM3 are turned off.

Therefore, when the bus driver 13 included in the microprocessor 1 outputs an address signal, the input capacitance of the internal signal wiring lLa3 and the bus receiver 15 included in the RAM 3 and the input capacitance of the internal signal wiring and bus receiver included in the DMAC 2 are This does not constitute an undesirable load for the bus driver 13. Similarly, ROM
When the bus driver 16 included in the RAM 3 outputs read data, the internal signal wiring ILd included in the RAM 3 and the input capacitance of the bus driver/receiver 14 as well as the DM
The internal signal wiring included in AC2 and the input capacitance of the bus receiver and bus driver/receiver are the same as the bus driver 16.
This will not constitute an undesirable load for the operator.

In this way, only the functional module selected for operation is selectively controlled to be conductive to a common bus such as the internal data bus DB or the internal address bus AB, so that the bus driver included in the functional module selected for operation is There is no need to drive the signal wiring, input gate capacitance, etc. inside the functional module whose operation is not selected, thereby reducing the driving load on the bus driver included in the functional module.6 According to the above embodiment. In this case, the following effects can be obtained.

(1) Microprocessor 1, DMAC2, RAM3,
and various functional modules such as ROM4 are connected to common buses such as internal data bus DB and internal address bus AB via selection gates Gdz~GcLtGa,~GC4, and these selection gates Gd~ Gd4
tGa□ to Ga4 are controlled to open and close according to the operation selection state of the corresponding function module, so that only the function module whose operation is selected is selectively controlled to be conductive to the common bus. This eliminates the need for the bus driver included in the functional module whose operation is selected to drive the signal wiring and input gate capacitance inside the functional module whose operation is not selected at that time. The driving load of the bus driver included in the bus driver can be reduced.

(2) As a result of the above effects, the size of the bus driver transistor can be reduced and its drivability can be relatively reduced without sacrificing the driving speed for the common bus.

(3) According to the above effect (2), by reducing the size of the bus driver transistor, it is possible to reduce the proportion of the chip occupied by such a drive transistor.

(4) From the above effect (2), it is possible to reduce the charging and discharging current flowing through the signal wiring when driving the common bus,
Thereby, it is possible to achieve low power consumption, and it is also possible to prevent the occurrence of noise and electromigration that cannot be substantially ignored.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, the bus master module is a microprocessor and DMAC, and the bus slave modules are RAM and ROM, but other functional modules such as a timer and communication interface controller can be added or replaced as appropriate to create a single chip. A microcomputer can be configured. Further, a selection gate can also be provided for the control bus as a common bus.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to a single-chip microcomputer, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can be widely applied to various data processing LSIs such as digital signal processing processors, and various other semiconductor integrated circuits. Can be applied to conditions that are combined. In this case, the functional module is a microprocessor or DM.
This does not mean only a relatively large unit block that can be integrated into an LSI, such as an AC or even a RAM, but the logical scale and circuit scale can be determined arbitrarily as long as the unit block can perform a unified function as a whole. It can be understood as something that has the property of being able to do something.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, since a selection gate is provided between the functional module and the common bus, the opening and closing of which is controlled according to the operation selection state of the functional module, the functional module that is not selected for operation is electrically disconnected from the common bus, so that it cannot be operated. The bus driver included in the selected functional module does not need to drive the signal wiring or input gate capacitance inside the functional module whose operation is not selected at that time. It is possible to reduce the driving load of the bus driver, and furthermore, by reducing the size of the bus driver transistor,
The current flowing through the signal wiring is reduced, resulting in low power consumption and prevention of noise and electromigration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a single-chip microcomputer that is an embodiment of the present invention, and FIG. 2 is a circuit diagram representative of an example of the coupling relationship of functional modules regarding a predetermined common signal line included in a common bus. It is a diagram. 1...Microprocessor, 2...DMA, 3~R
AM, 4...ROM, 5...Address decoder, 6
...Bus arbiter, AB...Address bus, DB.
...Data bus, CLd, CLa...Common signal line, G
d1~G d4. G a, ~G a4-selection gate,
C3I, C82...Chip selection signal, BACK, B
ACK, ... bus acknowledge signal, 10, 13, 1
6...Bus. Driver, 11, 15, 17... Bus receiver, 12
．． 14...Bus driver/receiver, ILd. ILd,,ILd,,ILa,,lLa3. lLa4・
・Internal signal wiring.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit formed by connecting a plurality of functional modules including a bus driver and a bus receiver to a common bus, an operation selection state of the functional module is provided between the functional module and the common bus. A semiconductor integrated circuit characterized by having a selection gate whose opening and closing are controlled according to the conditions. 2. The selection gate for a functional module to be a bus slave is controlled based on an address signal for selecting the functional module, and the selection gate for a functional module to be a bus master module is controlled based on a bus arbitration signal. 2. A semiconductor integrated circuit according to claim 1, wherein said semiconductor integrated circuit is controlled by said component.