JPH01292471A - Simulation system for logical circuit - Google Patents

Abstract

PURPOSE:To monitor an oscillation state at the time of simulating a logical circuit by providing the title system with a means for monitoring a logical value on a feedback signal line. CONSTITUTION:Although some logical circuit fixes its output value (output value of level 5), oscillation may be generated in its inside (level 2-4). Since oscillation is generally generated by possitive feedback, the oscillation can be surely detected by allowing a logical value propagation monitoring means 21 to monitor the logical values of feedback signal lines 31, 32 in a feedback group.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit simulation method, and more particularly to an oscillation detection method during simulation execution.

Until now, there was no perfect method for detecting oscillation during this type of simulation, and efforts were made to add oscillation detection gates, etc. when modeling the simulation.For example, H, A, Breuer, A ,D,Fr1edn+an
.

“Diagnosis & Reliable Des
ign of Diaital 5ystals”,
Computer 5science Press, In
Such a technique is disclosed in J. C., 1976, (PP, 242-244).

With the conventional simulation detection circuit described above, it is necessary to find a location where oscillation is likely to occur when creating a model or executing a simulation, and to add a detection circuit to that location, but finding a location where oscillation is likely to occur is itself difficult. This method requires a lot of time and effort, and the addition of a detection circuit increases the model size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic simulation method that has a simple configuration and can easily detect oscillations.

According to the present invention, there is provided a simulation method for a logic circuit in which a plurality of logic circuit elements constitute a sequential circuit including a feed pack loop, the logic being propagated on the feedback signal line of the feedback loop. A simulation method is obtained in which a means for monitoring a value propagation state is provided, and the logical value propagation state is monitored during simulation execution to detect oscillations during simulation of a simulated model.

Fire ■yo Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram for explaining the present invention in detail, in which gates 10 to 20 represent logic circuit elements included in the simulated model, and each gate 10 to 20 is as shown in the figure. interconnected. Logical value propagation monitoring means 21
has a function of monitoring the propagation state of state values in the feedback loop connection signal lines 31 and 32 between logic circuit elements in the simulated model. Therefore, logical value propagation monitoring means 2
1 inputs an apparent signal line (indicated by a dotted line) derived from this feedback signal line 31.32, and when oscillation occurs during simulation of the model, a logical value propagates to this signal line 31.32. The oscillation detection output 30 is generated by detecting a change in the state of the sensor.

The method for detecting oscillation when the above model is simulated is as follows. For simplicity, it is assumed that this circuit is only subjected to logic simulation, and that it is executed using an event-driven method and level ordering (levels 1 to 5 in Figure 1).The pattern input to the model is the first one. Assume that the conditions are as shown in ■ and ■ in the figure.

When pattern ■ is first set, each gate 10 to 2
The 0 output is fixed to a value like ■ added to the output of each gate in the figure. Next, pattern ■ is set. When this pattern is set, the outputs of gates belonging to levels 1 and 5 are fixed, but each gate of levels 2, 3, and 4 has 14 outputs.
, 16.18, the logic values are not fixed. This pattern is shown by ■ in FIG. ]
The gate 8 oscillates in the order O→1→0→1, and the gate 16 oscillates in the order 1→0→1→0. Therefore, when patterns such as ■ and ■ enter, events always occur at levels 2 and 3.4, and the logic simulation for the pattern of ■ does not converge.
The following pattern of logical simulation cannot be executed.

In order to detect this oscillation state, in the present invention, an apparent signal line connected to the feedback signal line is added, and the logical value 7 (or state change notification event) propagated every time an event occurs is converted into a logical value. 0 monitored by the propagation monitoring means 21, for example, the gate 18 detects 0 for the pattern (■).
→1→0→1, etc., so this state is monitored by the monitoring means 21. This monitoring means 21 determines through simulation that oscillation has occurred when the cumulative total of these state changes exceeds a certain predetermined value, and transmits this to its output 30. When the occurrence of oscillation at the output 30 is propagated, the next pattern is executed.

In this embodiment, a logical value is propagated from a single feedback signal line, but a case where logical values are propagated from a plurality of feedback signal lines can be handled in the same way. Furthermore, if the monitoring means 21 has data on which feedback loop the oscillation is propagating from, it is possible to specify where the oscillation is occurring.In this example, the level 4 If it is found that the loop is 2, it can be seen that oscillation occurs in the loop between these levels.

In this embodiment, for the sake of simplicity, a case where oscillation occurs in logic simulation is shown, but the same can be said even if oscillation occurs in fault simulation. Furthermore, simulations performed using the compilation method can be similarly detected using the method of the present invention.

As explained above, according to the present invention, in a simulation, apparent signal lines connected to the feedback signal line are added, and means for monitoring the state propagating through these signal lines is provided. This has the effect that oscillations during simulation can be detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 10-20...Gate 21... Logical value propagation monitoring means

Claims (1)

[Claims] (1) A simulation method for a logic circuit in which a plurality of logic circuit elements constitute a sequential circuit including a feedback loop, which includes means for monitoring a logic value propagation state propagating on a feedback signal line of the feedback loop. A simulation method characterized in that the logical value propagation state is monitored during simulation execution to detect oscillations during simulation of the simulated model.