JPH01291548A - Series controller - Google Patents

Abstract

PURPOSE:To surely prevent the malfunction or the runaway, etc., of a device by detecting data string length by supplying data string length data representing the data string length of a data area to be inputted to each node to each node, counting the data string length in the data area to be inputted actually, and comparing a count value with supplied data string length data. CONSTITUTION:The node 10-1 is provided with a means to count the data string length of data included in a signal S0, and the counted data length is compared with the data string length represented by the data string length data (0) included in the signal S0, and it is detected whether or not abnormality exists in the data string length, and inspection whether or not a data error exists based on an error check code (0) included in the signal S0 is performed. Here, when the abnormality is detected in the data string length or the data error is detected based on the error check code (0), an error code representing the generation of an error is attached after an error check code (1).

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is applicable to centralized management systems for various machines such as presses, machine tools, construction machinery, ships and aircraft, as well as for unmanned transport devices, unmanned warehouses, etc. The present invention relates to a series control device suitable for use.

[Conventional technology]

When centrally managing presses, machine tools, construction machinery, ships, aircraft, unmanned transportation devices, unmanned warehouses, etc., it is necessary to have many sensors that detect the status of each part of the equipment, and many actuators that control the status of each part of the equipment. . For example, the number of sensors and actuators is 30 when considering a press.
00 or more, and some devices have even more numbers.

Conventionally, a centralized management system for centrally managing this type of equipment connects the many sensors and actuators mentioned above to a main controller, collects the outputs of the many sensors, and uses signals from the main controller to control the many actuators. configured to control.

In the case of such conventional centralized control systems, as the number of sensors and actuators increases, the number of wiring connecting the main controller and the sensors and actuators also increases, and the configuration of the input/output section of the main controller also becomes extremely complex. Become.

Therefore, multiple nodes are connected in series, one or more sensors and actuators are connected to each node, these nodes are connected in a ring via a main controller, and each node is controlled by signals from this main controller. A configuration with the following structure is being considered. In such a configuration, the main controller basically only needs signal input lines and output lines, and each node only needs to connect signal input lines and output lines, so the number of wires can be significantly reduced. .

However, if the above nodes are connected in series,
The problem is how to ensure the simultaneity of collecting the outputs of each sensor and the simultaneity of controlling each actuator.

For example, if we consider a configuration in which an address is assigned to each node and each node is controlled based on this address, the time delay for this address processing becomes a problem, and it is necessary to satisfy the requirements for collecting the output of each sensor and controlling each actuator. Simultaneity cannot be guaranteed.

Therefore, the inventors abandoned the idea of assigning an address to each node even though they had a configuration in which nodes were directly connected, and identified each node by the order of its connections, thereby eliminating the need for address processing. In addition, the present invention provides a serial control device that eliminates time delays associated with address processing and further simplifies the configuration of nodes.

According to this device, each node sequentially adds a signal from an actuator to a signal from a previous node based on a predetermined rule, and also sequentially adds a predetermined signal from a signal from a previous node based on a predetermined rule. The configuration is such that it is deleted and output to the actuator. In this case, each node does not need an address at all, and since no address processing is required, the time delay at each node is very small, just due to timing alignment, and the configuration of the node is also very simple. .

By the way, when using the above configuration, each node and the main controller can determine which node the signal (data) is from and to which node, depending on the order of the signal (data) (the position of the data in the data). However, if an error occurs in the addition or deletion of a signal at each node, it becomes impossible to identify which node the signal is from, and it becomes impossible to identify which node the signal is directed to. It became impossible to control the equipment, and in some cases there was a risk that the equipment would go out of control.

[Problem to be solved by the invention]

As mentioned above, if an error occurs in signal addition or signal deletion in the above device, that is, erroneous bit omission or bit addition, this erroneous signal will be transmitted to the next stage node and main controller. This caused operational errors in the next stage nodes and the main controller, and in some cases caused problems such as the device going out of control.

This became a problem especially when a configuration was adopted in which each node was identified by the order in which each node was connected without allocating an address to each node.

Therefore, the present invention provides a serial control device that reliably detects abnormalities in data string length due to erroneous bit omission or erroneous addition of bits at each node, and reliably prevents malfunctions and runaways of controlled devices. The purpose is to

[Means to solve the problem]

In this invention, each node is provided with data string length data representing the data string length of data to be received at each node, ie, data from the previous stage. Each node detects an abnormality in the data string length based on this data string length data.

That is, in the present invention, a plurality of nodes are connected in series, and one or more terminals are connected to each node, and each node uses data contained in a signal from a previous node to connect a terminal connected to its own node. In a serial connection device that adds a signal from a node and deletes a signal to a terminal connected to its own node and sends it to a subsequent node, the signal from the previous node has a sublength of the data included in the signal. Each node includes data string length data indicating
A counting means for counting the data string length of the data included in the signal from the preceding node, and comparing the counted value of this counting means with the data string length, and the counted value of this counting means is the data string length data. a comparison means that generates an error signal if the data string length does not match the data string length indicated by the data string length data contained in the signal from the previous stage, and a data string length corresponding to the data string length of the data output from the own node; It is configured to include a data string length data converting means for converting the converted data string length data into data and transmitting the converted data string length data by including it in a signal to be sent to a subsequent node.

In addition, multiple nodes connected in series are connected to the main controller, and one or more terminals are connected to each node, and each node is connected to its own node based on the data contained in the signal from the previous node. In a serial control device that adds a signal from a terminal and deletes a signal to a terminal connected to its own node and sends it to a subsequent node, the main controller sends the data output from each node to each node. a distribution means for distributing data string length data corresponding to the data string length; a counting means provided at each node for counting the data string length of data included in the signal from the previous node; and an output of the counting means. the data string length data distributed by the distribution means, and generates an error signal if the counted value of the counting means does not match the data string length indicated by the data string length data. configured.

[Effect]

The data string length of the data included in the signal from the previous stage node is counted by a counting means, and the data string length counted by this counting means is compared with the data string length data included in the signal from the previous stage node. . If the counted data string length of the counting means does not match the data string length represented by the data string length data, an error signal is generated as an abnormality in the data string length. The data string length data included in the signal from the previous node is changed to data string length data corresponding to the sub-length of the data output from its own node, and is sent out as being included in the signal sent to the subsequent node.

Further, data string length data corresponding to each node representing the data string length of data included in the signal from the previous node is distributed from the main controller to each node by the distribution means. This data string length data is distributed to each node by, for example, a signal with a subframe structure that is different from a signal with a main frame structure that transmits data. The data string length of the data included in the signal from the previous node is counted by the counting means, and the data string length counted by the counting means is compared with the data string length data distributed by the distribution means. If the counted data string length of the counting means does not match the data string length represented by the data string length data, an error signal is generated as an abnormality in the data string length.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of a series control device according to the present invention. This embodiment is applied, for example, to a centralized control system for a press. In this case, the main controller 100 is provided in the controller section of the press, the sensor groups 1-1 to 1-n correspond to sensors that detect the state of each part of the press, and the actuator groups 2-1 to 2-n correspond to the sensors for each part of the press. Corresponds to the actuator that drives the. Sensor group 1-1 and actuator group 2-1 are connected to node 10-1.
connected to sensor group 1-2 and actuator group 2.
-2 is connected to node 10-2, sensor group 1-3 and actuator group 2-3 are connected to node 10-3, and similarly sensor group 1-n and actuator group 2 are connected to node 10-2.
-n is connected to node 10-n. Also node 10-
1 to 10-n are connected in series via the main controller 100.

The main controller 100 controls each node 10-1 to 10-
Collects signals output from sensor groups 1-1 to 1-n connected to nodes 10-1 to 1-n, and drives actuator groups 2-1 to 2-n connected to each node 10-1 to 10-n. output a signal for

Sensor groups 1-1 to 1 connected to each node 10-1 to 10-n based on a signal from the main controller 100
The operation of collecting the -n output signals will be explained based on FIG. In this case, each node 10-1 to 10-n does not output a signal to the actuator groups 2-1 to 2-n.

The main controller 100 first outputs a signal SO having a frame structure as shown in FIG. 2(a).

In other words, with the start code at the beginning, this signal SO
Data string length data (0) representing the data string length included in the signal (here, the data string length is zero because no data is included yet), a stop code, and a signal for error checking the data contained in the signal SO. Main controller 1 sends the error check code and subsequent frame configuration signal SO.
00 is sent first. Here, the error check code is a code for performing a well-known cyclic redundancy check (CRC) or parity check for detecting data errors.

This signal SO from main controller 100 is applied to node 10-1.

The node 10-1 converts the signals input in parallel from the sensor group 1-1 immediately after the data string length data (0) of the signal SO into a serial signal in a predetermined order, and converts this into a serial signal as data (1).
), the data string length data (0) is converted into data string length data (1) representing the data string length L・1 of the inserted data (1), and the signal SL (Figure 2 (b)) is Output. In addition, node 10-1 creates a new error check code (1) based on the inserted data (1).
This error check code (1) is output instead of the error check code (0).

Further, the node 10-1 has means for counting the data string length of the data included in the signal SO, and the counted data string length and the data string length represented by the data string length data (0) included in the signal SO are calculated. It is detected whether there is an abnormality in the data string length by comparing the data string length, and it is also checked whether there is a data error based on the error check code (0) included in the signal SO.

If an abnormality is detected in the data string length or a data error is detected based on the error check code (0), an error code indicating the occurrence of an error is added after the error check code (1). In addition, here there is a data abnormality,
A case is shown in which no error code is added because no data error is detected. Signal S1 output from node 10-1 is applied to node 10-2.

At node 10-2, data string length data (1) of signal S1
The signal (data) output from sensor group 1-2 immediately after
2)), and change the data string length data (1) to data (2).
) is converted into data string length data (2) corresponding to the data string length L2 of the data changed by inserting the data (2), and a new error check code (2) is created based on the new data into which this data (2) is inserted. Generate this error check code (2) and convert it to the error check code (
1) and outputs it as a signal S2 (FIG. 2(C)). Note that node 10-2 also has node 10-2.
-1 as well as data string length abnormality check and error check code (1) based on data string length data (1)
A check is made for data errors based on However, since data string length abnormalities and data errors are not detected here as well, no error code is added. Signal S2 output from node 10-2 is input to node 10-3.

Similarly to the node 10-2, the node 10-3 also inserts the signal (data (3)) output from the sensor group 1-3 immediately after the data string length data (2) of the signal S2, and inserts the signal (data (3)) output from the sensor group 1-3. 2) into data string length data (3) corresponding to the data string length L3 of the data changed by inserting data (3), and also converting data (3) into new data based on the new data inserted. An error check code (3) is generated and this error check code (3) is replaced with the error check code (2). However, in the node 10-3, a data string length abnormality check or error check code (2) based on the data string length data (2) is executed.
), it is assumed that an abnormal data string length or a data error is detected in any of the data error checks based on the data error check. In this case, the error code is added immediately after the newly generated error check code (3). FIG. 2(d) shows the signal S3 output from node 10-3 in this manner. Once the error code is added, subsequent nodes 10-4
(not shown) to 10-n, the error code remains attached regardless of whether a data string length abnormality or data error is detected.

Similarly, the signal output from the node 1O-n-1 (not shown), that is, the input signal of the node n, has data (f(n-1)) inserted as shown in FIG. 2(e), and the data string length data is The data string length becomes data (n-1), and the error check code becomes a signal Sn-1, which becomes the error check code (n-1).

In addition, at the node 10-n, data from the sensor group 1-n (
n) is added, the data string length data (n-1) is converted to data string length data (n), and an error check code (
n-1) is replaced with the error check code (n), and the signal Sn shown in FIG. 2 (5) is output. This signal Sn
is input to the main controller 100.

The main controller 100 identifies which node the sensor group the data is connected to is based on the data arrangement order of the data area from the rear end of the data string length data (n) of the signal Sn to the front end of the stop code. . As a result, in the main controller 100, each node 1-1 to
This means that signals from the sensor groups 1-1 to 1-n connected to sensor 1-n have been collected.

In addition, the main controller 100 receives the error code from the nodes 10-1 to 10-1 by adding an error code to the signal Sn.
It can be known that there is an abnormality in the data string length or a data error in any node among nodes 10-n. Note that if no data string length abnormality or data error occurs in any of the nodes 10-1 to 10-n, no error code is added to the signal Sn. In this case, the main controller has no abnormality and each node 10-1 to 10-n
It is known that data from the sensor groups 1-1 to 1-10 connected to the sensor group 1-1 to 1-10 have been collected.

FIG. 3 shows from the main controller 100 to each node 10-
Actuator groups 2-1 to 2 connected to 1 to 10-n
This figure shows the operation when sending drive data to -n. In this case as well, the explanation will be made assuming that the nodes 10-1 to 10-n do not receive signals from the sensor groups 1-1 to 1-n.

The main controller 100 first outputs a signal SO as shown in FIG. 3(a). This signal S0 starts with the start code, data string length data (0), and node 10-1.
Data for actuator group 2-1 connected to (
1), actuator group 2 connected to node 10-2
Data (2) for actuator group 2-n-1 connected to 1O-n-1, data (n
-1), a data area consisting of data (n) for the actuator group 2-n connected to the node 10-n, a stop code, and an error check code (1). This signal is applied to node 10-1.

The node 10-1 extracts data (1) for the actuator group 2-1 from the front end of the data area of the signal SO, converts it into a parallel signal, and sends the data to the actuator group 2-1.
1 to each actuator. Also, node 10-
In 1, data string length data (0) is converted to data string length data (1) corresponding to the data string length ρ1 of the remaining data after extracting data (1), and The error check code (0) is also replaced with the error check code (1) generated corresponding to the remaining data after extracting this data (1), and is sent to the node 10-1 as the signal Sl (FIG. 3(b)). is output from. In this node 10-1, the actually counted data string length and the data string length data (
0) to check for an abnormality in the data string length, and also check for data errors using the error check code (1). If an abnormality is detected by this check, an error code is added immediately after the error check code (1). However, if no abnormality is detected, no error code is added.

The node 10-2 extracts data for the actuator group 2-2 at the front end of the data area of the signal S1. Also, convert the data string length data (1) to data string length data (2) corresponding to the extracted remaining data string length g2, and use the error check code (1) to check the error corresponding to the extracted remaining data. Replace with code (2). Thereafter, similarly, data at the front end of the data area is extracted sequentially at each node (Fig. 3(C) to Fig. 3(5)
)).

In this operation example, it is assumed that a data string length abnormality or a data error has occurred in this node 10-2, so an error code is added immediately after the replaced error check code (2). If an abnormality in the data string length or a data error occurs, the data for the extracted actuator group 2-2 is not added to each actuator in the actuator group 2-2 in order to prevent malfunction of the actuators.

- Once the error code is added, the following node 10-
3 to 10-n, the output of the extracted data to the actuator group is prohibited due to this error code.

Signal Sn output from node 10-n (Fig. 3 (
r)) is added to the main controller 100. The main controller 100 can know whether or not there is an abnormality in each node based on the presence or absence of this error hood.

If no data string length abnormality or data error occurs at each node 10-1 = 10-n, each 1o-1 to 10
-n, each node 10-1 to 10 from the data area
The data corresponding to the actuator group connected to -n is sequentially extracted, and the extracted data is latched at an appropriate timing to be converted into a parallel signal and supplied to each actuator of the corresponding actuator group.

Note that in the above description, each node 10-1 to 10-1
Although it has been described that the sensor group and the actuator group are connected to -n, a node to which only the sensor group is connected may be provided, or a node to which only the actuator group is connected may be provided.

Further, the sensor group may be one sensor, and the actuator group may be one actuator.

Furthermore, when collecting data from the sensor groups 1-1 to 1-n, new data is inserted immediately after the data string length data, that is, at the front end of the data area, but at the rear end of the data area. It may also be configured to insert new data.

Furthermore, when outputting data to the actuator groups 2-1 to 2-n, the configuration is such that the data is sequentially extracted and output from the front end of the data area, but the configuration is configured such that the data is sequentially extracted and output from the rear end of the data area. You may.

In addition, in the above explanation, in order to facilitate understanding of the present invention, the cases in which data is collected from the sensor groups 1-1 to 1-n and the cases in which data is output to the actuator groups 2-1 to 2-n are explained separately. As described above, control such as collecting data from a group of sensors at each node and outputting data to a group of actuators is also possible. Control in this manner will be detailed later.

FIG. 4 shows a detailed configuration example of the nodes 10-1 to 10-n shown in FIG. 1. Here, node 10-1~
10-n each have the same configuration, and in FIG. 4, node 10 represents nodes 10-1 to 10-n.

Moreover, sensor group 1 is sensor group 1-1 to 1 shown in FIG.
-n, and the actuator group 2 corresponds to any of the actuator groups 2-1 to 2-n shown in FIG. In this embodiment, data transmission between each node 10 is performed using CMI (Coded Mark I n
version) code. This is to minimize transmission errors due to noise during the transmission process, and to enable regeneration (extraction) of the clock signal at each node. In this case, it is not necessary to provide each node with a clock oscillator, and the configuration of each node can be further simplified. Furthermore, in this embodiment, each node adds data input from sensor group 1 to the front end of the data area of the data transmitted from the previous node, and also adds data to be output to actuator group 2 in the transmitted data. The configuration is such that the transmitted data is extracted from the rear end of the data area and transmitted to the subsequent node, and the transmitted data (input signal) from the preceding node has a frame configuration as shown in Figure 5(a). ing. Here, the data string length data represents the data string length of data included in the input signal. In addition, an error hood is added when an error signal is generated at any node before the previous stage.If an error signal ("signal" does not occur) at any node before the previous stage, this error code is added. Not done.

In FIG. 4, the receiving circuit 11 receives the received signal from the previous node. Here, since the signal from the previous node is modulated by the CMI code as described above, the receiving circuit 11 converts this CMI code into NRZ (Non Return Zero) corresponding to normal "1" and "0".
) code. Also, the receiving circuit 11 receives this CM! A clock signal synchronized with the transmission data used in this node 10 is regenerated from the code-modulated input signal.

The input signal demodulated by the receiving circuit 11 is sent to a start code detection circuit 12, a stop code detection circuit 13, an error check code detection circuit 17, and an error code detection circuit 18.
, data string length data conversion circuit 19, data conversion circuit 20
It is also applied to the data string length setting circuit 14 and the data string length counter 15 via switches SW1 and SW2, respectively.

Here, the start code detection circuit 12 detects a start code (input side start code) included in the input signal. For example, an 8-bit digital code signal consisting of a predetermined pattern is used as the start code.

Further, the stop code detection circuit 13 detects a stop code included in the input signal. The stop code consists of, for example, an 8-bit digital code signal having a predetermined pattern different from the above-mentioned start code.

Further, the data string length setting circuit 14 reads data string length data included in the input signal 4 and sets the data string length used for testing data string length abnormalities in the data included in the input signal. Here, the data string length data is, for example, 8
Consists of binary code of bits. The data string length setting circuit 24 outputs a data string length data read completion signal upon completion of reading the data string length data, that is, after 8 bits of time corresponding to the data string length data have elapsed from the start of reading the data string length data. .

Further, the data string length counter 15 counts the data string length of data included in the input signal, and counts the actual data string length included in the input signal. The data string length is counted by counting clock signals synchronized with input data output from the receiving circuit 11.

Further, the error check code inspection circuit 17 detects transmission data code errors by inspecting the error check code included in the input signal. Here, the error check code is one formed for the well-known CRC or error check, as described above.

Further, the error code detection circuit 18 detects whether or not the input signal includes an error code. When a data string length abnormality or a code error is detected at any node before the previous stage node, an error code is added at this node, and this error code is transmitted as is to each subsequent stage node. Therefore, the error code detection circuit 18 detects whether or not an error code is added. Here, the error code is, for example, an 8-bit code signal having a predetermined pattern different from the start code and stop code. Further, the data string length data conversion circuit 19 converts the data string length data from the previous node included in the input signal into data string length data corresponding to the data string length of the data generated at this node 10. For example, as shown in FIGS. 5(a) and 5(b), the data string length of the data included in the input signal input from the previous node is L bits, and the data included in the output signal output to the subsequent node Assuming that the data string length of is L' bits, data string length data indicating the data sub-length L bits is converted into data string length data indicating the data string length L'. The output of this data string length data conversion circuit 19 is applied to contact C of switch SW4.

The data conversion circuit 20 also converts the parallel signals from the sensor group 1 into serial signals and adds them to the data area included in the input signal in a predetermined order, and also converts the parallel signals from the data area included in the input signal into serial signals to the actuator group 2. Data is extracted from the data included in the input signal, and the extracted serial data is converted into a parallel signal and sent to the actuator group 2 via the register 21.

The data string length set by the data string length setting circuit 14 and the data string length counted by the data string length counter 15 are applied to a data string length correctness determination circuit 16.

The data string length correctness determination circuit 16 is the data string length setting circuit 14.
The stop code detection circuit 1 detects the data string length set by the data string length counter 15 and the actual data string length counted by the data string length counter 15.
The timing of the output of step 3 is compared, and if the two do not match, it is detected that the data string length is abnormal.

Output of data string length correct/incorrect judgment circuit 16, output of error check code inspection circuit 17, and error code detection circuit 1
The output of 8 is applied to the switch SWO via the OR circuit OR.

The switch SWO is a data string length correct/incorrect judgment circuit when the output of the OR circuit OR is high level, that is, the output of any one of the data string length correct/incorrect judgment circuit 16, error check code inspection circuit 17, or error code detection circuit 18 is high level. If a data string length abnormality is detected in 16, a code error is detected in error check code detection circuit 17, or an error code is detected in error code detection circuit 18, switch SWO is shown. A predetermined error code generated from the error code generation circuit 25 is applied to the contact E of the switch SW4. but,
If the outputs of the data string length correct/incorrect judgment circuit 16, error check code inspection circuit 17, and error code detection circuit 18 are all at low level, the switch SWO will not change from the state shown in the figure, and the contact E of switch SW4 will be at low level. A signal is added. Here, the error code generation circuit 25 outputs an error code sending completion signal upon completion of error hood generation.

Further, the output of the data conversion circuit 20 is applied to the contact B of the switch SW4, and the start code detection circuit 23
, is added to the stop code detection circuit 24, and is also applied to the error check code generation circuit 2 via the switch SW3.
Added to 6.

Here, the start code detection circuit 23 detects the start code (output side start code) output from the data conversion circuit 20, and the stop code detection circuit 24 detects the stop code output from the data conversion circuit 20. It is something to detect.

Further, the error check code generation circuit 26 inputs the converted data output from the data conversion circuit 20, and generates an error check code such as a CRC check or a parity check based on this data. The error check code generation circuit 20 outputs an error check code transmission completion signal upon completion of transmission of the error check code.

The switch SW4 has the output of the data conversion circuit 20 applied to the contact 13, the output of the data string length data conversion circuit 19 applied to the contact C, the output of the error check code generation circuit 26 applied to the contact 1, and the output applied to the contact E. This selects one of the outputs of the switch SWO. The output of this switch SW4, ie, the signal at contact A, is applied to the transmitting circuit 27. The transmitting circuit 27 performs predetermined modulation processing to convert the applied signal into a CMI code, and outputs this modulated signal to the next stage node.

In addition, the input side start code detection output output from the start code detection circuit 12 and the stop code detection circuit 1
3, the data string length reading completion signal is output from the data string length setting circuit 14, the output side start code detection output is output from the start code detection circuit 23, and the stop code detection circuit 2.
The output side stop code detection output outputted from 4 is applied to the control circuit 22.

The control circuit 22 controls the switching timing of the switches SWI, SW2, SW3, and SW4 based on these input signals.

First, the operation of this node 10 is determined by the data string length of the data added to the data conversion circuit 20 (if 1 (i) bit is longer than the data string length II (o) bits of the extracted data, D (i) > II ( o) will be explained.

The operation in this case is shown in the timing chart shown in FIG.

In this case, the start code of the input signal (FIG. 5(a)) received by the receiving circuit 11 passes through the data conversion circuit 20 as it is and is applied to the switch SW4. Here, switch SW4 is in a state where contact A and contact B are connected (A-B
) (Fig. 5 (fil)), the start code that has passed through the data conversion circuit 20 passes through the switch SW4 and is output to the next stage node via the transmission circuit 27 (Fig. 5 (b)). )).

Further, the start code of the input signal is detected by the start code detection circuit 12, and the start code detection circuit 12 generates an input side start code detection output (see Fig. 5).
C)). Based on this input side start code detection output, the control circuit 22 turns the switch SW1 from off to on (fifth
Figure (j)).

When the switch SWI is turned on, the data string length data setting circuit 14 starts reading the data string length data in the input signal.

Further, the start code detection circuit 23 is connected to the data conversion circuit 2.
The start code is detected from the output of 0, and a start code detection output is generated on the output side (FIG. 5(b)). The control circuit 22 turns on the switch SW3 based on this output side start code detection output (FIG. 5(e)). switch SW
3 is turned on, the output of the data conversion circuit 20 is applied to the error check code generation circuit 26. The error check code generation circuit 26 generates a desired error check code based on the output of the data conversion circuit 20.

Further, in response to this output-side start code detection output, the control circuit 22 switches the switch SW4 from the state (A-B) to the state (A-C) in which the contact A is connected to the contact C (FIG. 5 (ffl)). As a result, the output of the data string length data conversion circuit 19 appears at the contact A of the switch SW4. Here, the output of the data string length data conversion circuit 19 is the data string length N
(1) Addition of bit data and data string length D (o
) The total data string length changed due to the deletion of bit data (
The data string length data corresponds to L+ρ(+)−g(0)) bits. This data string length data is output from the transmitting circuit 27 following the start code (see Fig. 5).
b)).

When the reading of the data string length data is completed in the data string length data setting circuit 14 and a data string length data reading completion signal is generated (FIG. 5(e)), the control circuit 22 switches SW1.
5(1)), and at the same time turn on the switch SW2 (FIG. 5(k)). When the switch SW2 is turned on, the data string length counter 15 starts its counting operation. Specifically, the data string length counter 15 is connected to the receiving circuit 11.
By counting the clock signals output from the input signal, the length of the data string, that is, the number of bits, of the data area included in the input signal is counted.

When the reading of the data string length data from the data string length data conversion circuit 19 is completed, that is, after the start code detection output on the output side is generated from the start code detection circuit 23, 8 bits of time corresponding to the data string length data has elapsed. The rear switch SW4 is from state B (A-C) so that contact A is connected to contact B.
(A-B) (Fig. 5 (11)
)). As a result, the data from the sensor group 1 is added to the output of the data conversion circuit 20, that is, the front end of the data area of the input signal, to the contact A of the switch SW4, and the data to the actuator group 2 is extracted from the rear end of the data area. The data will be output. This data is outputted via the transmission circuit 27 following the data string length data outputted earlier (FIG. 5(b)).

When the stop code included in the input signal is detected by the stop code detection circuit 13 and an input side stop code detection output is generated (FIG. 5(f)), this switch SW
2, the counting operation of the data string length counter 15 ends. That is, the data string length counter 15 counts the data string length from the start point of the data area of the input signal to the end point of the stop code. Since the sub-length of the stop code is known, for example 8 bits, the data string length counter 15 essentially counts the data string length of the data area of the input signal. The counted value of the data string length counter 15 (the value obtained by subtracting the sub-length of the stop code from the counted value of the data string length counter 15) is determined by the input side stop code detection output from the stop code detection circuit 13 in the data string length correctness judgment circuit 16. At the output timing (FIG. 5(f)), it is compared with the data string length set in the data string length setting circuit. If the two do not match, a high-level error signal will be output as an error in the data string length.

Data conversion circuit 20 by stop code detection circuit 24
When the stop code included in the signal output from the switch is detected and the output side stop code detection output is generated (FIG. 5(g)), the control circuit 22 changes the switch SW4 from the state (A-B) to the contact A. is connected to the contact (A
-D) (Fig. 5 (ffl)). This causes error check code 2 to be sent to contact A of switch SW4.
The error check code generated in step 6 will appear. This error check code is output from the transmission circuit 27 following the stop code output from the data conversion circuit 20 (FIG. 5(b)). Error check code generation circuit 26
When the transmission of the error check code is completed and the error check code transmission completion signal is generated (Fig. 5 (h)
), the control circuit 22 switches the switch SW4 from the state (A-D) to the state (A-E) in which the contacts A and E are connected.

Here, a high-level error signal is not generated from the data string length correctness determination circuit 16, no code error is detected by the error check code inspection circuit 17, and a high-level error signal is not generated, and the error hood detection circuit If no error code is detected in the input signal and a high level signal is not generated in step 18, the output of the OR circuit OR is low level.
As a result, the switch SWO remains selected at the ground level. Therefore, at this time, a ground level signal is generated at the contact A of the switch SW4, and this signal is output from the transmitting circuit 27 following the error check code. In other words, no error code is added at this time.

The data string length is determined by whether the data string length correctness judgment circuit 16 detects an abnormal data string length, the error check code inspection circuit detects a code error, or the error code detection circuit 18 detects an error code. Counter 15, error check code inspection circuit 17, error code detection circuit 18
When any of the outputs becomes high level, the OR circuit OR also becomes high level, and the switch SWO is switched from the illustrated state to select the error code generation circuit 25 side. As a result, a predetermined error code generated from the error code generation circuit 25 appears at the contact A of the switch SW4. In this case, the transmission circuit 27 outputs this error code following the above-mentioned error check code. That is, an error code is added (Fig. 5(b)).
).

In this case, the output of the OR circuit OR register 21
becomes inoperative, and transmission of control data to the actuator group 2 is prohibited.

When the error hood generation circuit 25 completes sending the error code and outputs the error code sending completion signal (fifth
(1)), or a predetermined number of bits (e.g. 8 bits) corresponding to the error code from the error check code transmission completion signal.
bit), the control circuit 22 switches switch SW4.
is switched from the state (A-E) to the initial state (A-B).

This ends the processing of this node.

Next, the operation of this node 10 is determined when the data string length Ω(1) bits of the data added by the data conversion circuit 10 is shorter than the data string length (1(o) bits) of the extracted data (j! (i) <fl (o)) will be explained.

The operation in this case is shown in the timing chart shown in FIG.

Data string length N of the data added by the data conversion circuit 10
(i) If the bit is shorter than the sub-length 1(o) bits of the data to be extracted, the data conversion circuit 10 converts the input signal (FIG. 6(a)) to the data string length f) (D bits and I).
(o) Data string length of bit difference (N (i) −D
(o) Output with a delay of ) bits. Along with this, the data string length data conversion circuit 13 also delays the converted data string length data by the data string length (f!(1) - R(o)) bits with respect to the input data string length data. Output.

Therefore, in this case, the input signal (FIG. 6(a)) received by the receiving circuit 11 is delayed by the data string length (J (i) - (o)) bits in the data conversion circuit 2°0, and the switch SW4, Output via the transmitting circuit 27 (sixth
Figure (b)).

Subsequently, when the start code is detected by the start code detection circuit 23 and an output side start code detection signal is generated (FIG. 6(d)), the switch sw3 is turned on.
Switch SW4 is switched from state (A-B) to state (A-C). When the switch SW3 is turned on, the error check code generation circuit 26 starts taking in the output of the data conversion circuit 2o. Furthermore, in the data string length data conversion circuit 19, the data string length data converted as described above is applied to the data string length data included in the input signal (g(
1) Since the output is delayed by −J (o) ) bits, the data string length data converted from the data string length data conversion circuit 19 is transferred to the contact point of the switch SW4 at the timing when the switch SW4 switches to the state (A-C). Appears at A,
This data string length data is output via the switch 27 following the start code described above (FIG. 6(b)).
.

Data conversion circuit 20 by stop code detection circuit 24
When the stop code output from the error check code generation circuit is detected and an output side stop code detection output is generated, the switch SW3 is turned off and the acquisition of the output of the data conversion circuit 20 by the error check code generation circuit is completed. At the same time, the switch SW4 changes from the state (A-B) to the state (A-
D) (FIG. 6(m)), and a new error check code generated by the error check code generation circuit 26 is output from the transmitting circuit 27 following the above-mentioned stop code (FIG. 5(m)). )). Other operations are similar to those shown in FIG. That is, when the sending of the error check code from the error check code generation circuit 26 is completed and the error check code sending completion signal is output (FIG. 6(h)), the switch SW4 is in the state (A-
E) (FIG. 6 (I)), and when the error code generation circuit 25 outputs an error code transmission completion signal (FIG. 6 (I)), the switch SW4 changes to the initial state (A). -B).

Further, the switch SWI is connected to the start code detection circuit 12.
The period from when the input side start code detection output is generated (FIG. 6(C)) until the data string length data read completion signal is generated from the data string length setting circuit 14 (FIG. 6(e)). It is turned on (FIG. 6(j)), and the data string length setting circuit 14 reads the data string length data included in the input data during this time.

Further, the switch SW2 is turned on after the data string length data read completion signal is generated from the data string length setting circuit 14 (see FIG. 6).
e)) until the input side stop code detection output is generated by the stop code detection circuit 13 (Fig. 6(r))
It is turned on (FIG. 6(k)), and thereby the data string length counter 15 counts the data string length of the data area included in the input signal.

FIG. 7 is a timing chart showing the operation when the node 10 takes in and adds data from the sensor group 1 as explained in FIG. 2, but does not extract or output data to the actuator group 2. It is something that In this case, in the timing chart shown in FIG. 5, if the bit length of the data extracted at this node 10, that is, the fl (o) bit, is set to 0, the result will be similar to that shown in FIG. In this case, the data conversion circuit 20 only adds data from the sensor group 1, and the single data string length data conversion circuit adds II(1) to the data string length data indicating L bits included in the input signal.
) bits are added to output data string length data corresponding to L'-L+R(1) (bits).

FIG. 8 is a timing chart showing the operation when the node 10 extracts and outputs data to the actuator group 2, but does not take in or add data from the sensor group 1, as explained in FIG. 3. It is. In this case, in the timing chart shown in FIG. 6, if the bit length D (i) of the data added at this node 10 is set to 0, the result will be similar to that shown in FIG. In this case, the data conversion circuit 20 only extracts and outputs data to the actuator group 2, and outputs the processed data with a delay of g(0) bits. L' -L-1(0)(
The data string length data corresponding to bits) is formed, and this data is delayed by II (o) bits and output.

In addition, in the configuration shown in FIG. 4, without providing the start code detection circuit 23 and the stop code detection circuit 24,
Input side start code detection output output from start code detection circuit 12 and stop code detection circuit 13
The input side stop code detection output output from
A signal equivalent to the outputs of the start code detection circuit 23 and the stop code detection circuit 24 described above may be formed using a signal delayed by the above-described signal.

Also, instead of the data read completion signal output from the data string length setting circuit 14, a signal obtained by delaying the input side start code detection output from the start code detection circuit 12 by the number of bits of the data string length data (for example, 8 bits) is used. May be used.

Also, instead of the error check code transmission completion signal output from the error check code generation circuit 26, a signal obtained by delaying the output side stop code detection output output from the stop code detection circuit 24 by the number of bits corresponding to the error check code is used. Alternatively, instead of the error code transmission completion signal output from the error code generation circuit 24, a signal obtained by delaying the error check code transmission completion signal by the number of bits corresponding to the error code may be used.

Further, in this embodiment, the data conversion circuit 10 is configured to perform predetermined processing on data in the data area in order to facilitate detection of start codes and stop codes. That is, if the data string length in the data area sometimes matches the start code or stop code, it may be mistakenly detected as the start code or stop code. Therefore, in this embodiment, predetermined processing is applied to the data in the data area so that the data string length in the data area does not have the same data string length as a start code or a stop code.

In this embodiment, data "1" is used in the data conversion circuit 20.
” to “10” and data “0” to “01”. According to this, three or more "1"s will not continue in the data in the data area. Therefore, if you set the start code and stop code in a pattern that includes a part where three or more "1"s continue, data in the data area will not be mistakenly detected as a start code or stop code, and the start code and stop code will be reliably set. Code detection becomes possible. In this case, data "0" is "0", data "1" is "1"
0” or data “0” as “00”, data “1” as “
The same configuration can be achieved by changing the data such as ``10'', data ``0'' to ``00'', and data ``1'' to ``01''.

Further, the data conversion circuit 20 may be configured to automatically insert "0" when a predetermined number of converted data, for example, 5 consecutive data, are converted. In this case, "1" in the data is 6
Since six or more consecutive start codes and stop codes "1" are set in a pattern including six or more consecutive start codes and stop codes, data can be reliably distinguished from the start code and stop code.

In the embodiments described above, the signals transmitted to each node (main frame structured signals ) contains data string length data and reads this data string length data into the data string length setting circuit to set the data string length for data string length abnormality inspection. A signal with a sub-frame configuration is set separately, and when this sub-frame configuration signal is input to each node at that node, data string length data representing the data string length of the input signal is distributed to each node. You can.

FIG. 9 shows the configuration of a node 10 according to another embodiment of the present invention configured as described above. In this embodiment, a main controller 100 (FIG. 1) collects data from a group of sensors connected to each node and provides a main frame configuration of signals used to send data to actuators connected to each node. In addition, it outputs a signal with a subframe configuration for distributing data string length data to each node. An example of an input signal having a main frame configuration input to each node in this embodiment is shown in FIG. 10(a),
An example of an input signal having a sub-frame structure is shown in FIG. 12(a). As is clear from FIG. 10(a), the input signal of the main frame configuration in this embodiment has a configuration in which data string length data is deleted from the input signal shown in FIG. 5(a). Furthermore, as shown in FIG. 12(a), the input signal of the subframe configuration in this embodiment has the subframe start code at the beginning, followed by the data string length data DLK of its own node (in this case, ), the next node's data string length data DL (K+I), ... the n-th node's data string length data DLn, and the subframe stop code is placed at the end. The subframe configuration signal is sent to each node when the device is activated or every time the main frame configuration signal is sent a predetermined number of times.

In this embodiment, the node 10 has the configuration shown in FIG. 4 by adding a sub-frame start code detection circuit 28, a sub-frame start code detection circuit 29, and a sub-frame stop code detection circuit 30 to the configuration shown in FIG. It is constructed by removing the data string length data conversion circuit 19 and directly connecting the output of the receiving circuit 11 to the contact C of the switch SW4.

Here, the sub-frame start code detection circuit 28 detects the sub-frame start code from among the input signals of the sub-frame configuration that are input from the previous stage node and received by the receiving circuit 11. Circuit 29 and sub-frame stop code detection circuit 3
0 detects the sub-frame start code and stop code output from the data conversion circuit 20, respectively.

In FIG. 10, when the number of data bits II (i) added by the data conversion circuit 20 is larger than the number of data bits 1 (o) extracted (!J(i) > D(0)
) for the input signal of main frame configuration in node 1
The operation of 0 is shown in a timing chart.

In this case, since the input signal of the main frame configuration does not include data string length data, the switch SW2 is sent to the start code detection circuit 12 instead of the data string length data read completion signal from the data string length setting circuit 14. From OFF to ON with the input side start code detection output from
The switch SW4 does not operate from the state (A-B) to the state (A-
The operation is the same as that described in FIG. 7 except that it does not switch to C). This is because in this embodiment, the main frame configuration input signal does not include data string length data, so it is necessary to start counting the data string length immediately after the start code is detected, and the main frame configuration signal does not include data string length data. At the time of input, the data string length setting circuit does not set the data string length, and since there is no data string length data conversion circuit, the switching state of switch SW4 (A-C ) is not necessary.

Further, in this case, since the switch SW1 is not turned on, the data string length data is not read into the data string length setting circuit 14. The data string length data is read into the data string length setting circuit 14 when a subframe configuration signal is input to this node 10, as will be described later. Therefore, when the main frame configuration signal is input, the data sequence length correctness determination circuit 16 uses the data sequence length data read into the data sequence length setting circuit when the sub frame configuration signal is input, and the main frame counted by the data sequence length counter 15. The data string length is compared with the actual data string length to detect an abnormality in the data string length.

FIG. 11 shows the number of data bits N (1) added by the data conversion circuit 20 and the number of data bits g extracted
(0) (42(i)<D(0)), the operation of the node 10 with respect to the input signal of the main frame configuration is shown in a timing chart. In this case, the data conversion circuit 20 converts the input signal into CD (o
) -J (1)) It is the same as that shown in FIG. 11 except that it is output with a delay of only one bit.

Figure 12 shows node 1 for input signals with subframe configuration.
This shows the operation of 0. In this embodiment, the sub frame configuration signal is transmitted from the main controller 100 to the first
The frame is output in a frame configuration as shown in FIG. 3(a), and is first input to the node 10-1. This signal is shown in Figure 13 (a
), there is a subframe start code at the beginning, followed by data string length data for node 10-1, data string length data for node 10-2, data string length data for node 10-3, etc. , node 1
Following the data string length data for 0-n, a sub-frame stop code is placed at the end.

When each node receives a signal with this subframe configuration, it extracts the data immediately after the subframe start code as data string length data for its own node, and stores it in its own node. Repeat this operation sequentially. That is, when the leading node 10-1 inputs a signal having a frame structure as shown in FIG. At the same time, this data DL1 is extracted and converted into a signal as shown in FIG. 13(b) and sent to the next stage node 10.
-2. The node 10-2 is shown in FIG. 13(b).
When the signal shown in Figure 13(e) is input, data DL2 immediately after the subframe start code of this signal is taken in as the data string length data of its own node, and this data DL2 is extracted, resulting in a signal as shown in Figure 13(e). It is output to the next stage node 10-3 as . In this way, the sub-frame configuration signal from the main controller 100 is such that each node sequentially extracts the data string length data corresponding to each node, and the final node 10-n outputs a signal as shown in FIG. 13(e). will be output. This signal is applied to main controller 100. Thereby, the main controller 100 is configured to know that the data string length data has been distributed to each node.

There, the node 10, which is the th node, is shown in Fig. 12 (
An input signal having a subframe configuration as shown in a) is added and received by the receiving circuit. The sub-frame start code first output from the receiving circuit 11 is detected by the sub-frame start code detection circuit 28, and the sub-frame start code detection circuit 28 generates an input side sub-frame start code detection output (see FIG. 12). C)). This input side sub-frame start code detection output is applied to the control circuit 22. The control circuit 22 thereby switches the switch SWI from off to on (FIG. 12(g)).

When the switch SW1 is turned on, the data string length data DLK for this node 10 is output from the receiving circuit 11.
is read into the data string length setting circuit 14, thereby setting the data string length of this node 10. When the reading of the data string length data DLK in the data string length setting circuit 14 is completed, a data string length data reading completion signal is output from the data string length setting circuit 14 (FIG. 12(d)).
. The control circuit 2 receives this data string length data read completion signal.
2 switches the switch SWI from on to off (12th
Figure (g)).

The output of the receiving circuit 11 is also applied to a data conversion circuit 20. When the data conversion circuit receives a sub-frame configuration signal, it delays this signal by the number of bits of the data string length data (for example, 8 bits) and outputs the signal. The output of this data conversion circuit 20 is applied to switch SW4. SW here
4 is in the state (A-B) in which contact A is connected to contact B (FIG. 12 (j)), so the output of the data conversion circuit 20 is sent to the next stage via this switch SW4 and the transmission circuit 27. Output to the node. Therefore, from the transmitting circuit 27,
First, the subframe start code is output after being delayed by 8 bits from the input signal (FIG. 12(j)). When the sub-frame start code is output from the data conversion circuit 20, this sub-frame start code is detected by the sub-frame start code detection circuit 29, and an output side sub-frame start code detection output is generated (see FIG. 12(e)). > is applied to the control circuit 22.The control circuit 22 thereby switches the switch SW4 from the state (A-B) to the state (A-C) in which the contact A is connected to the contact C.
As mentioned above, the output of the receiving circuit 11 is directly applied to the contact C of the switch SW4, so the contact A of the switch SW4 receives the data string length data DL (k
+1) appears.

This data DL (k+1) is applied to the transmitting circuit 27 and output following the above-mentioned sub-frame start code. In this way, the data string length data DL of this node
The signal from which K has been removed is output from the transmitting circuit 27 (FIG. 12(b)).

When the sub-frame stop code is output from the data conversion circuit 20, this sub-frame stop code is detected by the sub-frame stop code detection circuit 30, and an output side sub-frame stop code detection output is generated (see FIG. 12).
r)). This output side secondary frame stop code detection output is applied to the control circuit 22. The control circuit 22 thereby switches the switch SW4 to the initial state (A-B).

Note that in the configuration shown in FIG. 9, two sub-frame start code detection circuits are not provided, and the input terminal sub-frame start code detection output from the sub-frame start code detection circuit 28 is set to a predetermined bit (data string). A signal equivalent to the output of the sub-frame start code detection circuit 29 may be formed from a signal delayed by the number of bits of the long data.

FIG. 14 shows a node configuration of another embodiment in which the data string length data of each node is set using signals of subframe configuration. The node 10 used in this example is the ninth
The node shown in the figure includes a switch SW5, a subframe frame counter 31, a node address setting circuit 32, and a comparison circuit 3.
3 and switch SW4 from the receiving circuit 11.
It is constructed by deleting the wiring leading to the contact point C.

Here, the subframe frame counter 31 is the switch S
It is connected to the receiving circuit 12 via W5, and the switch SW5
The number of sub-frames is counted on the condition that the sub-frame is turned on. Further, a node address, which is the address of this node, is set in the node address setting circuit 32. In this embodiment, by comparing the node address set in the node address setting circuit 32 and the count value of the subframe frame counter 31 in a comparison circuit, the data string length data of the own node is retrieved from the signal of the subframe configuration. ,
This retrieved data string length data is transferred to the data string length setting circuit 1.
4 to set the data string length. This data string length setting operation will be explained with reference to the timing chart shown in FIG.

In this embodiment, an input signal having a subframe structure input to the receiving circuit 12 is as shown in FIG. 15(a). This signal is transmitted to the first stage node 10 shown in FIG.
It is the same as the signal applied to -1. However, in this embodiment, the data string length data of each node is not extracted at each node, so the same signal is input to each node. Each node searches this signal for data string length data corresponding to its own node, and reads the retrieved data string length data into the data string length setting circuit 14. Now, the node number of this node 1° is “
3". In this case, the node address setting circuit 32
is set to "3". When an input signal having a sub-frame configuration (FIG. 15(a)) is input and a sub-frame start code is output from the receiving circuit 11, this sub-frame start code is detected by the sub-frame start code detection circuit 28.
, and an input side sub-frame start code detection output is generated. As a result, the control circuit 22 turns on SW5 (FIG. 15(k)). When the switch SW5 is turned on, the subframe frame counter 31 starts counting the number of subframes. The initial value of the subframe frame counter 31 is set to "1",
At the front end of data string length data DL2, the count value becomes "2", and at the front end of data string length data DL3, the count value becomes "2".
3". Therefore, the comparison circuit 33 generates a coincidence output at the front end of the data string length data DL3 (15th
Figure (g)). The output of this comparison circuit 33 is applied to the control circuit 22. The control circuit 22 thereby switches SW5.
and turn off the switch SWI (FIG. 15(h)). When the switch SW1 is turned on, the data string length setting circuit 14 starts reading the data string length data DL3, thereby setting the data string length data DL3 in the data string length setting circuit 14. When the data string length setting circuit 14 outputs a data string length data read completion signal (FIG. 15(d)), the switch sw1 is turned off. Note that when receiving the signal with this subframe configuration, the data conversion circuit 2o passes the signal with this subframe configuration as it is, and the switch SW4 is in the state (
A-B).

In addition, in the configuration shown in FIG. 14, the operation when an input signal of the main frame configuration is added is shown in FIG.
This is the same as shown in the timing chart of FIG.

Note that the node number setting for the node address setting circuit 32 may be set by operating a predetermined switch provided in each node, or by sending out a signal having a subframe configuration (not shown) from the main controller 100. The setting may be performed by receiving a signal having a subframe configuration.

FIG. 16 shows another embodiment in which the input signal has a frame structure as shown in FIG. 17(a). In this embodiment, two start codes, an input data start code and an output data start code, are used as shown in FIG. It is configured using a frame configuration signal that allocates the output data, which is a data area from which data is extracted, to separate frames. Here, the data string length data inserted after the input data start code is the data string length of input data L (1) bits and the data string length of output data L (
o) Represents the data string length corresponding to the sum of bits.

The node configuration of this embodiment shown in FIG. 16 has an input data start code detection circuit 12a instead of the start code detection circuit 12 in the configuration of the node 10 shown in FIG.
and an output data start code detection circuit 12b,
It is constructed by providing an input data start code detection circuit 23a and an output data start code detection circuit 23b instead of the start code detection circuit 23.

7 The operation of this embodiment is such that the data bit length N (i) from the sensor group 1 added to the input data is the bit length g (0) of the data extracted from the output data for output to the actuator group 2. If larger than Ω(1)〉Ω(
0) is shown in the timing chart in FIG.
(1) <f) The case of (o) is shown in a timing chart in FIG. Here, the timing chart shown in FIG. 17 shows that the data shown in FIG.
It is the same as shown in FIG. 5 except that it is bit delayed. Similarly, the timing chart shown in Figure 1.8 is the same as the one shown in Figure 6, except that the data shown in Figure 5 is divided into input data and output data with an output data start code in between. be.

In FIGS. 17 and 18, the switch SW2 is turned on from the front end of the input data to the rear end of the stop code, and the data string length counter 15 counts the data string length during this period. Since the bit lengths of the start code and stop code are known, the result data string length counter 15 counts the data string length of the sum of the data string length L (i) of the input data and the data string length L (o) of the output data. That means you are doing it. In this embodiment, the data string length is determined depending on whether the data string length indicated by the data string length data input next to the input data start code matches the data string length of the sum of the actually counted input data and the input data. Detect anomalies.

Note that in the configuration shown in FIG. 16, the start code detection circuits 23a, 23b and the stop code detection circuit 24 are not provided, and the input side input data output from the start code detection circuit 12a, the start code detection output, and the start code detection The input side output data start code detection output output from the circuit 12b and the input side stop code detection output output from the stop code detection circuit 13 are each delayed by a predetermined bit (the number of bits delayed by the data conversion circuit). A signal equivalent to the voice power of the start code detection circuit 23 and stop code detection circuit 24 described above may be generated.

FIGS. 19 and 20 show the operation of another embodiment when a signal with a frame structure as shown in FIG. 19(a) is used as an input signal jJ (i) > Ω(o) and g(i) <
II (o) is shown. In this case, the data string length data corresponds only to the data string length (0) of the output data. In this embodiment, a data string length abnormality is detected based on whether the data string length indicated by the data string length data matches the data string length of the actually counted output data. In this embodiment, the output data start code detection circuit 12
After the input side output data start code detection output (FIG. 19(e) or FIG. 20(e)) output from the data string length setting circuit 14 is generated, the data string length data read completion signal (FIG. 19) is output from the data string length setting circuit 14. The data string length data setting circuit sets the data string length data by turning on the switch SW1 (Fig. 19 (N) or Fig. 20 (g)) until the problem (g) or problem 20 (g)) is generated. 14, the data string length data is read into the data string length data setting circuit 14, and the stop code is detected by the stop code detection circuit 13 from the time when the data string length data reading completion signal is generated (see FIG. 19(e). ) or FIG. 20(e)), and the data string length counter 15 is operated during this period to set the output data string length L(0>). is configured to count.

Further, the switch SW4 is the output side output data start code detection output (FIG. 19 (r) or FIG. 20 (r)) 1 output from the output data start code detection circuit 24.
．． : From the state (A-C) after the bit length of the data string length data (e.g. 8 bits) has elapsed from the output side output data start code detection output generation. switched to state (A-B),
Output side stop code detection output output from the stop code detection circuit 24 (FIG. 19(i) or FIG. 20(
1)) The state (A-B) is switched to the state (A-D). The subsequent operations are the same as those shown in FIGS. 5 and 6.

In addition, in FIG. 19 and FIG. 20, the configuration is such that only the data string length abnormality of the output data is detected, but it can be similarly configured so that only the data string length abnormality of the input data is detected. In this case, for example, a signal with a frame configuration as shown in FIG. 17(a) is used, the data string length data is set to indicate only the data string length of the input data, and the switch SW
2 may be turned on from the time when the data string length data read completion signal is generated until the time when the output data start code is detected, and the data string length counter 15 is operated during this period to count only the data string length of the input data.

FIG. 21 shows a node configuration of another embodiment using signals having a frame structure as shown in FIG. 22(a). In this case, as shown in FIG. 22(a), two data string length data, input data string length data and output data string length data, are introduced, and thereby data string length abnormalities of input data and output data are detected. It is configured so that they can be checked separately.

In the configuration shown in FIG. 21, an input data data string length setting circuit 14a is used instead of the data string length setting circuit 14 shown in FIG. The data string length counter 15a and the output data string length counter 15b1 are constructed by providing an input data string length correctness judgment circuit 16a and an output data data string length judgment circuit 16b in place of the data string length correctness judgment circuit 16. Further, a switch SW6 is provided on the input side of the output data data string length setting circuit 14b, and a switch SW6 is provided on the input side of the output data data string length setting circuit 14b.
A switch SW7 is provided on the input side of b.

The operation of the embodiment shown in FIG. 21 is shown in FIGS. 22 and 23.
As shown in the figure. Here, FIG. 22 shows that the data string length g(1) of the data to be added is the data string length D (o
) (N (i) > D (o)), and FIG. 23 shows the case where 0 (1) < D (o).

In this embodiment, the switch SW1 is activated after the input data start code detection output from the input data start code detection circuit 12a is generated (see FIG. 22).
C) or FIG. 23(C)) Until the input data data string length setting circuit 14a outputs the input data data string length data read completion signal (FIG. 22(g) or FIG. 23(C))
g))) (Fig. 22 (II) or 23).
(++)), the input data string length setting circuit 14a reads the input data string length data, and the switch SW6 receives the input side output data start code detection output from the output data start code detection circuit 12b. After the occurrence (Figure 22 (e) or Figure 23 (e))
Until the output data data string length setting circuit 14b outputs the output data data string length data reading completion signal (second block).
(h) or Fig. 23 (h)).
2(g) or FIG. 23(g)), the operation of reading the output data data string length data into the output data data string length setting circuit 14b is performed, and the switch SW2 generates the input data data string length reading completion signal. 22(e) or 23(e) until the input side output data start code detection output is generated from the output data start code detection circuit 12b (FIG. 22(n) or 23rd
(n)), during this time the input data data string length counter 15
A is operated to count the data sublength of the input data.

Switch SW7 output data The data string length reading completion signal is generated (FIG. 22 (h) or FIG. 22 (h)) until the input side stop code detection output is generated from the stop code detection circuit 13 (FIG. 22 ( 1) or Figure 23 (
1)) is turned on (FIG. 22(r) or FIG. 23(r)), and during this period the output data data string length counter 15b
Operate and count the data string length of the output data.

The input data string length correctness/incorrect determination circuit 16a compares the outputs of the input data string length setting circuit 14a and the input data string length counter 15a, and detects that the input data string length is abnormal if the two do not match. Further, the output data string length correctness determination circuit 16b compares the outputs of the output data string length setting circuit 14b and the output data string length counter 15b, and detects that the output data string length is abnormal if the two do not match.

When an input data string length error is detected by the input data string length correctness determination circuit 16a, or when an output data data string length abnormality is detected by the output data data string length correctness determination circuit 16b, or error check code inspection. When a code error is detected in the circuit 17 or an error code is detected in the error code detection circuit 18, the output of the OR circuit OR becomes high level, and in this case, the switch SWO is switched to the error code detection circuit side. An error code is added to the output signal. Other operations are the same as those shown in FIG.

FIG. 24 shows another embodiment in which input data data string length data and output data data string length data are distributed to each node using signals of a subframe structure different from signals of the main frame structure. It is something. In this embodiment, the input data data string length data and the output data data string length data are removed from the signal of the main frame configuration, the data string length data conversion circuit 19 is removed, and the receiving circuit 11 is
The output of is directly connected to contact C of switch SW4,
This is the same as that shown in FIG. 21, except that the input data data string length data and the output data data string length data are distributed to each node using a signal having a subframe configuration as shown in FIG. 27(a). .

The configuration shown in FIG. 24 is the same as that shown in FIG.
It is configured by providing 0.

25 and 26 are timing charts showing the operation of each node when a main frame configuration signal is input in this embodiment, and FIG. 25 shows the data string length g( 1) is larger than the data string length fl (o) of the data extracted from the output data, and FIG. 26 shows the case where the data string length fl (i) of the data added to the input data is smaller than the output data. The timing charts shown in FIGS. 25 and 26 are basically the same as those shown in FIGS. 22 and 23, except for the processing of input data string length data and output data string length data. That is, Fig. 25, 2nd
In FIG. 6, the input signal does not include the input data string length data and the output data string length data, so the switch SWI and the switch SW6 remain off (see FIGS. 25(k) and 26(o)). Figure (k
), (o)), input data data string length setting circuit 14a
The input data string length data is not read into the output data string length setting circuit 14b, and the output data string length data is not read into the output data string length setting circuit 14b.

The switch SW2 is connected to the input terminal from the output data start code detection circuit 12b after the input side input data start code detection output (FIG. 25(c) or FIG. 26(C)) is generated from the input data start code detection circuit 12a. It remains on until the output data start code detection output (FIG. 25(e) or FIG. 26(0)) is generated, the input data string length counter 15a counts the input data string length, and the switch is turned on. SW7 is turned on after the input terminal output data start code detection output is generated until the input side stop code detection output (FIG. 25 (g) or FIG. 26 (g)) is generated from the stop code detection circuit 13. The output data data string length counter 15
At step b, the length of the output data string is counted. Further, the switch SW4 does not switch to the state (A-C).

FIG. 27 shows the operation of each node in this embodiment when a signal having a subframe structure as shown in FIG. 27(a) is input. The operation for signals having this sub-frame structure is basically the same as that described in FIGS. 12 and 13. However, in this case, Fig. 27(a)
As shown in the figure, since the signal of the sub-frame configuration includes two data string length data for each node, that is, input data data string length data and output data data string length data, the reading operation of each data string length data is is Figure 12,
It is different from Fig. 13. That is, in FIG. 27, after the input side sub-frame start code detection output (FIG. 27(C)) is output from the sub-frame start code detection circuit 28, the input data string length setting circuit 14a outputs the input data string. Long data reading completion signal (Figure 27(d)
)) is generated, the switch SWI is turned on until the input signal of the subframe configuration (Fig. 27(a)
), the input data string length data D L K (1) corresponding to this node is read into the input data string length setting circuit 14a. Further, after the input data string length data read completion signal is generated, the output data string length setting circuit sends the output data string length read completion signal (second
The switch SW7 is turned on until the signal shown in FIG. 7(e) is generated, and as a result, the output data string length data D L K ( o) is read into the output data data string length setting circuit 14b. In this case, the data conversion circuit 20 also converts the input signal (second
7 (a)) is delayed by the number of bits corresponding to the length of the data string length data corresponding to its own node, that is, the data string length of the sum of the input data data string length data and the output data data string length data. The switch SW4 is configured to output the sub-frame start code detection circuit 29.
The state is switched from state (A-B) to state (A-C) by the output-side sub-frame start code detection output output from the sub-frame stop code detection circuit 30, and by the output-side sub-frame stop code detection output output from the sub-frame stop code detection circuit 30. The state (A-C) is switched to the initial state (A-B).

FIG. 28 shows still another embodiment in which input data data string length data and output data data string length data are distributed to each node by signals having a subframe configuration. In this embodiment, the node address of each node is set in the node address setting circuit 32, and this node address is used to generate the input signal of the subframe configuration (see FIG. 29(a)).
) is configured to read input data data string length data and output data data string length data corresponding to each node into each node.

In this embodiment, the operation of each node when an input signal having a main frame structure is applied is the same as that shown in the timing charts of FIGS. 25 and 26.

FIG. 29 shows the operation of each node in this embodiment when an input signal having a subframe configuration is applied. The operation for the input signal of this sub-frame configuration is the first
This is basically the same as that explained using the timing chart in FIG. However, in this embodiment, since two data string length data, input data string length data and output data string length data, are used, the operation of the sub-frame frame counter 31 and the input data string length setting circuit 14a are
The operation of the output data string length setting circuit 14b is different from that shown in FIG. 15. That is, when the input side sub-frame start code detection output (FIG. 29(C)) is generated from the sub-frame start code detection circuit 28, the switch SW5 (FIG. 29(j)) is turned on and the sub-frame frame counter 31 is turned on. The operation starts, but in this embodiment, two data string length data, input data string length data and output data string length data, are set for each node, so the subframe frame counter 31 is set to 2. By detecting two frames, that is, a frame to which input data data string length data is allocated and a frame to which output data data string length data is allocated,
It is configured to count up. In this case, the node 10 shown in FIG. 28 corresponds to the third node, and data corresponding to "3" is set in the node address setting circuit 32. Therefore, from the comparison circuit 33, 3
A match signal (FIG. 29(h)) is generated at the timing when the input data string length data corresponding to the th node is input, and this turns off SW5 and turns on switch SW1. This switch SWI continues to be on until the input data string length setting circuit 14a generates the input data string length data read completion signal (FIG. 29(d)), thereby causing the input signal of the sub frame configuration (the From FIG. 29(a), input data string length data D L 3 (1) corresponding to this node 10 is read into the input data string length setting circuit 14a. Further, the switch SW6 is activated by the output data data string length setting circuit 14 after the input data string length data read completion signal is generated.
Output data data string length data read completion signal (second
The output data string length data D L 3 (o) corresponding to this node 10 is changed from the input signal (FIG. 29(a)) to the output data string. It is read into the length setting circuit 14b.

By the way, in the above-described embodiment, in order to easily distinguish between the start code and stop code and the data in the data area that is input or output at each node, the data in the data area is encoded in a predetermined manner, or is encoded in a predetermined manner. It has been explained that a configuration is adopted in which "0" is inserted for each bit. However, in this case, a problem arises in that the length of the data string in the data area becomes long and the transmission efficiency decreases. For example, if we consider a configuration in which "0" is encoded as "01" and "1" as "10", the length of the data string in the data area will be twice as long as when this encoding is not performed.

Therefore, in the embodiment shown in FIG. 30, by utilizing the fact that data string length data is given to each node, the switches 5WOI and 5W are used while receiving data in the data area.
The special code detection circuit, ie, the start code detection circuit 12.23 and the stop code detection circuit 13.24, is configured to be inoperable by turning off O2. As a result, there is no risk that the data in the data area will be mistakenly detected as a special code, so there is no need to perform special encoding or other processing on the data in the data area, and the reduction in transmission efficiency due to the sub-length of the data string can be avoided. It can be prevented.

Figures 31 and 32 are timing charts showing the operation of switches 5W01 and 5W02 when configured in this way. Indicates the case where the data string length of the data extracted from the data area is longer than Ω(0), and the 32nd
The figure shows the data string length N (1
) is the data string length D (
o) A shorter case is shown. The switch 5WOI is turned off from the detection of the input signal (Fig. 31 (a) or Fig. 32 (a)) start code to the rear end of the data area (
31 (e) or 32 (C)), during this period the start code detection circuit 12 and the stop code detection circuit 1
3 becomes inoperative, and switch 5WO2 outputs the output signal (
The start code detection circuit 23 and The stop code detection circuit 24 becomes inoperative. Other operations are similar to those shown in FIG.

In the embodiment shown in FIG. 30, when the input signal or the output signal is in the data area in the configuration shown in FIG. 9, 14, 16, 21,
A similar configuration can be made in FIGS. 24 and 28.

〔Effect of the invention〕

As explained above, according to the present invention, data string length data indicating the data string length of the data area input to each node is provided to each node, and data string length data of the data area actually input is provided to each node. By counting the data and comparing the counted value with the given data string length data, data string length abnormalities are checked. , this can be reliably detected.

Further, by detecting the data string length, it is possible to reliably prevent malfunctions and runaways of the device. In addition, by using a configuration that prohibits detection of special codes such as start codes and stop codes while data in the data area is being input using data string length data, data in the data area may be mistakenly detected as special codes. Malfunctions can also be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a series control device according to the present invention, FIGS. 2 and 3 are timing charts showing an example of its operation, and FIG. 4 is a block diagram showing an example of this series control device. A block diagram showing an example of the configuration of a node, FIGS. 5, 6, 7, and 8 are timing charts explaining the operation of the node shown in FIG. 4, and FIG. FIG. 10, FIG. 11, FIG. 12, and FIG. 13 are timing charts explaining the operation of the node shown in FIG. 9, and FIG. FIG. 15 is a block diagram showing an example of the configuration of nodes related to yet another embodiment of the series control device.
4 is a timing chart explaining the operation of the node shown in FIG.
8, FIG. 19, and FIG. 20 are timing charts explaining the operation of the node shown in FIG. 16, and FIG. 21 is a block diagram showing an example of the configuration of a node related to still another embodiment of this serial control device. , FIGS. 22 and 23 are timing charts explaining the operation of the nodes shown in FIG.
FIG. 4 is a block diagram showing a configuration example of a node according to yet another embodiment of this series control device, and FIGS. 25, 26, and 27 are timing charts explaining the operation of the nodes shown in FIG. 24. , FIG. 28 is a block diagram showing an example of the configuration of a node related to yet another embodiment of this serial control device, FIG. 29 is a timing chart explaining the operation of the node shown in FIG. 28, and FIG. A block diagram showing a configuration example of a node according to yet another embodiment of the serial control device, and FIGS. 31 and 32 are timing charts illustrating the operation of the node shown in FIG. 30. 1.1-1 to 1-n...sensor group, 2.2-1 to 2-
n...actuator group, 10.10-1 to 10-n
...Node, 100... Main controller.

Claims (1)

[Claims] (1) A plurality of nodes are connected in series, and one or more terminals are connected to each node, and each node receives a signal from a previous node and is connected to its own node. In a serial control device that processes a signal input from a terminal or a signal output to the terminal and sends it to a subsequent node, the signal from the previous node indicates the column length of data included in the signal. each node includes a counting means for counting the data string length of the data included in the signal from the preceding node; and a counting means for comparing the counted value of the counting means with the data string length data. , a comparison means for generating an error signal when the counted value of the counting means does not match the data string length indicated by the data string length data; and a comparison means for outputting the data string length data included in the signal from the previous stage from its own node. a data string length data conversion means for converting data into data string length data corresponding to the data string length of data to be processed, and transmitting the converted data string length data by including it in a signal to be sent to a subsequent node. Device. (2) The signal from the previous node is a serial signal in which a start code, data string length data indicating the string length of data sent from the previous node, data sent from the previous node, and a stop code are sequentially arranged. Claims (1)
) Line length control device. (3) The counting means starts the counting operation after a time period corresponding to the data string length of the data string length data has elapsed after the detection of the start code, and ends the counting operation upon detection of the stop code. series controller. (4) The comparison means includes a data string length setting circuit that sets a data string length by reading data string length data included in a signal from a previous node upon detection of a start code; Claim (2) further comprising a comparison circuit that compares the set data string length and the output of the counting means.
) Series control device described. (5) The data string length data conversion means adds the data string length of the data added at its own node to the data string length indicated by the data string length data included in the signal from the previous stage, and sends the result to the subsequent node. 2. The serial control device according to claim 1, further comprising adding means for forming a data string length. (6) The data string length data conversion means subtracts the data string length of the data deleted at its own node from the data string length indicated by the data string length data included in the signal from the previous stage, and sends the result to the subsequent node. 2. A series control device according to claim 1, further comprising subtraction means for forming a column length. (7) The data string length data conversion means adds the data string length of the data added at its own node to the data string length indicated by the data string length data included in the signal from the previous stage, and deletes it at its own node. 2. The serial control device according to claim 1, further comprising adding/subtracting means for subtracting the data length of the data to form a data string length to be sent to a subsequent node. (8) The signal from the previous node includes a data area,
2. The serial control device according to claim 1, wherein each node adds data from a terminal connected to its own node to the front end of the data area. (9) The signal from the previous node includes a data area,
2. The serial control device according to claim 1, wherein each node adds data from a terminal connected to its own node to the rear end of the data area. (10) The signal from the previous node includes a data area, and the rear end of the data area includes data to the terminal connected to its own node, and each node sends the signal to the terminal connected to its own node. 2. The serial control device according to claim 1, wherein the data is deleted from the rear end of the data area. (11) The signal from the previous node includes a data area, and the front end of the data area includes data to the terminal connected to its own node, and each node transmits data to the terminal connected to its own node. The serial control device according to claim 1, wherein data is deleted from the front end of the data area. (12) The signal from the previous node includes a data area and includes data to the terminal connected to its own node at the rear end of the data area, and each node receives data from the terminal connected to its own node. The serial control device according to claim 1, wherein data for a terminal connected to the own node is added to the front end of the data area, and data for a terminal connected to the own node is deleted from the rear end of the data area. (13) The signal from the previous node includes a data area and includes data to the terminal connected to its own node at the front end of the data area, and each node transmits data to the terminal connected to its own node. The serial control device according to claim 1, wherein data is deleted from the front end of the data area, and data from a terminal connected to its own node is added to the rear end of the area. (14) The serial control device according to claim (2), wherein each data in the data area sent from the preceding node is encoded into a plurality of bits to facilitate identification between the start code and the stop code. (15) According to claim (2), each data in the data area sent from the previous node has "0" inserted every predetermined number of bits to facilitate identification from the start code and stop code. series controller. (16) If an error signal is generated from the comparison means,
2. The serial control device according to claim 1, further comprising error code adding means for adding an error code indicating the occurrence of the error signal to a signal sent to a subsequent node. (17) The serial control device according to claim (1), further comprising means for prohibiting transmission of a signal to a terminal connected to its own node when an error signal is generated from the comparison means. (18) The signal from the previous node is the start code,
Data string length data indicating the data string length of data sent from the previous node, data sent from the previous node, stop code, error check code for detecting data errors in data sent from the previous node ,
If an error code is sent from the previous stage, the claim (1) includes a serial signal in which the error code is sequentially arranged.
) Series control device described. (19) Error check code inspection means that detects data errors in data sent from the previous node by detecting the error check code sent from the previous node, and generates an error signal if there is a data error. The series control device according to claim 18, further comprising: (20) If an error signal is generated from the comparison means, an error signal is generated from the error check code inspection means, or an error code is sent from the previous node, the subsequent stage The serial control device according to claim 19, further comprising error code adding means for adding an error code to the signal sent to the node. (21) The series control device according to claim (1), wherein the plurality of nodes include a main controller and are connected in a closed loop. (22) The series control device according to claim (1), wherein the plurality of nodes include a main controller and are connected in an open loop. (23) The serial control device according to claim (1), wherein the terminal includes a sensor. (24) The serial control device according to claim (1), wherein the terminal includes an actuator. (25) The serial control device according to claim (1), wherein the terminal includes a sensor and an actuator. (26) The signal from the previous node includes a serial signal in which an input data start code, data string length data, input data, output data start code, output data, and stop code are arranged in sequence, and the input data is input from the terminal. The output data corresponds to the data output to the terminal, and the data string length data corresponds to the data string length of the sum of the data string length of the input data and the data string length of the output data. The series control device according to claim (1). (27) Claim (26) wherein the counting means starts the counting operation in response to a reading completion signal indicating completion of reading the data string length data, and ends the counting operation upon detection of a stop code.
) Series control device described. (28) Claim (26) wherein the counting means starts the counting operation after a time period corresponding to the data string length of the data string length data has elapsed after the detection of the input data start code, and ends the counting operation upon detection of the stop code. ) Series control device described. (29) The comparison means includes a data string length setting circuit that sets the data string length by reading the data string length data included in the signal from the previous node upon detection of the input data start code; and the data string length setting circuit. Claim (2) further comprising a comparison circuit that compares the data string length set in the circuit and the output of the counting means.
6) The series control device described. (30) The data string length data conversion means adds the data string length of the data added to the input data at its own node to the data string length indicated by the data string length data included in the signal from the previous stage, and also adds the data string length of the data added to the input data at its own node. Claim (26) further comprising an adding/subtracting means for subtracting the data string length of the data deleted from the output data to form a data string length to be sent to a subsequent node.
) Series control device described. (31) The signal from the previous node includes a serial signal in which an input data start code, input data, output data start code, data string length data, output data, and stop code are sequentially arranged, and the input data is input from the terminal. 2. The serial control device according to claim 1, wherein the output data corresponds to data to be output to a terminal, and the data string length data corresponds to a data string length of the output data. (32) Claim (31) wherein the counting means starts the counting operation after a time period corresponding to the data string length of the data string length data has elapsed after the detection of the output data start code, and ends the counting operation upon detection of the stop code. ) Series control device described. (33) The comparison means includes a data string length setting circuit that sets the data string length by reading the data string length data included in the signal from the previous node upon detection of the output data start code; and the data string length setting circuit. Claim 3 further comprising a comparison circuit that compares the data string length set in the circuit and the output of the counting means.
1) The series control device described above. (34) The data string length data conversion means subtracts the data string length of the data deleted from the output data at its own node to the data string length indicated by the data string length data included in the signal from the previous stage, and transmits the result to the subsequent node. 32. The serial control device according to claim 31, further comprising subtraction means for forming the length of the data string to be sent. (35) The signals from the previous node are input data start code, input data string length data, input data,
It includes a serial signal in which an output data start code, output data data string length data, output data, and a stop code are sequentially arranged, the input data corresponds to data input from a terminal, and the output data corresponds to data output to the terminal. According to claim (1), the input data string length data corresponds to the data string length of the input data, and the output data string length data corresponds to the data string length of the output data.
) Series control device described. (38) The counting means starts counting operation in response to a reading completion signal of input data data string length data, and ends the counting operation upon detection of an output data start code; and output data data string length data. 36. The serial control device according to claim 35, further comprising a second counting means that starts a counting operation in response to a reading completion signal and ends the counting operation upon detection of a stop code. (37) The comparison means is a first data string length setting circuit that sets the input data string length by reading the input data string length data included in the signal from the previous node upon detection of the input data start code. and a second data string length setting circuit that sets the output data string length by reading the output data string length data included in the signal from the previous node upon detection of the output data start code; A first method that compares the input data data string length set in the data string length setting circuit and the count value of the first counting means.
and a second comparison circuit that compares the data string length set in the second data string length setting circuit and the count value of the second counting means. Series controller. (38) Connect multiple nodes connected in series to the main controller, and connect one or more terminals to each node, and each node transmits the signal from the previous node to the terminal connected to its own node. In a serial control device that processes a signal input from the main controller or a signal output to the terminal and sends it to a subsequent node, the data string length of the data output from each node from the main controller to each node is a distributing means for distributing corresponding data string length data; a counting means provided at each node for counting the data string length of data included in a signal from a preceding node; and an output of the counting means and the distributing means. and a comparison means for comparing the data string length data distributed by the data string length data and generating an error signal if the counted value of the counting means does not match the data string length indicated by the data string length data. (39) The distribution means sends a signal containing a serial signal in which a subframe start code, a plurality of data string length data representing the data string length output from each node, and a subframe stop code are sequentially arranged to each node as a subframe. 39. The serial control device according to claim 38, further comprising a transmitting means, wherein the signal from the preceding node comprises a main frame including a serial signal in which a start code, data, and stop code are sequentially arranged. (40) The subframe transmitted from the previous node includes data string length data corresponding to its own node at the front end of the data string length data area, and the distributing means is provided at each node and transmits the start code of the subframe. a data string length setting circuit that sets the data string length by reading the data string length data at the front end of the data string length data area by detecting the data string length data area; 40. The serial control device according to claim 39, further comprising a data string length data processing circuit that deletes data string length data and sends the data to a subsequent node. (41) The distributing means includes a detecting means provided in each node and detecting data string length data corresponding to its own node from the data string length data area of the sub-frame; and a detecting means provided in each node and detected by the detecting means. 40. The serial control device according to claim 39, further comprising data string length setting means for setting the data string length by reading the data string length data. (42) The detection means includes: a frame number setting circuit that sets the number of frames corresponding to its own node; a frame number counting circuit that counts the number of frames of sub-frames; and a frame number set by the frame number setting means and the frame number. 42. The serial control device according to claim 41, further comprising a comparison circuit that detects the data as its own data string length data when the counted value of the number counting means matches. (43) The serial control device according to claim (40), wherein the counting means starts counting operation upon detection of a start code of the main frame, and ends the counting operation upon detection of a stop code. (44) The serial control device according to claim (43), wherein the comparison means includes a comparison circuit that compares the data string length set in the data string length setting circuit and the count value of the counting means. (45) Claim (45) wherein each piece of data sent from the preceding node is encoded into multiple bits to facilitate identification from the start code and stop code.
40) The series control device described. (46) A claim in which "0" is inserted into every predetermined number of bits of each data sent from the previous node in order to facilitate identification from the start code and stop code.
40) The series control device described. (47) If an error signal is generated from the comparison means,
39. The serial control device according to claim 38, further comprising error code adding means for adding an error code indicating the occurrence of the error signal to a signal sent to a subsequent node. (48) The serial control device according to claim 38, further comprising means for prohibiting transmission of a signal to a terminal connected to its own node when an error signal is generated from the comparison means. (49) The signal from the previous node is the start code,
Data sent from the previous node, stop code,
Claim (3) consisting of a main frame including an error check code for detecting data errors in data sent from a previous stage node, and a serial signal in which error codes are sequentially arranged if an error code is sent from the previous stage.
8) The series control device described. (50) Error check code inspection that detects data errors in data received by the node at the current stage by checking the error check code sent from the previous node, and generates an error signal if there is a data error. 50. A series control device according to claim 49, further comprising means. (51) If an error signal is generated from the comparison means, an error signal is generated from the error check code inspection means, or an error code is sent from the previous node, the subsequent stage 51. The serial control device according to claim 50, further comprising error code adding means for adding an error code to the signal sent to the node. (52) The signal from the previous node consists of a main frame including a serial signal in which an input data start code, input data, output data start code, output data, and stop code are arranged in sequence, and the input data is input from a terminal. 39. The serial control device according to claim 38, wherein the output data corresponds to data to be output to a terminal. (53) The distributing means includes means for transmitting to each node a subframe containing data string length data representing the sum of the data string length of input data and the data string length of output data of each node; 53. The serial control device according to claim 52, further comprising data string length setting means provided in the sub-frame for setting the data string length by reading data string length data corresponding to its own node from the sub-frame. . (54) The serial control device according to claim (52), wherein the counting means starts the counting operation upon detection of an input data start code and ends the counting operation upon detection of a stop code. (55) The serial control device according to claim (54), wherein the comparison means includes a comparison circuit that compares the data string length set in the data string length setting circuit and the count value of the counting means. (56) The distributing means includes means for transmitting to each node a sub-frame containing data string length data representing the data string length of the output data of each node, and means provided in each node to select a sub-frame from among the sub-frames. 53. The serial control device according to claim 52, further comprising data string length setting means for setting the data string length by reading data string length data corresponding to the data string length. (57) The serial control device according to claim (52), wherein the counting means starts the counting operation upon detection of an output data start code and ends the counting operation upon detection of a stop code. (58) The serial control device according to claim (57), wherein the comparison means includes a comparison circuit that compares the data string length set in the data string length setting circuit and the count value of the counting means. (59) The distributing means is means for transmitting to each node a sub-frame including input data string length data representing the data string length of the input data of each node and output data data string length data representing the data string length of the output data. and a first data string length setting means provided in each node and configured to set the input data string length by reading input data string length data corresponding to its own node from the sub-frame; 2. A second data string length setting means provided in a node and configured to set an output data string length by reading output data string length data corresponding to the own node from the sub-frame. (52) The series control device described in (52). (60) The counting means includes a first counting means that starts counting operation upon detection of an input data start code and ends the counting operation upon detection of an output data start code, and a first counting means that starts counting operation upon detection of an output data start code. 53. The serial control device according to claim 52, further comprising second counting means that starts and ends the counting operation upon detection of a stop code. (61) The comparison means includes a second comparison circuit that compares the input data string length set in the first data string length setting means and the count value of the first counting means; 61. The serial control device according to claim 60, further comprising a second comparison circuit that compares the output data string length set in the setting means and the count value of the second counting means. (62) Connect multiple nodes in series and connect one or more terminals to each node, and each node receives the signal from the previous node and the signal input from the terminal connected to its own node. Alternatively, in a serial control device that processes a signal output to the terminal and sends it to a subsequent node, the signal from the previous node includes a start code and data string length data indicating the string length of data included in the signal. , a stop code, and each node includes: a start code detection means for detecting the start code; a stop code detection means for detecting the stop code; and a stop code detection means for detecting the start code and then detecting the start code. A serial control device comprising inhibiting means for inhibiting detection operations of the start code detecting means and the stop code detecting means until a data string length indicated by the string length data is reached.