JPH01290191A - Sense amplifier circuit device - Google Patents

Abstract

PURPOSE:To exactly read data by using the data of an arithmetic result for the exclusive OR of the respective outputs of first and second amplifying means as the determining signal of the data for the output of a third amplifying means. CONSTITUTION:A first amplifying means A1 subtracts and amplifies a second input signal IN2 from a first input signal IN1 and amplifies the signal IN2. Then, a second amplifying means A2 subtracts the first input signal IN1 from the second input signal IN2 and amplifies the signal IN1. Next, a third amplifying means A3 amplifies the level of difference between the output of the first amplifying means A1 and the output of the second amplifying means A2 and after that, the operation of the exclusive OR is executed for the respective outputs of the first and second amplifying means A1 and A2. Then, the determining signal is outputted to show the determination of the data for an output OUT of the third amplifying means A3. Thus, the data can be exactly read in the output voltage of a sense amplifier circuit device to be the output of the third amplifying means A3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier circuit device for reading data stored in a memory device.

[Conventional technology] FIG. 2 is a circuit diagram of a conventional sense amplifier circuit.

In FIG. 2, a first input signal INI output from a storage device is input to an inverting input terminal of a differential amplifier A1 and a non-inverting input terminal of a differential amplifier A2, and is also input to a node via a transmission gate TG. It is input to N3. Further, the second input signal IN2 output from the storage device is input to the non-inverting input terminal of the differential amplifier At, and is also input to the inverting input terminal of the differential amplifier A2.

Here, the transmission gate TG is, for example,
P-channel MO3 field effect transistors (hereinafter referred to as PMOSFETs) are connected in parallel.

) and N-channel MOS field effect transistor (hereinafter referred to as
It is called NMOSFET. ).

Furthermore, the enable signal SE of this sense amplifier circuit is input to the gate of the PMOSFET of the transmission gate TG, and is also input to the gate of the NMOSFET via the invert INV. Furthermore, the enable signal SE is outputted as an output voltage confirmation signal OC via a delay circuit DL having a predetermined delay time Δt.

The signal output from the output terminal of the differential amplifier At is input to the non-inverting input terminal of the differential amplifier A3, while the signal output from the output terminal of the differential amplifier A2 is input to the non-inverting input terminal of the differential amplifier A3.
Human power is input to the inverting input terminal of. Furthermore, the signal output from the output terminal of this differential amplifier A3 is output as the output voltage OUT of this sense amplifier circuit.

In the conventional sense amplifier circuit configured as described above, the output voltage determination signal OC is changed to the enable signal SE which is simply manually inputted by the delay time Δt.
You're only getting delayed.

FIG. 3 is a timing chart showing the operation of the sense amplifier circuit of FIG. 2. In FIG. 3, the enable signal SE input from the storage device is delayed by the delay time Δt of the delay circuit DL to determine the output voltage. It is output as signal OC.

The output voltage OUT of this sense amplifier circuit is determined at times t1 and t3, and the determination signal OC is at the time t+.
, ts, respectively, the delay time Δt of the delay circuit DL is set so that the signal goes to H level at times t2 and t4, which are some time after ts, respectively.

[Problems to be Solved by the Invention] The delay time of the delay circuit DL is set constant as described above. On the other hand, for example, power supply voltage Vcc, ambient temperature,
If process parameters, etc. change, time 1 in FIG. ．． 1. The timing of determining the data of the output voltage of the sense amplifier circuit indicated by fluctuates, and the timing of determining the data set by the delay circuit DL, indicated by time t3 in FIG. There was a problem in that it became impossible to read data at the output voltage of the amplifier circuit.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a sense amplifier circuit device that can accurately read data at the output voltage of the sense amplifier circuit device.

[Means for Solving the Problems] The present invention provides a first amplification means that subtracts and amplifies a second input signal from a first input signal, and a first amplification means that subtracts and amplifies a second input signal from a first input signal.
a second amplifying means for subtracting and amplifying the input signal; a third amplifying means for amplifying the difference level between the output of the first amplifying means and the output of the second amplifying means; and second
It is characterized by comprising a calculation means for calculating an exclusive OR of each output of the third amplification means and outputting a determination signal indicating determination of the data of the output of the third amplification means.

[Operation] With the above configuration, the first amplifying means subtracts and amplifies the second input signal from the first input signal, and the second amplifying means subtracts and amplifies the second input signal from the second input signal. The first input signal is subtracted and amplified.

Next, after amplifying the level of the difference between the output of the third amplifying means or the first amplifying means and the output of the second amplifying means, the calculating means An exclusive OR operation is performed on the outputs, and a confirmation signal indicating confirmation of the data output from the third amplification means is output.

Therefore, by using the data of the exclusive OR operation result of each output of the first and second amplification means as a confirmation signal indicating the confirmation of the data of the output of the third amplification means, the conventional example can be improved. Even if the power supply voltage Vcc, ambient temperature, process parameters, etc. change, the level of the confirmation signal does not change. This makes it possible to accurately read data at the output voltage of the sense amplifier circuit device, which is the output of the third amplification means.

[Embodiment] FIG. 1 is a block diagram of a sense amplifier circuit that is an embodiment of the present invention.The sense amplifier circuit of this embodiment has a delay circuit that is different from the conventional sense amplifier circuit of FIG. D
It is characterized in that it does not include an exclusive OR gate XOR that uses two inputs, the output of the differential amplifier A1 and the output of the differential amplifier A2. The above differences will be explained in detail below.

In FIG. 1, the output terminal of the differential amplifier A1 is connected to the first input terminal of the exclusive OR gate xOR, and the output terminal of the differential amplifier A2 is connected to the second input terminal of the exclusive OR gate
connected to the input terminal of

An output voltage confirmation signal OC indicating when data of the output voltage of the sense amplifier circuit is confirmed is output from the output terminal of the exclusive OR gate XOH.

The operation of the sense amplifier circuit configured as above is explained in the first section.
Explain with reference to the table.

First, when the enable signal SE is at the L level and the levels of the input signals lN14N2 are equal, the levels at the nodes Nl and N2 are at the H level, and as a result, the output voltage confirmation signal OC is at the L level.

Next, the enable signal SE is at H level and the input signal I
N1. When the levels of IN2 are equal, the levels of node Nl and node N2 become H level, and as a result, output voltage determination signal OC becomes L level.

Further, when the enable signal SE is at the H level and the level of the input signal INI is higher than the level of the input signal IN2, the respective levels of the nodes N1 and N2 are set to the L level.
As a result, the output voltage confirmation signal OC becomes I (level).

Furthermore, when the enable signal SE is at H level and the level of input signal INl is lower than the level of input signal IN2, the levels of node Nl and node N2 become H level and L level, respectively, and as a result, the output voltage The confirmation signal OCh becomes less than H level.

Therefore, when enable signal SE is at H level and the level of input signal INI and input signal IN2 are different, output voltage confirmation signal OC becomes H level. That is, when the output voltage confirmation signal OC changes from L level to H level, it can be detected that the output voltage OUT of the sense amplifier circuit has been determined.

FIG. 4 is a circuit diagram of the sense amplifier circuit of FIG. 1.

In FIG. 4, the input signal INI is input to the node ND4 via the transmission gate TG, and is also input to the gate of the NMO5FET Nl and the gate of the NMOSFET N4 via the node ND3. On the other hand, input signal IN2 passes through node ND4 to NMO
Gate of SFET N2 and NMOSFET N5
input into the gate.

Furthermore, the enable signal SE is input to the gate of the PMOSFET of the transmission gate TG, and is also input to the gate of the NMOSFET via the inverter INV. Furthermore, the enable signal SE is applied to the gate of the pull-up PMO8FETpt, the pull-up PMO
8'FET P2 gate, NMOSFET N3
and the gate of NMOSFET N6.

Here, the source of PMOSFET PI is +5
It is connected to a DC power supply Vcc that outputs a DC voltage of V, and P
The drain of MOSFET PI is connected to node NDI. Further, the source of PMOSPET P2 is connected to the DC power supply Vcc, and the drain of PMOSPET P2 is connected to node ND2.

Differential amplifier AI consists of two PMOSFETs P3゜P4
and three NMOSFETs Nl, N2. Equipped with N3. In this differential amplifier AI, PMOSPET P
The source of the PMOSFET P3 and the source of the PMOSFET are both connected to the DC power supply Vcc, and the gate of the PMOSF'ET P3 and the gate of the PMOSFET P4 are connected together and connected to the drain of the NMOSFET N2.

Drain of PMOSFET P3 and NMOSFET
The drains of Nl are connected together and the PMOSFET
Connected to the drain of PI and node NDI. PM
The gate of OSFET P3 is PMOSF'ET P
4, and is connected to the gate and drain of NMOS
Connected to the drain of FET N2. NMOSF
The source of ET Nl is connected to the source of NMOSFET N2 and to the drain of NMOSFET N3. Furthermore, NMOS FET N
The source of 3 is connected to ground. This differential amplifier AI
The output terminal of is the node NDI, and the exclusive OR gate X
is connected to the first input terminal of OH, and is connected to the first input terminal of NMOS
Connected to the gate of FET N7.

Differential amplifier A2 consists of two 8MO3FETs P5゜P6
and three NMOSFETs N4. It includes N5 and N6. In this differential amplifier A2, 2MO8FET
The source of P5 and the source of 2MO8FET P6 are both connected to the DC power supply Vcc, and the gate of 8MO3FET P5 and the gate of PMO8FET P6 are connected together, and the drain of PMOSFET P5 and the NMOSFE are connected together.
Connected to the drain of T N4. PMOSFET
The drain of P6 and the drain of NMOSFET N5 are connected together and connected to the drain of PMOSPET P2 and node ND2.

Source of NMOSFET N4 and NMOSFET
The sources of N5 are connected together and NMO9F'ET
Connected to the drain of N6. Furthermore, NMOSF
The source of ET N6 is connected to ground. The output terminal of the differential amplifier A2 is connected to the node ND2, as well as to the second input terminal of the exclusive OR gate X0R and the gate of the NMO9F'ET N8.

Differential amplifier A3 consists of two PMOSFETs P7゜P8
and three NMOSFETs N7. N8. Equipped with N9. In this differential amplifier A3, PMOSFET P
The source of PMOSFET P7 and the source of PMOSFET P8 are both connected to the DC power supply Vcc, and the gate of 2MO8FET P7 and the gate of 2MO8FET P8 are connected together, and the drain of PMOSFET P7 and the source of NMOSFET P8 are connected together.
Connected to the drain of ET N7. Also, 2MO8
The drain of FET P8 and the drain of NMOSFET N8 are connected together and connected to the output signal OUT terminal of this sense amplifier circuit.

NMOSFET N7 source and NMOSFET
The sources of N8 are connected together and the NMOS FET
Connected to the drain of N9. Furthermore, NMO9F
'ET N9 gate is connected to DC power supply Vcc,
The source of NMOSFET N9 is connected to ground.

Furthermore, the output terminal of the exclusive OR game) XOH becomes the output terminal of the output voltage confirmation signal OC.

The sense amplifier circuit of FIG. 4 configured as above is as follows.
As shown in Table 1, the sense amplifier circuit operates in the same way as the sense amplifier circuit shown in FIG.

As explained above, the differential amplifiers A1 . Since the exclusive OR gate XOR which inputs each output terminal of A2 is provided, when the enable signal SE is at H level and the level of the input signal INI is different from the level of the input signal IN2, the exclusive OR gate XOR inputs the H level. Output voltage confirmation signal OC
is output, and when this signal OC changes from L level to H level, it can be detected that the data of the output voltage OUT of the sense amplifier circuit has been determined.

Table 1 [Effects of the Invention] As detailed above, according to the present invention, the exclusive OR operation result of each output of the first and second amplification means that subtracts and amplifies a 2g input signal is Since the data is used as a confirmation signal indicating the confirmation of the output data of the sense amplifier circuit device, even if the power supply voltage Vcc, ambient temperature, process parameters, etc. fluctuate as in the conventional example, the The signal level does not change. Therefore, there is an advantage that data at the output of the sense amplifier circuit device can be read out accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a sense amplifier circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional sense amplifier circuit, and FIG. 3 is a timing chart showing the operation of the sense amplifier circuit of FIG. 2. , FIG. 4 is a circuit diagram of the sense amplifier circuit of FIG. 1. At, A2. A3...Differential amplifier, TG...Transmission gate, INV...Inverter, XOR...Exclusive OR gate. Patent Applicant Rico Co., Ltd., Attorney-at-Law Patent Attorney Seihaku Ho and 1 other person;
CgT Figure 2 A1 Figure 3 1111-t @4th page

Claims (1)

[Claims] (1) A first amplification means that subtracts and amplifies a second input signal from a first input signal, and a second amplification means that subtracts and amplifies a first input signal from a second input signal. , third amplifying means for amplifying the difference level between the output of the first amplifying means and the output of the second amplifying means, and an exclusive OR of each output of the first and second amplifying means. A sense amplifier circuit device comprising: arithmetic means for performing an arithmetic operation and outputting a confirmation signal indicating confirmation of data output from the third amplification means.