JPH01289918A - Active matrix type liquid crystal display device and its driving method - Google Patents

Active matrix type liquid crystal display device and its driving method

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Publication number
JPH01289918A
JPH01289918A JP63120931A JP12093188A JPH01289918A JP H01289918 A JPH01289918 A JP H01289918A JP 63120931 A JP63120931 A JP 63120931A JP 12093188 A JP12093188 A JP 12093188A JP H01289918 A JPH01289918 A JP H01289918A
Authority
JP
Japan
Prior art keywords
liquid crystal
voltage
gate
display device
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63120931A
Other languages
Japanese (ja)
Inventor
Yorimasa Kamigaki
上垣 頼政
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63120931A priority Critical patent/JPH01289918A/en
Publication of JPH01289918A publication Critical patent/JPH01289918A/en
Pending legal-status Critical Current

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  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To decreases factors which decreases impedance and to realize high picture quality and high yield by equipping a transistor (TR) array substrate with source lines arranged in parallel to gate lines and equipping a counter substrate with counter electrodes which are arrayed in stripes at right angles to the gate lines. CONSTITUTION:This display device has source electrodes 10 connected to a common voltage, gate electrodes 11 connected in common by columns, drain electrodes 12, TFTs 13, liquid crystal 14, and counter electrodes 15 which are connected in common by rows and input signals. Namely, the TR array substrate is equipped with the source lines arranged in parallel to the gate lines and the counter substrate is equipped with the counter electrodes 15 which are arrayed in stripes at right angles to the gate lines. Thus, a display voltage input part is composed of the counter substrate in simple structure, so the factors which decrease the impedance are decreased to realize the high picture quality and high yield.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、電界効果型薄膜トラ・ンジスタ(以下TP
Tという)を用いたアクティブマトリックス型液晶表示
装置およびその駆動方法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention relates to field effect thin film transistors (hereinafter referred to as TP).
The present invention relates to an active matrix liquid crystal display device using an active matrix type liquid crystal display device (referred to as T) and a method for driving the same.

〔従来の技術〕[Conventional technology]

第3図は、例えば特開昭55−59494号公報に示さ
れた従来のアクティブマトリックス型液晶表示装置を駆
動する回路を、第4図は、その駆動波形を示す。これら
は4エレメントのみを示したが、これをX−Y方向に配
置しそれを適当に結線することにより、多ラインマトリ
ックス表示が可能になる。
FIG. 3 shows a circuit for driving a conventional active matrix liquid crystal display device disclosed in, for example, Japanese Patent Laid-Open No. 55-59494, and FIG. 4 shows its driving waveform. Although only four elements are shown, by arranging them in the X-Y direction and connecting them appropriately, a multi-line matrix display becomes possible.

第3図において1はソース電極、2はゲート電極、3は
ドレイン電極、4はTPT、5は液晶、6は対向電極を
示す。第3図のソース電極1からソース電圧■2、ゲー
ト電極2からゲート電圧v1を印加すると、T’FT3
は導通(ON)状態となり、ソース電極1からTPT3
のON抵抗(Ron)を通して液晶5に充電が行われる
。次にゲート電極2のゲート電圧を零にするとTPT4
は遮断(OFF)状態となり、液晶5の容量(C1c)
  5に充電されている電荷は、TPT4の遮断抵抗(
Roff)及び液晶の抵抗(Rlc)を通して放電をす
る。この時の各電極の電圧波形を第4図に示すが、Ro
ff) I?on、Rlc> Roffの関係があるた
め、ソース電極1に加わる電圧のデユーティ−が小さく
実効電圧が極めて小さいにもかかわらず、ドレイン電極
に生じる実効電圧、つまり液晶エレメントに印加される
実効電圧は非常に大きくなり、デユーティ−ファクター
が小さ(でも高コントラストの表示が行われることとな
る。
In FIG. 3, 1 is a source electrode, 2 is a gate electrode, 3 is a drain electrode, 4 is a TPT, 5 is a liquid crystal, and 6 is a counter electrode. When applying source voltage 2 from source electrode 1 and gate voltage v1 from gate electrode 2 in FIG. 3, T'FT3
becomes conductive (ON), and the source electrode 1 to TPT3
The liquid crystal 5 is charged through the ON resistance (Ron). Next, when the gate voltage of gate electrode 2 is made zero, TPT4
is in the cut-off (OFF) state, and the capacitance (C1c) of the liquid crystal 5
The electric charge charged in 5 is the cutoff resistance of TPT4 (
Roff) and the liquid crystal resistor (Rlc). The voltage waveform of each electrode at this time is shown in FIG.
ff) I? on, Rlc>Roff, so even though the duty of the voltage applied to the source electrode 1 is small and the effective voltage is extremely small, the effective voltage generated at the drain electrode, that is, the effective voltage applied to the liquid crystal element is extremely small. The duty factor is small (but a high contrast display is performed).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の液晶表示装置は以上のように構成されているので
、下記のような問題があった。
Since the conventional liquid crystal display device is configured as described above, it has the following problems.

■ 現在の駆動回路の構成上特にソースラインに高いイ
ンピーダンスが要求される。1走査時間の約10%回路
がアクティブの後はディセーブルされるからである。現
在のアレーはゲートラインとソースラインが二層構造に
なっていたりTPTが接続されていたりして複雑な回路
を形成している。そのためどうしてもソースラインのイ
ンピーダンスが下がり易く画質向上の妨げになっている
■ Due to the configuration of current drive circuits, high impedance is particularly required for the source line. This is because the circuit is active for about 10% of one scan time and then disabled. In current arrays, gate lines and source lines have a two-layer structure, or TPTs are connected, forming a complex circuit. Therefore, the impedance of the source line tends to drop, which hinders improvement in image quality.

■ 従来のアクティブマトリックス型液晶表示装置は、
ゲート電圧に対してソース電圧が一定していない為TF
TのId −Vg特性カベ十分活がされていないという
問題がある。第5図において、7はゲート電圧、8はソ
ース電圧、9は対向電極電圧である。例えば偶数フレー
ムでの各電圧を第5図のように設定した時のソース電圧
のゲート電圧との相対値を見るとゲート電圧が2゜V時
にはvgs−15v、ゲート電圧がOV時にはVgs−
−5Vであるが、奇数フレームではゲート電圧が20V
時にはVgs = 5V、ゲート電圧がOV時にはVg
s −−15Vである。次にTPTは一般的には第6図
のようなId = vg特性を示すがここで前述の奇数
フレームにおける各相対値でのドレイン電流1dは第6
図のA点(OFF)  B点(ON)の値になり通常1
00000以上必要と言われているRof f/Ron
比は1000以下となる。このように電圧条件によって
はRoff/Ron比が悪くなりアクティブマトリック
ス型液晶表示装置の住命である良好な電圧保持特性が得
られなくなり、画質も悪くなる可能性がある。
■ Conventional active matrix liquid crystal display devices are
TF because the source voltage is not constant with respect to the gate voltage.
There is a problem that the Id-Vg characteristic surface of T is not fully utilized. In FIG. 5, 7 is a gate voltage, 8 is a source voltage, and 9 is a counter electrode voltage. For example, when looking at the relative value of the source voltage to the gate voltage when each voltage in an even frame is set as shown in Figure 5, when the gate voltage is 2°V, it is vgs - 15V, and when the gate voltage is OV, it is Vgs -
-5V, but in odd frames the gate voltage is 20V
Sometimes Vgs = 5V, when gate voltage is OV Vg
s --15V. Next, TPT generally shows Id = vg characteristics as shown in Figure 6, but here, the drain current 1d at each relative value in the odd-numbered frame mentioned above is 6th
The value of point A (OFF) and point B (ON) in the diagram is normally 1.
Rof f/Ron, which is said to require more than 00000
The ratio will be 1000 or less. As described above, depending on the voltage conditions, the Roff/Ron ratio may deteriorate, making it impossible to obtain good voltage holding characteristics, which is the lifeblood of an active matrix liquid crystal display device, and possibly resulting in poor image quality.

■ 又、TPTにはゲート、ドレイン間の寄生容量Cg
dが存在し画質に影響を与える。第7図は1画素につい
ての等価回路図、第8図は部分チャート図である。ここ
でC1cは1画素の液晶の容量である。TPTのゲート
を開いてC1cにVdを充電してもゲートを閉じる際に
△Vd分ドロンブし、そのフレーム間はVd−△Vdだ
け保持される。△Vdの大きさは次式で決定される。
■ Also, TPT has a parasitic capacitance Cg between the gate and drain.
d exists and affects image quality. FIG. 7 is an equivalent circuit diagram for one pixel, and FIG. 8 is a partial chart diagram. Here, C1c is the capacitance of one pixel of liquid crystal. Even if the gate of TPT is opened and C1c is charged with Vd, when the gate is closed, it will be blown by ΔVd, and only Vd-ΔVd will be maintained between frames. The magnitude of ΔVd is determined by the following equation.

△Vd = (Cgd/C1c)x  Vg即ちVgs
が大きければ△Vdも大きくなりフレーム当たりの実効
値は小ざくなる。このようにこの△Vdがゲート、ドレ
イン間の寄生容51cgdの影響で出るものであってそ
の大きさはCgd、CdとVgs の兼合いで決まる事
は既に明らかにされている。従来の技術では同じON、
10FF比を得るのにより高いVgsを印加しなければ
ならず画質に悪影響を与えている。
△Vd = (Cgd/C1c) x Vg or Vgs
If ΔVd is large, ΔVd also becomes large, and the effective value per frame becomes small. As described above, it has already been made clear that this ΔVd is caused by the influence of the parasitic capacitance 51cgd between the gate and the drain, and its magnitude is determined by the balance between Cgd, Cd, and Vgs. With conventional technology, the same ON,
In order to obtain a FF ratio of 10, a higher Vgs must be applied, which adversely affects image quality.

この発明は上記のような課題を解消するためになさ、れ
たもので、TPTの特性が最大限発揮でき、これに〜よ
って高画質のアクティブマトリックス型液晶表示装置と
その駆動方法を得ることを目的とする。
This invention was made in order to solve the above-mentioned problems, and it is hoped that the characteristics of TPT can be maximized, thereby providing a high-quality active matrix liquid crystal display device and its driving method. purpose.

〔課題を解決するための手段〕 この発明に係るアクティブマトリックス型液晶表示装置
は、トランジスタアレイ基板はゲート線と平行に配置さ
れた複数のソース線を備え、対向基板はゲート線に対し
て直角方向にストライプ状に配列された対向電極を備え
たものである。
[Means for Solving the Problems] In an active matrix liquid crystal display device according to the present invention, the transistor array substrate has a plurality of source lines arranged in parallel to the gate line, and the counter substrate has a plurality of source lines arranged in a direction perpendicular to the gate line. It is equipped with counter electrodes arranged in stripes.

また、この発明によるアクティブマトリックス型液晶表
示装置の駆動方法は、ソース線には総て共通の直流電圧
を印加し、表示電圧は対向電極より入力するものである
Further, in the method for driving an active matrix liquid crystal display device according to the present invention, a common DC voltage is applied to all the source lines, and the display voltage is inputted from the counter electrode.

〔作 用〕[For production]

この発明におけるアクティブマトリックス型液晶表示装
置は、ソース電圧を固定し、常に一定のVgson、V
gsoffにしたことによりTPTを常に一定の動作点
で使用でき、例えばTPTの特性を第9図のようにVg
sof f点を0点からD点ヘシフトしたもめである。
The active matrix liquid crystal display device according to the present invention fixes the source voltage and always maintains constant Vgson and Vgson.
By setting gsoff, the TPT can always be used at a constant operating point. For example, the TPT characteristics can be changed to Vg as shown in Figure 9.
sof This is a dispute in which the f point was shifted from the 0 point to the D point.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図は本発明のアクティブマトリックス型液晶表示装置を
駆動する回路図、第2図はその駆動波形を示す。第1図
において、10はコモン電圧に接続されたソース電極、
11は列毎に共通に接続されたゲート電極、12はドレ
イン電極、13はTPT、14は液晶、15は行毎に共
通に接続され表示信号が入力される対向電極である。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram for driving the active matrix type liquid crystal display device of the present invention, and FIG. 2 shows its driving waveform. In FIG. 1, 10 is a source electrode connected to a common voltage;
Reference numeral 11 designates a gate electrode commonly connected for each column, 12 a drain electrode, 13 a TPT, 14 a liquid crystal, and 15 a counter electrode commonly connected for each row to which a display signal is input.

次に動作について説明する。Next, the operation will be explained.

ソース電極10にコモン電圧Vcomを印加しておき、
対向電極15から表示信号電圧V2、ゲート電極11か
らゲート電圧■1を印加すると、TFT4は導通(ON
)状態となり、ソース電極10から’l’FT4のON
抵(Ron)を通して液晶14に充電が行われる。次に
ゲート電極11のゲート電圧を零にするとTFT4は遮
断(OFF)状態となり、液晶14の容量(C1c) 
 14に充電されている電荷は、TFT4の遮断抵抗(
Roff)及び液晶の抵抗(Rlc)を通して放電をす
る。次のフレームで対向電極15から表示信号電圧v1
、ゲート電極11から圧v1を印ゲート電加すると、T
FT4は再び導通(ON)状態となり、対向電極15か
らTFT4のON抵抗(Ron)を通して液晶14は放
電され液晶層14にはVlの電圧が印加される。液晶層
14には以下同様の充放電が繰り返される。一方ゲート
電圧が零の間は対向電極15の表示信号電圧が変化して
も遮断抵抗(Roff)によって充放電が阻止される為
、表示の影響は受けない。
A common voltage Vcom is applied to the source electrode 10,
When the display signal voltage V2 is applied from the counter electrode 15 and the gate voltage ■1 is applied from the gate electrode 11, the TFT 4 becomes conductive (ON).
) state, and the 'l' FT4 is turned on from the source electrode 10.
The liquid crystal 14 is charged through a resistor (Ron). Next, when the gate voltage of the gate electrode 11 is reduced to zero, the TFT 4 enters the cut-off (OFF) state, and the capacitance (C1c) of the liquid crystal 14 decreases.
The electric charge charged in 14 is transferred to the cutoff resistance (
Roff) and the liquid crystal resistor (Rlc). Display signal voltage v1 from the counter electrode 15 in the next frame
, when a voltage v1 is applied to the gate electrode 11, T
The FT 4 becomes conductive (ON) again, the liquid crystal 14 is discharged from the counter electrode 15 through the ON resistance (Ron) of the TFT 4, and a voltage of Vl is applied to the liquid crystal layer 14. The same charging and discharging process is repeated for the liquid crystal layer 14 thereafter. On the other hand, while the gate voltage is zero, even if the display signal voltage of the counter electrode 15 changes, charging and discharging are blocked by the cutoff resistor (Roff), so the display is not affected.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明によれば、ゲート線と平行
に配置された複数のソース線を備えたトランジスタアレ
イ基板からなり、ゲート線に対して直角方向にストライ
プ状に配列された対向電極を備えた対向基板から構成し
たので、 (1)  表示電圧入力部をシンプルな構造の対向基板
としたためインピーダンスを低下させるファクターが少
なく、高画質、高歩留りが実現される。
As explained above, according to the present invention, the transistor array substrate includes a transistor array substrate having a plurality of source lines arranged in parallel with a gate line, and has counter electrodes arranged in stripes in a direction perpendicular to the gate line. (1) Since the display voltage input section is a simple-structured counter substrate, there are few factors that reduce impedance, achieving high image quality and high yield.

(2)  ソース電圧を固定したのでTPTの特性をフ
ルに使う事により高い0N10FF比と良好な画質を得
る事ができる。
(2) Since the source voltage is fixed, it is possible to obtain a high 0N10FF ratio and good image quality by fully utilizing the TPT characteristics.

(3)  言い換えればゲート電圧を下げる事ができる
と言うことで、ゲート電圧のCgdの影響も少なく、か
つ回路の低電圧設計にも寄与する。
(3) In other words, the gate voltage can be lowered, which reduces the influence of Cgd on the gate voltage and contributes to low voltage design of the circuit.

(4)  ゲート配線とソース配線が交差しない構造と
することが出来るため、配線部分のクロス部の短絡が無
くなり、歩留りが向上する。
(4) Since it is possible to create a structure in which the gate wiring and the source wiring do not intersect, there is no short circuit at the crossing part of the wiring part, and the yield is improved.

(5)  動作範囲が固定されているため、それに合わ
せた特性のTPTを製作すれば良く、品質向上、歩留り
向上につながる。
(5) Since the operating range is fixed, it is sufficient to manufacture a TPT with characteristics that match the operating range, leading to improved quality and yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例によるアクティブマトリッ
クス型液晶表示装置を駆動する回路図、第2図はゲート
電圧、対向電極電圧、ドレイン電圧の各駆動波形図、第
3図は従来のアクティブマトリックス型液晶表示装置の
駆動回路図、第4図は第3図の駆動回路図のゲート電圧
、ソース電圧、ドレイン電圧の各波形図、第5図はゲー
ト電圧、ソース電圧、対向電極電圧の波形図、第6図は
Id−Vg特性図、第7図は一画素の等価回路図、第8
図はゲート電圧とドレイン電圧の部分チャート図、第9
図はTPTの特性図である。 10・・・ソース電極、11・・・ゲート電極、12・
・・ドレイン電極、13・・・TFT、14・・・液晶
、15・・・対向電極。 なお、図中同一符号は同−又は相当部分を示す。
FIG. 1 is a circuit diagram for driving an active matrix type liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a drive waveform diagram of gate voltage, counter electrode voltage, and drain voltage, and FIG. 3 is a diagram of a conventional active matrix liquid crystal display device. Figure 4 is a waveform diagram of the gate voltage, source voltage, and drain voltage of the drive circuit diagram of Figure 3, and Figure 5 is a waveform diagram of the gate voltage, source voltage, and counter electrode voltage. , Fig. 6 is an Id-Vg characteristic diagram, Fig. 7 is an equivalent circuit diagram of one pixel, and Fig. 8 is an Id-Vg characteristic diagram.
The figure is a partial chart of gate voltage and drain voltage, No. 9.
The figure is a characteristic diagram of TPT. 10... Source electrode, 11... Gate electrode, 12.
...Drain electrode, 13...TFT, 14...Liquid crystal, 15...Counter electrode. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)複数本のゲート線とソース線およびゲート線、ソ
ース線に接続された複数の電界効果トランジスタを備え
たトランジスタアレイ基板と、導電性薄膜電極を備える
対向基板と、この対向基板の電極と上記トランジスタア
レイ基板間に挟持された液晶材とからなるアクティブマ
トリックス型液晶表示装置において、上記トランジスタ
アレイ基板はゲート線と平行に配置された複数のソース
線を備え、対向基板はゲート線に対して直角方向にスト
ライプ状に配列された対向電極を備えたことを特徴とす
るアクティブマトリックス型液晶表示装置。
(1) A transistor array substrate including a plurality of gate lines, a source line, a plurality of field effect transistors connected to the gate line and the source line, a counter substrate including a conductive thin film electrode, and an electrode of the counter substrate. In an active matrix type liquid crystal display device comprising a liquid crystal material sandwiched between the transistor array substrates, the transistor array substrate has a plurality of source lines arranged parallel to the gate line, and the counter substrate has a plurality of source lines arranged parallel to the gate line. An active matrix liquid crystal display device characterized by having counter electrodes arranged in stripes in the right angle direction.
(2)複数本のゲート線とソース線およびゲート線、ソ
ース線に接続された複数の電界効果トランジスタを備え
たトランジスタアレイ基板と、導電性薄膜電極を備える
対向基板と、この対向基板の電極と上記トランジスタア
レイ基板間に挟持された液晶材とからなるアクティブマ
トリックス型液晶表示装置において、ソース線には総て
共通の直流電圧を印加し、表示電圧は対向電極より入力
することを特徴とするアクティブマトリックス型液晶表
示装置の駆動方法。
(2) a transistor array substrate including a plurality of gate lines, a source line, a plurality of field effect transistors connected to the gate line and the source line; a counter substrate including a conductive thin film electrode; and an electrode of the counter substrate. In an active matrix type liquid crystal display device comprising a liquid crystal material sandwiched between the transistor array substrates, a common DC voltage is applied to all the source lines, and the display voltage is input from the counter electrode. A method for driving a matrix type liquid crystal display device.
JP63120931A 1988-05-17 1988-05-17 Active matrix type liquid crystal display device and its driving method Pending JPH01289918A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63120931A JPH01289918A (en) 1988-05-17 1988-05-17 Active matrix type liquid crystal display device and its driving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63120931A JPH01289918A (en) 1988-05-17 1988-05-17 Active matrix type liquid crystal display device and its driving method

Publications (1)

Publication Number Publication Date
JPH01289918A true JPH01289918A (en) 1989-11-21

Family

ID=14798517

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH01289918A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04214594A (en) * 1990-12-13 1992-08-05 Oki Electric Ind Co Ltd Liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04214594A (en) * 1990-12-13 1992-08-05 Oki Electric Ind Co Ltd Liquid crystal display device

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