JPH01288969A - Layout verifying method - Google Patents

Abstract

PURPOSE:To suppress occurrence of false errors so as to output real errors only by verifying that layout designing results are correctly realized in logic against logical designing results. CONSTITUTION:Transistor connecting information 3 extracted from layout designing results 1 is converted into cell connecting information 6 by the logical recognition of a rule base. The connecting information 6 and logical designing results 7 are respectively expressed by logical expressions using circuit outputs and register inputs as output variables and circuit inputs and register outputs as input variables. The designing results 1 and 7 are respectively converted into logical expressions expressing them and collation between both results is performed by a collating section 8 by verifying the identity between corresponding logical expressions. Therefore, even when the layout designing results give a circuit configuration which is different from the logical designing results, the layout designing results are not outputted as errors if they are logically equal. Thus only real errors having different logic are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a layout verification method for semiconductor integrated circuit devices.

BACKGROUND ART Conventional layout verification methods include the following.

(1) A method in which circuit elements such as transistors are extracted from a layout pattern and connections are verified against reference data.

(2) A method of verifying by simulating the circuit extracted from the layout.

(3) Restore the logic diagram by recognizing the registered cells from the circuit extracted from the layout,
How to visually verify.

(1) is widely used and put into practical use when reference data is available. However, this technique requires that the layout results closely match the reference results;
It tends to generate many spurious errors.

(2) and (3) are also effective when there is no reference data.

However, in ■, the computer load of circuit simulation is large, and it is not suitable for large-scale circuits. The problem with method (3) is that it ultimately relies on human visual inspection of the logic diagram, which cannot eliminate the possibility of errors and is not effective for large-scale circuits.

A typical conventional layout verification method, which uses connection verification at the transistor level, will be described below.

FIG. 8 shows a conceptual diagram of this method.

In step 21, circuit elements such as transistors are extracted from the layout design result 25 and converted into transistor-level connection information 26.

On the other hand, in step 22, each cell of the logic design result 27 is developed into a circuit, thereby converting it into transistor level connection information 28.

In step 23, the two pieces of connection information 27 and 28 obtained as described above are checked for connection, and a check result 29 is output.

By using the method described above, it is possible to know whether the layout design result 25 is a correct realization of the original logical design result 27 by looking at the output comparison result 29.

Problems to be Solved by the Invention However, problems in layout verification that are difficult to solve with conventional layout verification methods based on transistor-level connection verification will be described below.

(1) Circuit changes during layout design Layout design is not necessarily performed faithfully to logical design data (i.e., circuit configuration can be flexibly modified according to the situation, such as saving area). As a result, the layout pattern may have the same functionality (and therefore be correctly designed) but differ from the reference data in circuit terms, or two identical cells contained in the reference data may appear in the layout pattern. Each one corresponds to a different circuit.

■ Replacement of gate inputs It is common knowledge for designers that gate inputs are equivalent and interchangeable. In layout design, gate inputs are exchanged freely depending on the situation.

(3) Addition of redundant transistors For reasons such as fan-out adjustment, multiple transistors with the same function are often laid out.

In conventional layout verification systems, some of these inconsistencies between layout patterns and reference data have been addressed through various exceptional measures.
Basically, pseudo errors are output together with true errors that the system should detect, and it is difficult to distinguish between them.

In order to avoid such problems, it is possible to modify the logic design results based on the layout pattern, but this would require an increase in design man-hours, including re-verification of the modified logic design.

The above-mentioned problems are fundamental shortcomings of the conventional layout verification method based on transistor connection verification.

In view of this, it is an object of the present invention to propose a layout verification method that suppresses the occurrence of pseudo errors as described above and outputs only true errors.

Means for Solving the Problems The present invention provides a layout verification method for verifying whether a layout design result based on a logic design result correctly realizes the original logic design. a step of deriving a logical formula expressing the logic realized by the logical design result, a step of deriving a logical formula expressing the logic realized by the logical design result, and a step of determining whether the two logical formulas are logically equivalent. A layout verification method comprising: verifying that the layout design result is logically correctly realized with respect to the logical design result.

Operation In the present invention, both the layout design result and the logical design result are converted into logical formulas expressing them, and the comparison between the two is performed by proving the identity between the corresponding logical formulas.

Therefore, even if the layout design result has a circuit configuration that differs from the logic design result due to various circumstances, if they are logically equal, it will not be output as an error, but only true errors that are logically different will be output. be able to.

Embodiment FIG. 1 shows a system conceptual diagram of an embodiment of the layout verification method according to the present invention.

In FIG. 1, 1 is a layout design result composed of graphic data, 2 is a circuit extraction section, 3 is extracted transistor connection information, 4 is a rule-based logic recognition section, and 5 is a circuit extraction section.
is a knowledge source containing logical recognition rules, 6 is connection information of recognized cells, 7 is a logic design result which is reference data, 8 is a verification unit based on proof of identity of logical formulas, 9 is cell connection This is a logic diagram creation unit that creates a logic diagram from information.

A detailed explanation of the processing will be given below in order.

(1) Logic Recognition The transistor connection information 3 extracted from the layout design result 1 is converted into cell connection information 6 by rule-based logic recognition. By changing the rules stored in the knowledge source 5, the user can
It can support layout designs using various technologies such as CL, and various circuit styles such as static and dynamic.

By using a rule-based method in this embodiment, more flexible logical recognition is possible than with conventional cell recognition methods.

An example of the rules is shown in FIG. This rule is
If the series connection of MO8 and the parallel connection of NMO3 are connected as shown in the figure, and the lists L1 and L2, which are sets of gates, have the same elements regardless of the order, then
"replace it with the corresponding NOR gate."

What should be noted here is that this one rule corresponds to any permutation of the inputs of a NOR gate with any number of inputs. As a result, this method
This solves the problem regarding gate input replacement.

FIG. 3 shows the processing flow of the logic recognition section.

1. Removal of redundant transistors Prior to recognition, if there is a redundant transistor as shown in FIG. 4, it is removed from the working memory.

2. Recognizing parallel and series connections First, recognize parallel and series connections of transistors. As shown in FIG. 5, transistors of the same polarity connected in series are converted into a virtual circuit element meaning a series connection of transistors. The gate of each transistor is
are combined into one list. Here, each transistor may be connected in parallel or in series instead.

3. Removal of redundant parallel/series connections If there are redundant parallel/series connections as shown in Figure 6, they are removed from the working memory. Here, even if the order of the transistors is changed, they are considered to be the same.

4. Gate recognition Next, if transistors or series connections and parallel connections are connected complementary, connect them to an inverter or N
Replace with OR and NAND gates. Figure 2 shows an example of NOR, but since any transistors in this can be connected in series or in parallel, this rule applies not only to simple NOR (and AND-NOR type complex It is also possible to recognize gates.

5. Removal of redundant gates Also at the gate level, logical redundancies such as serial inverters are removed.

6. Cell Recognition Gates Recognized circuits are subsequently exchanged into the cells configured by those gates. Here too, recognition proceeds hierarchically. The main purpose of cell recognition is to recognize registers in the circuit for subsequent logic verification.

Q) Proof of identity of logical formula Cell connection information 6 converted from layout design result 1
and the logic design result 7, which is reference data, are each expressed by a logical formula in which the circuit output and register input are output variables, and the circuit input and register output are input variables.

Two circuits expressed by logical formulas are verified to be logically equivalent by proof of identity based on conversion to a binary decision tree after correspondence is established between inputs and outputs. Therefore, even if there is a circuit change in the layout design, if the change is logically equivalent, this method will not cause an error, and only true errors that change the logic can be output. .

Conversion to a binary decision tree is performed based on Shannon expansion of a logical formula.

What is S hannon expansion? One input variable X of logical formula F
Let Fl and FO be the logical expressions when fixed to 1 or O, respectively, and F can be expanded as follows using Fl and F2.

By recursively applying the 3hannon expansion until the logical expression becomes 1 or O, a corresponding binary decision tree can be obtained.

FIG. 7 shows an example of a logical formula and a corresponding binary decision tree. Each vertex of the binary decision tree corresponds to a logical formula, and the input variables that are the basis of expansion and the 2
It has nodes to vertices corresponding to two logical expressions. The top vertex corresponds to the original logical formula.

It is known that a binary decision tree created in this way is a canonical representation of a logical function, and it is possible to determine the identity of two logics by determining isomorphism of the graph.

In this example, a method based on conversion to a binary decision tree is used to prove the identity of a logical formula, but as another method, for example, a method based on expansion to a sum-of-products standard form is used. It is also possible.

(3) Logic diagram creation A logic diagram can be automatically created based on the results of logic recognition, and the designer can perform visual verification based on the results. Among the circuits that are laid out manually, there are many, such as memories, that are laid out directly without going through logic design. Visual verification is effective in the absence of such reference data.

As described in detail, according to the present invention, only true errors in which the layout design result is logically different from the logic design result can be output, and verification in the layout design of semiconductor integrated circuit devices can be performed. In addition to improving efficiency, it also increases the degree of freedom in layout design, leading to increased efficiency.

In addition, by realizing the logic recognition part using a rule-based method, designers can easily apply this method to various technologies and circuit styles by simply changing the rules. The effect is significant.

[Brief explanation of the drawing]

Fig. 1 is a system conceptual diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the rules of the logic recognition unit in the same embodiment, Fig. 3 is a processing flow diagram of the logic recognition unit, and Fig. 4 FIG. 5 is an explanatory diagram of the redundant transistor removal process of the logic recognition unit, and FIG. 5 is an explanatory diagram of the parallel/series connection recognition process of the logic recognition unit.
FIG. 6 is an explanatory diagram of the process of removing redundant parallel/serial connections in the logic recognition unit, and FIG. 7 is an explanatory diagram of the conversion from a logical formula to a binary decision tree in the logical formula matching unit of the same embodiment. , FIG. 8 is a conceptual diagram of a conventional layout verification method based on circuit connection verification. 1...Layout design result, 2...Circuit extraction section 3...Transistor connection information, 4...
...Logic recognition unit 5...Knowledge source, 6...
...Cell connection information, 7...Logic design results, 8.
...Logical formula matching section, 9...Logic diagram creation section. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 8

Claims (2)

[Claims] (1) In a layout verification method that verifies whether the result of layout design based on the logical design result correctly realizes the original logical design, a logical expression expressing the logic realized from the layout design result a step of deriving a logical formula expressing the logic realized by the logical design result from the logical design result, and a step of determining whether the two logical formulas are logically equivalent, A layout verification method, comprising verifying that the logical design result is logically correctly realized. (2) The layout verification method according to claim 1, wherein in the step of deriving a logical formula from the layout design result, a method of recognizing logic based on rules is used.