JPH01286517A - Drive circuit - Google Patents

Abstract

PURPOSE:To avoid ringing and to hardly cause malfunction by using a CMOS transistor(TR) of common source connection. CONSTITUTION:A drive circuit 1 of a logic circuit consists of MOS n-channel TR Qn1 and a p-channel TR Qp1 whose common gate receives an input signal Vi supplied from an inverter I, whose common source S outputs an output signal vs and whose drains Dn, Dp are respectively connected to power terminals TSS, TDD, and the output signal vs controls a capacitive load. Since the common electrode of the CMOS TR consists of the source S and the other electrodes consist of the drains Dn, Dp in this way, a drive circuit is obtained, where malfunction due to ringing hardly takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit, and more particularly to a drive circuit that controls a capacitive load.

[Conventional technology]

2. Description of the Related Art As semiconductor circuits have recently become faster and have lower voltage power supplies, the reliability of logic circuit operation has become increasingly important.

Particularly, during high-speed switching of 10 ns or less, parasitic vibration (hereinafter referred to as ringing) due to parasitic inductance between circuits or internal wiring of the IC or parasitic capacitance between the gate and the power supply may occur, resulting in circuit malfunction.

FIG. 5 is a circuit diagram of an example of a conventional drive circuit.

The drive circuit 11 inputs an input signal Vl to a common gate G, and sources S and So are connected to power supply terminals T'ss and T, respectively.
It has a p-channel transistor Qpt and an n-channel transistor Qpt connected to DD, whose common drain D supplies an output signal VD.

A common train D has a common gate g and both sources SP+SO.
A CMO with parasitic gate capacitances CI and C between
It is connected to the common gate g of the three circuits 2 via wiring to form a logic circuit.

When the switching speed of the input signal Vl is high-speed switching of 10 ns or less, the parasitic inductance of the wiring between the common drain D and the common drain 58 cannot be ignored and is therefore shown as a dotted line.

FIG. 6 is a voltage/current waveform diagram of each part for explaining the operation of the circuit of FIG. 5.

The input signal v1 changes from Ov to the voltage V of the DC power supply E at time t1.
When E rises, the p-channel transistor QQI of the MOSFET turns off, and the n-channel transistor Q
Since t is in the on state, the sum it of the discharging current from the parasitic gate capacitance Cn of the n-channel transistor Qfi2 of the CMOS circuit 2 and the charging current to the gate capacitance C of the p-channel transistor Q112 is connected to the common drain D and the common gate capacitance C. 58 to the transistor Qfi+ through the parasitic inductance L of the wiring between them.
On-resistance R8 of ゎ1, gate capacitance C of CMOS circuit 2,
Ringing occurs when the sum C of l and C and the inductance L satisfy equation (1).

R,<2 ・Aff ・(1) This ringing similarly occurs after the end time t2 of the input signal v1, and if the common gate voltage v, is lower than the logic threshold voltage of the CMOS circuit 2, it will not work properly. There is no problem.

[Problem to be solved by the invention]

The above-described conventional drive circuit has the disadvantage that ringing tends to occur in the output voltage due to the parasitic reactance of the circuit, resulting in malfunction when the peak voltage exceeds the logic threshold voltage of the next-stage load IC.

For example, the voltage VE of the DC power supply E in FIG. 5 is 5V.

If the on-resistance R8 of the transistor Q+xt is 10 Ω, the load capacitance C is 50 pF, and the inductance L between D and g is 200 nH with a wiring length of 20 cm, the ringing of the voltage v of the common gate g is calculated using equation (1). The lowest peak value Vp of the voltage is -4V, the maximum peak value VQ is +3V, and the logic threshold voltage of the CMOS circuit 2 is 2.5V.
It was malfunctioning beyond this point.

An object of the present invention is to provide a drive circuit that is unlikely to malfunction due to ringing.

[Means to solve the problem]

The drive circuit of the present invention has a 0MO3) transistor whose common gate receives an input voltage, whose common electrode outputs an output signal, and whose other electrodes are connected to respective power supply terminals, the output signal being applied to a capacitive load. In the drive circuit that controls
The common electrode of the CMOS transistor is a source, and the other electrode is a drain.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIGS. 2 and 3 are voltage and current waveform diagrams of various parts and voltages of p-channel transistors to explain the operation of the circuit of FIG. 1. It is a current characteristic diagram.

In the drive circuit 1 of the logic circuit, the common gate G receives the input signal vI.
In response, the common source S outputs an output signal V5, and the drains Dfi and T are connected to the respective power supply terminals 'I'ss and T.
MOS type n-channel transistor Q n and p-channel transistor Qp+ connected to I), ).

The drive circuit 1 and the inverter I supplying the input signal Vl are the drive circuit 1. of FIG. It is the same as the conventional logic circuit except that it is replaced with .

Next, the operation of the circuit will be explained.

First, the same input voltage Vl as before is applied to the input terminal T'+, and the input voltage v of an inverted signal is applied to the common gate G by the inverter I.

Time point 1. When the voltage of the input voltage Vl drops from V= to Ov, the voltage of the common gate G of the n-channel transistor Ql, l and the p-channel transistor Qp1 both becomes Ov with respect to the potential of the common source S, so that the voltage of the transistor Qゎ1
is turned off, and transistor Qp1 is turned on.

Therefore, the discharging current from the gate capacitance C and the charging current to the gate capacitance Cp pass through the inductance L to a current of 1L.
and flows into the transistor Q'pt.

As shown in FIG. 3, the transistor Qp1 has a characteristic that as the voltage of the output signal Vs of the common source S decreases, the source-gate voltage V GSP decreases.

Therefore, equivalently, the on-resistance R2 of the transistor Qps increases inversely to vosp.

As a result, the on-resistance Rp becomes larger than 2.~βL, Σstone-, and it no longer satisfies equation (1), which is the vibration condition for the LCR series circuit, resulting in a waveform that does not cause ringing, as shown in Figure 2. .

Also, the time t2 when the input signal voltage vH changes from 0 to VE
Also, as the voltage of the output signal v5 increases, the gate-source voltage V of the n-channel transistor Ql11 increases.
Since GIN becomes smaller, the transistor Q n
The on-resistance R of 1 increases, and ringing no longer occurs.

Note that in this embodiment, the transistors Qp1 and Q fil
Although a depletion type MOSFET was used as the method, an enhancement type or insulated gate type MOSFET is also used.

Similar effects can be obtained with other types of transistors, regardless of the junction type.

FIG. 4 is a schematic cross-sectional view of a semiconductor chip according to a second embodiment of the present invention.

The resistance terminal with the positive electrode of the DC power supply E is Too + the connection terminal with the negative electrode is Tss, and the insulating P+ isolation layer 4 is T' to isolate it from other areas in the integrated circuit such as the inverter. ss, and a CMO8 structure corresponding to the drive circuit 1 is configured within the n-type substrate 3 within the separation layer 4.

Here, when a P-type substrate is used instead of the n-type substrate 3, an n+ separation layer is used instead of the P+ separation layer, and T's
The same effect can be obtained by connecting to the TDD end instead of the S end.

〔Effect of the invention〕

As explained above, the present invention provides common source connection CMO
The use of an S transistor has the effect of eliminating ringing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIGS. 2 and 3 are voltage and current waveform diagrams of various parts and voltages of p-channel transistors to explain the operation of the circuit of FIG. 1. A current characteristic diagram, FIG. 4 is a cross-sectional view of a semiconductor chip according to a second embodiment of the present invention, FIG. 5 is a circuit diagram of an example of a conventional drive circuit, and FIG. 6 explains the operation of the circuit in FIG. 5. FIG. 4 is a voltage/current waveform diagram of each part for the 1...Drive circuit, 2...CMO3 circuit, 3...n
type substrate, 4...separation layer, D,,D,...drain,
G... common gate, Qllll... n channel transistor, Qpt... p channel transistor, S...
-Common source, T1...input terminal, Vl...input voltage, ■,...source voltage.

Claims (1)

[Claims] In the drive circuit, the drive circuit has a CMOS transistor whose common gate receives an input voltage, whose common electrode outputs an output signal, and whose respective other electrodes are connected to respective power supply terminals, and whose output signal controls a capacitive load. A drive circuit characterized in that the common electrode of a CMOS transistor is a source and the other electrode is a drain.