JPH0128438B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a function converter that converts an analog input signal as a converted function input into a desired function signal.

For example, the output signal of a differential pressure oscillator for measuring flow rate connected to a process control device is an analog signal proportional to the square of the flow rate. must be converted to and used.

Therefore, as a means to perform such a square root calculation with a simple circuit, the square root calculation value for any instantaneous value of an analog input signal is stored in advance in a read-only memory, and the analog input signal is digitally transferred to the read-only memory. There is a system in which a signal converted into a signal is given as an address signal, thereby obtaining a square root value for an arbitrary instantaneous value of an analog input signal. For example, there is "Input Characteristic Correction Circuit for Process Control Device" described in Japanese Patent Application Laid-Open No. 11848/1984. In addition, as a similar device, as shown in the block diagram of Fig. 1, an analog-to-digital converter (hereinafter referred to as
A read-only memory (hereinafter referred to as ROM) with a K-bit (n = 2K) output, which has a smaller number of output bits than the output bit number n of the ADC (ADC), is installed in parallel, and the converted value (for example, the square root value) is stored in the upper There is a conversion value that is divided into digits and lower digits and has a total of 2K bits.

Here, the operation of the function converter shown in FIG. 1 will be described as a representative example.

First, ADC 1 is the timing signal generation circuit 2
When an AD conversion start signal S _A is given from , the analog input signal as the input of the function to be converted is converted into an n-bit digital signal. When this conversion operation is completed, a conversion end signal S _B is output.
The n-bit digital signal output from ADC-1 is commonly supplied to the address inputs of ROM-3 and ROM-4.

The timing signal generation circuit 2 generates a conversion end signal S _B
is given, the read command signal Sc is supplied to ROM-3 and ROM-4, and these
Among the converted values stored in advance in ROM.3 and ROM.4, the converted value corresponding to the value of the n-bit digital signal input as the address input signal is output. In this case, ROM.3 stores a K-bit digital signal representing the upper digit of the converted value, and ROM.4 stores a K-bit digital signal representing the lower digit. Therefore, in this function converter, 2K bits (i.e.,
A converted value of n-bit) configuration is obtained.

However, in a function converter with such a configuration, although the function values stored in ROM-3 and ROM-4 are different,
If the number of output bits of ROM-3 and ROM-4 is the same, their appearance is also exactly the same. For this reason, there is a risk of attaching it to the wrong position when attaching it to the printed circuit board, and there is a drawback that it is necessary to confirm each time whether or not it is attached correctly. Additionally, since multiple ROMs are used, there are drawbacks such as high power consumption.

The present invention has been made to solve these drawbacks, and its purpose is to provide a function converter that does not require the above-mentioned confirmation work and consumes less power.

To this end, the present invention divides a single read-only memory into a plurality of memory blocks corresponding to the number of digits of the converted value, and sequentially selects each memory block to store each of the converted values stored in each memory block. The numerical values of the digits are sequentially read out in a time-division manner, and the read numerical values of each digit are then latched in a latch circuit digit by digit.
The structure is such that the outputs of the latch circuits for each digit are output as converted values at the same timing.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram showing one embodiment of a function converter according to the present invention. In the figure, 10 is an ADC that converts an analog input signal into an n-bit digital signal when the signal _S1 is applied, and 20 is an AD
A timing signal generation circuit 30 outputs a conversion start signal S ₁ , a memory block instruction signal S ₂ , and latch instruction signals S ₃ and S ₄ . Reference numeral 30 indicates two memory blocks MB 1 and MB ₁ corresponding to the upper and lower digits of the conversion value. The lower digit of the converted value is stored as an m-bit (m<n) digital signal in the memory address corresponding to the analog input signal of memory block MB ₂ , and the analog input signal of memory block MB ₂ is stored as an m-bit (m _< n) digital signal. This ROM is a ROM in which the upper digit of the converted value is stored as a K-bit (m+K=n) digital signal at the memory address corresponding to the signal.
The memory block instruction signal _S2 and the output digital signal of the ADC 10 are input as address inputs to the address input. 40 is a first latch circuit that latches the upper digit numerical signal (K-bit configuration) read from memory block MB ₂ in response to latch instruction signal S 3; 50 latches the numerical signal of the upper digit read out from memory block MB ₁ in response to latch instruction signal _{S 4} ; The lower digit numerical signal (m
a second latch circuit that latches the bit configuration), the output signal (K bits) of the first latch circuit;
Together with this, it is output as a converted value of K+m=n bits.

Next, the operation of the function converter configured in this way will be explained.

First, the timing signal generator 20 is configured as shown in FIG.
Based on the clock signal φ having a predetermined period shown in FIG _.
Outputs S ₂ , S ₃ , and S ₄ .

In this state, when an analog input signal is supplied to ADC 10, the instantaneous value of this analog input signal is at the period when AD conversion start signal S ₁ is generated.
It is converted into an n-bit digital signal by the ADC 10. This n-bit digital signal is
It is supplied as the address input of ROM・30, but
At this time, a memory block instruction signal _S2 is also supplied as another address input. Then, when the memory block instruction signal _S2 is "0", the memory block _MB1 is selected.

And further this selected memory block
In MB ₁ , a memory address corresponding to an n-bit digital signal supplied as an address input from ADC 10 is selected. At this storage address, a numerical signal of the lower digit of the converted value corresponding to the instantaneous value of the analog input signal at this time is stored in advance. Therefore, when the signal _S2 is "0", a numerical signal (m bits) of the lower digit of the converted value corresponding to the instantaneous value of the analog input signal is output from the ROM 30.
Next, when the memory block instruction signal _S2 becomes "1", the memory block _MB2 is selected. and,
Furthermore, within this memory block MB ₂ , the ADC
n supplied as address input from 10
A memory address corresponding to the bit digital signal is selected. At this storage address, a numerical signal of the upper digit of the converted value corresponding to the instantaneous value of the analog input signal at this time is stored in advance. For this reason, the signal S ₂
When is "1", the numeric signal (m bits) of the upper digit of the converted value corresponding to the instantaneous value of the analog input signal is output from the ROM 30. In this case, the signal S ₂ repeats "1" and "0" every time the signal S ₁ is output, and the time width of each "1" and "0" of the signal S ₂ is converted by the ADC 10. It is set sufficiently longer than the required operation time. Therefore, since signal S ₁ is generated once from ROM 30, the converted value corresponding to the instantaneous value of the analog input signal at the timing of generation of signal S ₁ is divided into upper and lower digits and serially transmitted. Output.

The numerical signals of the upper digits and lower digits of this serially output converted value are the numerical signals of the upper digits _.
The numerical signal of the lower digit is latched in the first latch circuit 40 by the signal _S4 .
Latched to 0. These two latch circuits 4
The numeric signals latched at 0,50 are (K+
m) Output as a converted value of bit configuration. In this case, the generation timings of the latch instruction signals S ₃ and S ₄ are shifted by one cycle of the clock pulse φ, so the numerical signals of the upper and lower digits are aligned during the period indicated by the symbol X in Figure 2. Therefore, on the side that uses the converted value, the converted value is captured and used during this period of X.

Therefore, since the function converter configured in this way has only one ROM, no errors occur when attaching it to the printed circuit board, and there is no need to check the attachment. At the same time, power consumption is reduced, and the configuration can be made lighter and more compact. moreover,
Since the converted value is divided into upper and lower digits and output serially, even if the number of output bits of the ROM is K bits, it is possible to freely obtain converted values of (K+1) bits to 2K bits. I can do it. This is very effective when matching the number n of output bits of the ADC 10 with the number of bits of the converted value.

Note that although the above embodiment deals with the case where the converted value is divided into high-order digits and low-order digits, it can be similarly implemented even when the converted value is further divided into a plurality of digits. Further, although the number of output bits of the ADC and the number of bits of the converted value are assumed to be the same, it goes without saying that they do not have to be the same number of bits.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional function converter, Fig. 2 is a block diagram showing an embodiment of a function converter according to the present invention, and Fig. 3 is a block diagram showing an example of a function converter according to the present invention. This is a time chart showing the timing of various signals. 10...Analog-digital converter, 20...
...Timing signal generation circuit, 30... Read-only memory, 40... First latch circuit, 50...
Second latch circuit.

Claims (1)

[Claims] 1 An analog-to-digital converter that converts an analog input signal as an input to a converted function into a digital signal, and a plurality of memory blocks corresponding to the number of digits of the converted value to be output, and each memory block converts the analog input signal into a digital signal. Each digit of the converted value corresponding to the analog input signal is stored as a multi-bit digital signal in the memory address corresponding to the analog input signal, and the analog/digital converter is used as a common address signal for each of the memory blocks. a single memory into which the output signal of is input; a latch circuit provided corresponding to each digit of the converted value and latching the numerical signal of each digit of the converted value read from each memory block of the memory; a timing signal generation circuit that generates an address signal for sequentially specifying each memory block of the memory in a time-division manner and a latch signal for causing the latch circuit to latch the numerical signal of each digit read from each memory block; Equipped with a function converter.