JPH01283836A - Manufacture of compound semiconductor wafer - Google Patents

Manufacture of compound semiconductor wafer

Info

Publication number
JPH01283836A
JPH01283836A JP11315488A JP11315488A JPH01283836A JP H01283836 A JPH01283836 A JP H01283836A JP 11315488 A JP11315488 A JP 11315488A JP 11315488 A JP11315488 A JP 11315488A JP H01283836 A JPH01283836 A JP H01283836A
Authority
JP
Japan
Prior art keywords
wafer
compound semiconductor
wafers
shape
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11315488A
Other languages
Japanese (ja)
Inventor
Toshiya Toyoshima
豊島 敏也
Mineo Wajima
峰生 和島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP11315488A priority Critical patent/JPH01283836A/en
Publication of JPH01283836A publication Critical patent/JPH01283836A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable a round wafer to be obtained efficiently by removing faulty part such as projection, etc., without damaging the surface so as to process and form it into the round shape for single or many sheets at a time by machine grinding regardless of the shape of a semiconductor substrate. CONSTITUTION:SiO2 films are formed by vapor growth method (CVD method) on both sides of a wafer 1 so that the surface may not be damaged, and fifty sheets of these wafers are piled up with the positions of orientation flats 6 fixed and then adhered with thermosoftening adhesive into cylindrical shape. The periphery of this cylindrical wafer 5 is ground with a cylinder grinding device into the specific cylindrical shape, and further the orientation flat part is ground. After finish of grinding the thermosoftening adhesive is dissolved and removed using trichloroethylene, and further SiO2 film is dissolved and removed by hydrofluoric acid. Hereby, it can improve efficiency, economical efficiency, etc., exceptionally as compared with conventional processing method by manual operation.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、化合物半導体ウェハの製造方法、特に液相エ
ピタキシャル成長法により得られるウェハの加工法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing compound semiconductor wafers, and particularly to a method for processing wafers obtained by liquid phase epitaxial growth.

[従来の技術] 液相エピタキシャル成長方法は例えばガリウム・ヒ素(
GaAS)、ガリウム・アルミニウム・ヒ素(GaAj
lAs)及びガリウム・リン(GaP)等、m−v族化
合物半導体ウェハの成長方法として広く用いられている
が、この成長方法を用いて得られるウェハは一般に周辺
部に突起部等の欠陥が生じ易い。第3図及び第4図は例
えば(100)面を有する円形のGaAS基板にGaA
S層を50μm程度成長させた場合の状況を示すもので
、夫々平面図及び一部所面図を示ず。
[Prior art] The liquid phase epitaxial growth method uses, for example, gallium arsenide (
GaAS), gallium aluminum arsenic (GaAj
It is widely used as a growth method for m-v group compound semiconductor wafers such as lAs) and gallium phosphide (GaP), but wafers obtained using this growth method generally have defects such as protrusions on the periphery. easy. Figures 3 and 4 show, for example, a circular GaAS substrate with a (100) plane
This figure shows the situation when the S layer is grown to a thickness of about 50 μm, and a plan view and some partial views are not shown.

両図において1はエピタキシャル成長後のウェハ、2は
エピタキシャル層平坦部、3は突起部、4は基板を示す
が、これらの図からも明らかなように、ウェハ1の周辺
部、特に(010)、(010)、(001)、(00
j)方向には高さが100μm以上になる突起部を生ず
る場合がある。
In both figures, 1 shows the wafer after epitaxial growth, 2 shows the flat part of the epitaxial layer, 3 shows the protruding part, and 4 shows the substrate.As is clear from these figures, the peripheral part of the wafer 1, especially (010), (010), (001), (00
In the j) direction, protrusions with a height of 100 μm or more may be produced.

このような突起部は次のフォトリソグラフィー工程に種
々の障害を与えるもので、例えばレジストをスピンナー
て塗布する場合、突起部の近傍にレジストの不均一部が
集中し、又マスクアライナ−による露光詩にこの突起部
が露光機に接触してウェハを損傷させたり、又は露光不
能にさせる場合が生ずる。このため従来は液相エピタキ
シャル成長後にこれらの突起部を小形グラインダーやヤ
スリ等を用いて削り取る整形作業が行なわれている。
These protrusions cause various problems in the subsequent photolithography process. For example, when resist is applied using a spinner, non-uniform areas of the resist concentrate near the protrusions, and the exposure process using a mask aligner is difficult. In some cases, this protrusion comes into contact with the exposure machine and damages the wafer or makes exposure impossible. For this reason, conventionally, after liquid phase epitaxial growth, a shaping operation is performed in which these protrusions are shaved off using a small grinder, file, or the like.

−・般にウェハは搬送の自動化や小トレジスト作業等を
考慮すると角形よりは円形の方が作業が格段に容易とな
るので、加工方法が面倒でも円形に整形して使用される
ことが多い。
- Generally speaking, circular wafers are much easier to work with than rectangular wafers when automating transportation, small resist work, etc. are taken into account, so wafers are often shaped into circular shapes even if the processing method is cumbersome.

[発明が解決しようとする課題] 上述したように液相エピタキシャル成長が終γしたウェ
ハは突起部を削り取る作業が行われるが、手作業による
ため仕上り精度が低く、加工時に損傷し易い等、作業が
非能率的で経済性に劣る嫌いがあった。
[Problems to be Solved by the Invention] As mentioned above, the protrusions of the wafer that have undergone liquid phase epitaxial growth are scraped off. However, since this is done manually, the finishing accuracy is low, and the process is easily damaged, resulting in problems with the work. It was considered inefficient and uneconomical.

本発明の目的は、液相Jビタキシャル成長時にウェハの
円形加工が容易で作業能率、経済性に有利な化合物半導
体ウェハの製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing compound semiconductor wafers that facilitates circular processing of wafers during liquid phase J-bitaxial growth and is advantageous in terms of work efficiency and economy.

[11題を解決するための手段] 本発明は、液相エピタキシャル成長方法を用いて半導体
基板にエピタキシャル層を形成する化合物半導体ウェハ
の製造方法において、前記エピタキシャル層形成後のウ
ェハを前記半導体基機の形状に拘らず機械研削により単
独もしくは多数枚同時に表面を傷つけずに突起部等欠陥
部を除去して円形に加工整形することを特徴とし、円形
ウェハが効率よく得られるようにして目的の達成を計っ
たものである。
[Means for Solving Problem 11] The present invention provides a method for manufacturing a compound semiconductor wafer in which an epitaxial layer is formed on a semiconductor substrate using a liquid phase epitaxial growth method, in which the wafer after the epitaxial layer is formed on the semiconductor substrate. Regardless of the shape, it is characterized by mechanically grinding single or multiple wafers at the same time to remove protrusions and other defects without damaging the surface, and process and shape them into a circle, thereby achieving the objective by efficiently obtaining circular wafers. It was measured.

[作  用〕 本発明の化合物半導体ウェハの製造方法では液相エピタ
キシャル成長方法を用いて例えばGaAS等の■−■族
化合物半導体ウェハを製造する場合、ウェハの両面に例
えば二酸化ケイ素(Si02)膜を形成して損傷が生じ
ないようにし、多数枚ウェハを同時に処理する場合はこ
のウェハを川ね合せて熱軟化性接着剤で接着して円筒状
とし、これを必要な直径に研削して円筒形とした後オリ
1ンテーションフラット部を研削してその後接着剤及び
SiO2膜を溶解除去して円形ウェハとしている。又角
形ウェハを円形ウェハに加工する場合は面取装置により
外周部を研削して円形に加工するようにしであるので、
加工後のウェハには上記いずれの場合にも突起部その他
の欠陥が生ぜず、高品質のウェハが高能率で得られる。
[Function] In the compound semiconductor wafer manufacturing method of the present invention, when manufacturing a ■-■ group compound semiconductor wafer such as GaAS using a liquid phase epitaxial growth method, for example, a silicon dioxide (Si02) film is formed on both sides of the wafer. When processing multiple wafers at the same time, the wafers are glued together with heat-softening adhesive to form a cylindrical shape, which is then ground to the required diameter to form the cylindrical shape. After that, the orientation flat portion is ground, and then the adhesive and SiO2 film are dissolved and removed to form a circular wafer. Also, when processing a square wafer into a circular wafer, the outer periphery is ground using a chamfering device and processed into a circular shape.
In any of the above cases, the processed wafer does not have protrusions or other defects, and high-quality wafers can be obtained with high efficiency.

[実 施 例] 以下、本発明の実施例について説明する。[Example] Examples of the present invention will be described below.

実施例1:直径54履、厚さ0.355wのN型GaA
sウェハにデイツプ式液相エピタキシャル成長法により
シリコン(S i )をドープしてエピタキシャル成長
層を80μmの厚さに成長させた。
Example 1: N-type GaA with a diameter of 54 mm and a thickness of 0.355 W
An epitaxially grown layer was grown to a thickness of 80 μm by doping silicon (S i ) onto the S wafer by a dip-type liquid phase epitaxial growth method.

このウェハは、エピタキシャル層内にpn接合が形成さ
れ赤外発光ダイオードに使用される。
This wafer has a pn junction formed in the epitaxial layer and is used for an infrared light emitting diode.

第1図はこの実施例によるウェハを示すもので、第3図
と同様2が平坦部、3が突起部を示す。突起部3には通
常の成長により生ずる突起部の他にウェハとグラフフィ
ト成長容器との接触による異常成長も形成される。
FIG. 1 shows a wafer according to this embodiment, where 2 indicates a flat portion and 3 indicates a protruding portion, as in FIG. 3. In addition to the protrusions generated by normal growth, abnormal growth is also formed in the protrusion 3 due to contact between the wafer and the graphite growth container.

このようなウェハ1の両面に5i0211を気相成長法
(CVD法)により形成させて表面に損傷が生じないよ
うにし、これらのウェハ50枚をオリエンテーションフ
ラットの位置を一定にして重ね合せ熱軟化性の接着剤で
接着して円筒状とし、この円筒状ウェハの外周部を円筒
研削装置で直径50■の円筒形に研削し、更にオリエン
テーションフラット部を幅10MIRに研削した。第1
図において5は加工後のウェハ、6がオリエンテーショ
ンフラット部を示す。
5i0211 is formed on both sides of the wafer 1 by vapor phase epitaxy (CVD) to prevent damage to the surface, and 50 of these wafers are stacked with the orientation flat at a constant position and thermally softened. The outer periphery of this cylindrical wafer was ground into a cylindrical shape with a diameter of 50 cm using a cylindrical grinder, and the orientation flat part was further ground into a width of 10 MIR. 1st
In the figure, 5 shows the wafer after processing, and 6 shows the orientation flat part.

研削終了侵は熱軟化性接着剤をトリクロールエチレンで
溶解して除去し、更にS i O2mをフッ化水素酸に
より溶解して除去する。
After grinding, the heat-softening adhesive is dissolved and removed with trichlorethylene, and the S i O2m is further dissolved and removed with hydrofluoric acid.

このようにして突起部その他の欠陥が除去された直径5
0m+、オリエンテーシ」ンフラット幅10m+のGa
Asウェハ50枚が同時に得られる。
Diameter 5 with protrusions and other defects removed in this way
0m+, orientation flat width 10m+ Ga
Fifty As wafers can be obtained at the same time.

このrウェハを用いて発光ダイオードを作成するためウ
ェハにホトレジストを塗布して発光ダイオードのパター
ンを形成したが、ホトレジストの厚さを均一とすること
ができ、又露光も円滑に行うことができるので、特性良
好な発光ダイオードを得ることができる。製品の合格率
を手作業の場合に比べると約20%向上しており、1枚
当たりの加工時間は同じく手作業の場合に比べ1/3以
下となることが認められた。
In order to create light emitting diodes using this R wafer, a light emitting diode pattern was formed by coating the wafer with photoresist, but the thickness of the photoresist could be made uniform and exposure could be carried out smoothly. , a light emitting diode with good characteristics can be obtained. It was found that the acceptance rate of the products was improved by approximately 20% compared to the case of manual processing, and the processing time per piece was reduced to less than 1/3 compared to the case of manual processing.

実施例2ニ一辺の長さが45M1厚ざが0.3511m
のp型GaAS駐機に液相エピタキシャル成長法により
p型Ga   Aj!  As(x=1−x× 0.37>層を20μmの厚さに形成させ、n型Ga1
.AfJ、As (Y=0.6)層をへさ30μmとな
るように連続成長させた。
Example 2 Length of one side is 45M1 Thickness is 0.3511m
p-type GaA Aj! by liquid phase epitaxial growth method on the p-type GaAS parked in Aj! As (x=1−xx×0.37> layer was formed to a thickness of 20 μm, and n-type Ga1
.. AfJ, As (Y=0.6) layers were continuously grown to a height of 30 μm.

このウェハは赤色発光ダイオードの製造に使用されるが
、ウェハ端部に突起部が形成された。
This wafer was used to manufacture red light emitting diodes, but a protrusion was formed on the edge of the wafer.

第2図はこの場合のウェハを示すもので、7がエピタキ
シャル成長後の角形ウェハである。2及び3は第1図同
様夫々平坦部及び突起部を示す。
FIG. 2 shows the wafer in this case, where 7 is a rectangular wafer after epitaxial growth. 2 and 3 indicate a flat portion and a protrusion, respectively, as in FIG.

このウェハ7の両面にSiO2!l!JをCVD法によ
り形成させ、次に面取り装置によりウェハ7の外周部を
研削して直径41履の円形ウェハに加工し、更に端部を
面取りした。第2図において8が加工後のウェハ、9が
オリエンテーションフラット部を示す。
SiO2 on both sides of this wafer 7! l! J was formed by the CVD method, and then the outer peripheral portion of the wafer 7 was ground using a chamfering device to form a circular wafer having a diameter of 41 mm, and the edges were further chamfered. In FIG. 2, reference numeral 8 indicates the wafer after processing, and reference numeral 9 indicates the orientation flat portion.

このようにして角形ウェハ7より突起部等の欠陥部が取
除かれた円形ウェハが得られるが、このウェハより得ら
れた発光ダイオードの特性も実施例1の場合と同様に良
好であった。
In this way, a circular wafer with defective parts such as protrusions removed from the square wafer 7 was obtained, and the characteristics of the light emitting diode obtained from this wafer were also good as in Example 1.

上述の各実施例ではエピタキシャル成長を行わ往る基板
の形状としては円形又は角形の場合について示したが、
これは特定な形状でなくとも矩形その他、不定形のもの
を用いることができる。
In each of the above embodiments, the shape of the substrate on which epitaxial growth is performed is circular or square.
This does not have to have a specific shape, but may be rectangular or other irregular shapes.

これらの基板より円形ウェハを取出す方法としては実施
例1に示すように1クエ八を多数枚重ね円筒状にして研
削する方式、及び実施例2に示すように面取り装置で加
工する方式があるが、その他超音波によるくり抜き加工
方式、ベベリング装置による研削方式等各種の方法を用
いることができる。尚加工時に生ずるウェハの歪はエツ
チングにより除去することができる。
Methods for extracting circular wafers from these substrates include a method of stacking a large number of wafers in a cylindrical shape and grinding them as shown in Example 1, and a method of machining them with a chamfering machine as shown in Example 2. Various other methods can be used, such as a hollowing method using ultrasonic waves and a grinding method using a beveling device. Note that distortion of the wafer that occurs during processing can be removed by etching.

又加工時につ1ハの@傷を防止する保護膜は5102膜
の他にレジスト膜等を用いることができる。
In addition to the 5102 film, a resist film or the like can be used as a protective film for preventing scratches during processing.

[発明の効果] 以上述べたように本発明によれば次のような効果が得ら
れる。
[Effects of the Invention] As described above, according to the present invention, the following effects can be obtained.

(1)液相エピタキシャル成長法を用いてエピタキシャ
ル層を成長さぜる場合、ウェハ端部に発生する突起部等
欠陥部を除去して円形に整形されたウェハを得ることが
できる。
(1) When growing an epitaxial layer using a liquid phase epitaxial growth method, a circularly shaped wafer can be obtained by removing defects such as protrusions that occur at the edge of the wafer.

(2)円形ウェハへの加工は機械加工により行うことが
できるので従来の手作業による加工法に比べ効率、経済
性等を格段に向上することができる。
(2) Since processing into circular wafers can be performed by mechanical processing, efficiency, economy, etc. can be significantly improved compared to conventional manual processing methods.

(3)自動化による加工整形が旬能となり、ウェハの量
産化、品質の安上等を向上させることができるので、こ
れを用いて製造される各種素子の性能を飛躍的に上界さ
せることができる。
(3) Processing and shaping through automation will become a new skill, and it will be possible to mass produce wafers and improve quality and quality, so the performance of various devices manufactured using this technology will be dramatically improved. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は夫々本発明の化合物半導体ウェハの
製造方法による一実施例を示すウェハ表面図、第3図は
液相エピタキシャル成長後のつ1ハ表面図、第4図は第
3図の部分断面図を示す。 1.7:エピタキシャル成長後のウェハ、2:平 坦 
部、 3:突 起 部、 5.8:加工後の円形ウェハ。
1 and 2 are wafer surface views showing one embodiment of the compound semiconductor wafer manufacturing method of the present invention, FIG. 3 is a wafer surface view after liquid phase epitaxial growth, and FIG. A partial cross-sectional view is shown. 1.7: Wafer after epitaxial growth, 2: Flat
Part 3: Projection part 5.8: Circular wafer after processing.

Claims (1)

【特許請求の範囲】 1、液相エピタキシャル成長方法を用いて半導体基板に
エピタキシャル層を形成する化合物半導体ウェハの製造
方法において、前記エピタキシャル層形成後のウェハを
前記半導体基板の形状に拘らず機械研削により単独もし
くは多数枚同時に突起部等欠陥部を除去して円形に加工
整形することを特徴とする化合物半導体ウェハの製造方
法。 2、前記ウェハは、前記機械研削時に少なくともエピタ
キシャル層表面側に保護膜を形成した後に加工整形する
ものである特許請求の範囲第1項記載の化合物半導体ウ
ェハの製造方法。 3、前記加工整形後のウェハは、加工時に生ずる歪はエ
ッチングにより除去し、その後に前記保護膜を除去する
ものである特許請求の範囲第2項記載の化合物半導体ウ
ェハの製造方法。
[Claims] 1. In a method for manufacturing a compound semiconductor wafer in which an epitaxial layer is formed on a semiconductor substrate using a liquid phase epitaxial growth method, the wafer after the epitaxial layer is formed is mechanically ground regardless of the shape of the semiconductor substrate. A method for manufacturing compound semiconductor wafers, which comprises removing defective parts such as protrusions and shaping a compound semiconductor wafer individually or simultaneously into a circular shape. 2. The method for manufacturing a compound semiconductor wafer according to claim 1, wherein the wafer is processed and shaped after forming a protective film on at least the epitaxial layer surface side during the mechanical grinding. 3. The method for manufacturing a compound semiconductor wafer according to claim 2, wherein the processed and shaped wafer is subjected to etching to remove distortions caused during processing, and then the protective film is removed.
JP11315488A 1988-05-10 1988-05-10 Manufacture of compound semiconductor wafer Pending JPH01283836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11315488A JPH01283836A (en) 1988-05-10 1988-05-10 Manufacture of compound semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11315488A JPH01283836A (en) 1988-05-10 1988-05-10 Manufacture of compound semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH01283836A true JPH01283836A (en) 1989-11-15

Family

ID=14604934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11315488A Pending JPH01283836A (en) 1988-05-10 1988-05-10 Manufacture of compound semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH01283836A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016117209A1 (en) * 2015-01-21 2016-07-28 住友電気工業株式会社 Silicon carbide substrate and method for manufacturing silicon carbide substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016117209A1 (en) * 2015-01-21 2016-07-28 住友電気工業株式会社 Silicon carbide substrate and method for manufacturing silicon carbide substrate
CN107109695A (en) * 2015-01-21 2017-08-29 住友电气工业株式会社 The manufacture method of silicon carbide substrate and silicon carbide substrate

Similar Documents

Publication Publication Date Title
US5920769A (en) Method and apparatus for processing a planar structure
US20060057850A1 (en) Method of manufacturing carrier wafer and resulting carrier wafer structures
US20040104491A1 (en) Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive
US20170011964A1 (en) Reusable semiconductor substrates
TWI747695B (en) Indium Phosphide Substrate
US6974721B2 (en) Method for manufacturing thin semiconductor chip
JPH01283836A (en) Manufacture of compound semiconductor wafer
CN113692639A (en) Indium phosphide substrate and method for producing indium phosphide substrate
TWI781801B (en) Indium phosphide substrate, manufacturing method of indium phosphide substrate, and semiconductor epitaxial wafer
US20230392289A1 (en) Indium phosphide substrate, method for manufacturing indium phosphide substrate, and semiconductor epitaxial wafer
CN113646873A (en) Indium phosphide substrate and method for producing indium phosphide substrate
US8033011B2 (en) Method for mounting a thinned semiconductor wafer on a carrier substrate
US20140284660A1 (en) Method for manufacturing semiconductor wafer, and semiconductor wafer
TWI810847B (en) Indium Phosphide Substrate
US20230082020A1 (en) Indium phosphide substrate
JP2005032804A (en) Semiconductor wafer processing method
JPH11289107A (en) Polygonal epitaxial wafer
US20240112928A1 (en) Trimming method
JP2825715B2 (en) Method for manufacturing compound semiconductor wafer
JPH1070056A (en) Semiconductor substrate and its manufacture
JPH10150218A (en) Epitaxial wafer
JPH04342116A (en) Manufacture of epitaxial growth wafer
JP2004165484A (en) Processing method for semiconductor wafer
JPH07221056A (en) Semiconductor wafer
JPH02164794A (en) Epitaxial growth method for compound semiconductor