JPH01282826A - Electronic device and manufacture thereof - Google Patents
Electronic device and manufacture thereofInfo
- Publication number
- JPH01282826A JPH01282826A JP11318988A JP11318988A JPH01282826A JP H01282826 A JPH01282826 A JP H01282826A JP 11318988 A JP11318988 A JP 11318988A JP 11318988 A JP11318988 A JP 11318988A JP H01282826 A JPH01282826 A JP H01282826A
- Authority
- JP
- Japan
- Prior art keywords
- solder ball
- solder
- layer
- film sheet
- sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910000679 solder Inorganic materials 0.000 claims abstract description 45
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 abstract description 8
- 239000004642 Polyimide Substances 0.000 abstract description 7
- 239000007864 aqueous solution Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 230000035882 stress Effects 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000003779 heat-resistant material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910002710 Au-Pd Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- 229910000366 copper(II) sulfate Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明の電子機器装置の構造およびその製造方法に関し
、特に半導体素子を回路基板にフリップチップ実装して
なる電子機器装置の構造およびその製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of an electronic device and its manufacturing method, particularly the structure of an electronic device formed by flip-chip mounting a semiconductor element to a circuit board and its manufacturing method. Regarding.
はんだバンプを用いたフリップチップ実装技術では以前
からはんだポールが熱ストレスにより破壊しやすいこと
が問題となっていた。この改善を目的とした従来技術と
して、松井他「多段はんだバンプ接続技術」電子通信学
会報告会ＣＰＭ８７−３８． ＰＰ １９−２４に示さ
れているようにポリイミドフィルムに形成したはんだポ
ールを積み重ねる方法がある。Flip-chip mounting technology using solder bumps has long had a problem in that the solder poles are easily destroyed by thermal stress. As a conventional technique aimed at improving this, Matsui et al., "Multi-stage solder bump connection technology" IEICE report meeting CPM87-38. There is a method of stacking solder poles formed in polyimide film as shown in PP 19-24.
上述した従来の積層はんだバンブを用いるフリップチッ
プ技術では、はんだポールを直列に積層してＬＳＩチッ
プと基板を接続しているため、熱膨張係数の違いにより
生じる応力はそのままはんだポールに加わり、はんだポ
ールと基板およびはんだポールとＬＳＩチップの境界部
に応力が集中している。従来技術でははんだポールの高
さを３００μｍとして２段はんだバンプにした場合前記
文献の図９に示すごと＜１０００回以下の温度サイクル
で破壊がおこっている。はんだポールの高さを低くした
場合にはより大きな応力が生じることが知られており、
（前記文献のＰ２０参照）従来技術でより微細ピッチの
接続を行なう場合にはどうしてもはんだポールの高さを
低くせねばならず、それでは充分な信頼性が得られない
。このため接続端子数が多い半導体素子の接続技術とし
ては従来技術は適用できないことが問題となる。In the above-mentioned conventional flip-chip technology using laminated solder bumps, the solder poles are stacked in series to connect the LSI chip and the board, so the stress caused by the difference in thermal expansion coefficients is directly applied to the solder poles, causing the solder poles to Stress is concentrated at the boundary between the substrate, the solder pole, and the LSI chip. In the prior art, when the height of the solder pole is 300 .mu.m and a two-stage solder bump is formed, as shown in FIG. 9 of the above-mentioned document, destruction occurs after less than 1000 temperature cycles. It is known that lowering the height of the solder pole causes greater stress.
(See page 20 of the above-mentioned document) When using the prior art to make connections with a finer pitch, it is necessary to reduce the height of the solder poles, which does not provide sufficient reliability. Therefore, the problem is that the conventional technology cannot be applied as a connection technology for semiconductor elements having a large number of connection terminals.
〔課題を解決するための手段〕
本発明のフリップチップ実装技術は、ポリイミド等で形
成したフィルムシート上に導体配線とポリイミド等の有
機膜で形成した絶縁層を有し、導体配線の両端の位置に
フィルムシートと絶縁膜に形成したスルーホールを有し
、そのスルーホール部分にはんだポールを有し、そのは
んだポールによりＬＳＩチップと基板回路を接続してい
る。[Means for Solving the Problems] The flip-chip mounting technology of the present invention has a conductor wiring and an insulating layer formed of an organic film such as polyimide on a film sheet formed of polyimide or the like, and the positions of both ends of the conductor wiring are The device has a through hole formed in the film sheet and the insulating film, and a solder pole is provided in the through hole portion, and the LSI chip and the board circuit are connected by the solder pole.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（＄）は本発明の一実施例の縦断面図で
ある。まず第１図（ａ）に示すようにポリイミド、ガラ
スエポキシ等の耐熱性材料で形成したフィルムシート１
０１に銅（Ｃｕ）、チタン（Ｔｉ）。FIGS. 1(a) to ($) are longitudinal cross-sectional views of one embodiment of the present invention. First, as shown in FIG. 1(a), a film sheet 1 made of a heat-resistant material such as polyimide or glass epoxy is used.
Copper (Cu) and titanium (Ti) for 01.
銅（Ｃｕ）の順でスパッタを行ない導体層１０２を形成
する。ここでフィルムシート１０１の膜厚は１０〜ｌＯ
Ｏμｍ１導体層１０２は約５μｍ以下とした。また導体
層１０２としては例えばＳｎ。A conductor layer 102 is formed by sputtering copper (Cu) in this order. Here, the film thickness of the film sheet 101 is 10 to 10
The Oμm1 conductor layer 102 was approximately 5 μm or less. Further, the conductor layer 102 is made of Sn, for example.
Ａｎ、Ｐｔ、Ｎｉ、Ｃｒ等を組み合わせて用いることも
できる。次に第１のフォトレジスト層１０３を形成する
。次に第１のフォトレジスト層１０３をマスクとして硫
酸銅（ＣｕＳＯ４）水溶液中で銅の電気メツキを行ない
、次に金メツキ液中で金の電気メツキを行ない配線層１
０４を形成する。Combinations of An, Pt, Ni, Cr, etc. can also be used. Next, a first photoresist layer 103 is formed. Next, using the first photoresist layer 103 as a mask, copper is electroplated in a copper sulfate (CuSO4) aqueous solution, and then gold is electroplated in a gold plating solution to form the wiring layer 1.
Form 04.
配線層１０４の膜厚は１０〜２０μｍとする。The thickness of the wiring layer 104 is 10 to 20 μm.
次に第１図（ｂ）に示すように第１の７オトレジスト層
１０３を剥離する。次に配線層１０４をマスクとして希
硫酸（Ｈ２ＳＯ４）、フッ化水素（ＨＦ）水溶液中で導
体層１０２の一部の領域をエツチング除去する。次に感
光性ポリイミドを塗布し、露光、現像することにより絶
縁層１０５を形成する。Next, as shown in FIG. 1(b), the first seven photoresist layers 103 are peeled off. Next, a part of the conductor layer 102 is removed by etching in a dilute sulfuric acid (H2SO4) or hydrogen fluoride (HF) aqueous solution using the wiring layer 104 as a mask. Next, photosensitive polyimide is applied, exposed to light, and developed to form an insulating layer 105.
この絶縁層１０５ははんだレジストとなる。This insulating layer 105 becomes a solder resist.
次に第１図（Ｃ）に示すようにフィルムシート１０１に
第２のフォトレジスト層１０６を形成する。次にそれを
マスクとしてヒドラジン等の液中でフィルムシート１０
１の一部の領域をエツチングしてピアホール１０７を形
成する。Next, a second photoresist layer 106 is formed on the film sheet 101 as shown in FIG. 1(C). Next, using it as a mask, 10 film sheets were placed in a liquid such as hydrazine.
1 is etched to form a pier hole 107.
次に第１図（ｄ）に示すごとく第２のフォトレジスト層
１０６を剥離する。次に有機酸を含むはんだメツキ液中
で鉛、スズから成るはんだをメツキし、その後の熱処理
により第１のはんだポール１０８および第２のはんだポ
ール１０９を形成する。Next, as shown in FIG. 1(d), the second photoresist layer 106 is peeled off. Next, solder consisting of lead and tin is plated in a solder plating solution containing an organic acid, and a first solder pole 108 and a second solder pole 109 are formed by subsequent heat treatment.
次に、第１図（チ）に示すように、半導体素子１１０に
Ｔｉ、Ｃｕ、Ａｕで形成した第２の電極１１１とフィル
ムシート１０１上の第１のはんだポール１０８の位置合
わせとしてフラックスを使用して半導体素子１１０とフ
ィルムシート１０１を仮止めする。次に回路基板１１２
上にＣｕ、Ａｕを用いて形成した第２の電極１１３をフ
ィルムシート１０１上の第２のはんだポール１０９に位
置合わせをして仮止めする。次にリフロー炉の中で溶解
させて端子接続を行なう。Next, as shown in FIG. 1(H), flux is used to align the second electrode 111 formed of Ti, Cu, and Au on the semiconductor element 110 and the first solder pole 108 on the film sheet 101. Then, the semiconductor element 110 and the film sheet 101 are temporarily attached. Next, the circuit board 112
A second electrode 113 formed on the top using Cu and Au is aligned with the second solder pole 109 on the film sheet 101 and temporarily fixed. Next, it is melted in a reflow oven and terminal connections are made.
次に本発明の他の実施例について第２図を用いて説明す
る。まず第２図に示すようにポリイミド等の耐熱性材料
で形成したフィルムシート２０１にスクリーン印刷で銅
ペーストを印刷し配線層２０２を形成する。ここで配線
材料としてＡｇ。Next, another embodiment of the present invention will be described using FIG. 2. First, as shown in FIG. 2, a wiring layer 202 is formed by printing copper paste on a film sheet 201 made of a heat-resistant material such as polyimide by screen printing. Here, Ag is used as the wiring material.
Ａｇ−Ｐｄ、Ａｕ、Ａｕ−Ｐｄ、Ａｕ−Ｐｔ等を用いる
こともできる。次に感光性ポリイミドを塗布し露光現像
することにより絶縁層２０３を形成する。以下の方法は
第１図の一実施例の第１図（ｃ）以下と同様であるため
省略する。この他の実施例では工程を大巾に短縮できる
という利点を有する。Ag-Pd, Au, Au-Pd, Au-Pt, etc. can also be used. Next, an insulating layer 203 is formed by applying photosensitive polyimide and exposing and developing it. The following method is the same as that shown in FIG. 1(c) and subsequent steps in the embodiment shown in FIG. 1, so the description thereof will be omitted. This other embodiment has the advantage that the process can be greatly shortened.
本発明のフリップチップ接続技術は従来技術に比べて、
はんだポールに加わる応力が緩和される。Compared to the conventional technology, the flip-chip connection technology of the present invention has the following advantages:
The stress applied to the solder pole is alleviated.
これを第１図（４）を参照しながら説明する。第１図（
−＄）の電子機器装置に温度変化が生じたとすると、回
路基板１１２および半導体素子１１０間の熱膨張係数の
差により両者の間にひずみΔδが生じる。このひずみΔ
δは第１のはんだポール１０８の変形ひずみΔδ１、第
２のはんだポール１０９の変形ひずみΔδ２、配線層１
０４の変形ひずみΔδ、に分割される。つまり
Δδ＝Δδ１＋Δδ２＋Δδ、 ・・・・・・（
１）となる。ここで第１のはんだポール１０８に加わる
せん断応力τは、Δδ１に比例する。従来技術の多段は
んだバンプでは（１）式で、Δδ、＝０であり、本発明
ではΔδ３〉０であるため、（１）式より本発明の方が
Δδ１が小さい。よって第１のはんだポール１０８に加
わるせん断応力τは本発明では従来技術よりも小さくな
ることがわかる。This will be explained with reference to FIG. 1 (4). Figure 1 (
-$) When a temperature change occurs in the electronic device, the difference in thermal expansion coefficient between the circuit board 112 and the semiconductor element 110 causes strain Δδ between them. This strain Δ
δ is the deformation strain Δδ1 of the first solder pole 108, the deformation strain Δδ2 of the second solder pole 109, and the wiring layer 1
04 deformation strain Δδ,. In other words, Δδ=Δδ1+Δδ2+Δδ, ・・・・・・(
1). Here, the shear stress τ applied to the first solder pole 108 is proportional to Δδ1. In the conventional multi-stage solder bump, Δδ=0 in equation (1), and in the present invention, Δδ3>0, so Δδ1 is smaller in the present invention than in equation (1). Therefore, it can be seen that the shear stress τ applied to the first solder pole 108 is smaller in the present invention than in the prior art.
以上の説明から本発明は従来技術にくらべて応力が緩和
されるため、熱ストレスに対する信頼性が大巾に向上す
るという大きな効果がある。またこのためはんだポール
を微小化しても充分な信頼性のある接続が可能で、はん
だポール間のピッチを微細化できる効果がある。As can be seen from the above description, the present invention has the great effect of significantly improving reliability against thermal stress because the stress is relaxed compared to the prior art. Furthermore, even if the solder poles are miniaturized, connection with sufficient reliability is possible, and the pitch between the solder poles can be miniaturized.
第１図（ａ）〜（＄）は本発明の一実施例を説明するた
めの工程縦断面図、第２図は本発明の他の実施例を説明
するための縦断面図である。
１０１・・・・・・フィルムシート、１０２・・・・・
・導体層、１０３・・・・・・第１のフィルムシート層
、１０４・・・・・・配線層、１０５・・・・・・絶縁
層、１０６・・・・・・第２のフォトレジスト層、１０
７・・・・・・ピアホール、１０８・・・・・・第１の
はんだポール、１０９・・・・・・第２のはんだポール
、１１０・・・・・・半導体素子、１１１・・・・・・
第１の電極、１１２・・・・・・回路基板、１１３・・
・・・・第２のｉｌＥ＆、２０１・・・・・・フィルム
シート、２０２・・・・・・配線層、２０３・・・・・
・絶縁層。
代理人 弁理士 内 原 晋FIGS. 1(a) to ($) are process longitudinal cross-sectional views for explaining one embodiment of the present invention, and FIG. 2 is a longitudinal cross-sectional view for explaining another embodiment of the present invention. 101...Film sheet, 102...
・Conductor layer, 103...First film sheet layer, 104...Wiring layer, 105...Insulating layer, 106...Second photoresist layer, 10
7... Pier hole, 108... First solder pole, 109... Second solder pole, 110... Semiconductor element, 111...・・・
First electrode, 112...Circuit board, 113...
...Second ILE&, 201...Film sheet, 202...Wiring layer, 203...
・Insulating layer. Agent Patent Attorney Susumu Uchihara
Claims (2)
にフリップチップ実装してなる電子機器装置において、
前記フィルムシートに導電性材料よりなる配線層が形成
されかつ前記配線層の一端の表面側に第１のはんだボー
ルが形成されかつ前記配線層の他端の裏面側に第２のは
んだボールが形成されかつ前記半導体素子に形成された
第１の電極が前記第１のはんだボールと接合されかつ前
記回路基板に形成された第２の電極が前記第２のはんだ
ボールと接合されかつ前記第１のはんだボールおよび前
記第２のはんだポールが前記フィルムシートの異なる位
置に存在することを特徴とする電子機器装置。(1) In an electronic device in which a semiconductor element is flip-chip mounted on a circuit board by sandwiching a film sheet,
A wiring layer made of a conductive material is formed on the film sheet, a first solder ball is formed on the front side of one end of the wiring layer, and a second solder ball is formed on the back side of the other end of the wiring layer. and a first electrode formed on the semiconductor element is bonded to the first solder ball, a second electrode formed on the circuit board is bonded to the second solder ball, and a first electrode formed on the semiconductor element is bonded to the first solder ball. An electronic device characterized in that the solder ball and the second solder pole are located at different positions on the film sheet.
、前記フィルムシートに前記配線層を形成する工程と前
記フィルムシート上に絶縁層を形成する工程と前記絶縁
層に第１のスルーホールを形成する工程と前記フィルム
シートに第２のスルーホールを形成する工程と前記配線
層に前記第１および第２のスルーホール部分に前記第１
および第２のはんだボールを形成する工程を含むことを
特徴とする請求項１記載の電子機器装置の製造方法。(2) A method for manufacturing an electronic device according to claim 1, including the step of forming the wiring layer on the film sheet, the step of forming an insulating layer on the film sheet, and the step of forming a first through hole in the insulating layer. forming a second through hole in the film sheet; and forming a second through hole in the first and second through hole portions of the wiring layer.
2. The method of manufacturing an electronic device according to claim 1, further comprising the steps of: and forming a second solder ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11318988A JPH01282826A (en) | 1988-05-09 | 1988-05-09 | Electronic device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11318988A JPH01282826A (en) | 1988-05-09 | 1988-05-09 | Electronic device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01282826A true JPH01282826A (en) | 1989-11-14 |
Family
ID=14605812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11318988A Pending JPH01282826A (en) | 1988-05-09 | 1988-05-09 | Electronic device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01282826A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6395637A (en) * | 1986-10-13 | 1988-04-26 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1988
- 1988-05-09 JP JP11318988A patent/JPH01282826A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6395637A (en) * | 1986-10-13 | 1988-04-26 | Hitachi Ltd | Semiconductor integrated circuit device |
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