JPH01280351A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a DRAM cell whose capacity is large, which is resistant to a soft error and whose cell area is small by forming a capacitor after a first conductive thin film, a dielectric film, a second conductive thin film, a dielectric film and a third conductive thin film are piled up inside a groove whose inner wall has been covered with an insulating film. CONSTITUTION:A groove 33 is formed in an active region on the surface of a semiconductor substrate 31; its inner wall is covered with an insulating film 34; a first conductive thin film 36 and a first dielectric film 37 are formed in a prescribed region including the inside of the groove 33; after that, an oxide film 39 is formed at an end part of the first conductive thin film 36; a contact diffusion layer 42 is formed by the immediate side of the groove 33; a contact part 43 is formed. After that, a second conductive thin film 44, a dielectric film 45 and a third conductive thin film 47 are formed on the whole surface including the inside of the groove 33; these are patterned one after another by using an identical mask; these are left as a second cell plate of a capacitor, a second dielectric film 45 and a storage electrode in a prescribed region including the groove 33 and an upper part of the contact part 43; the second conductive thin film 44 as the storage electrode is set to a state that its end part has been connected to the contact diffusion layer 42.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, which consists of a capacitor and one MO5 type transistor. DR formed in
The present invention relates to a method for manufacturing an AM cell.

(Prior Art) A conventional method of manufacturing a RAM cell as described above will be explained with reference to FIG.

First, a field oxide film 2 with a thickness of 4,500 to 6,000 layers is selectively formed on the surface of a P-type silicon substrate 1 by the LOCO3 method, and then a thermal oxide film 3 with a thickness of about 300 layers is formed on the surface of the substrate 1 in the active area. A through this thermal oxide film 3
By selectively implanting s ions into the substrate 1, a layer 4 is formed on the N-type plate 11 selectively in the active region of the substrate.

After that, the entire surface of the substrate 1 is coated with a film of 300~
The nitride film 5 was grown at 1000 JV, and further APCV
An oxide film 6 is grown to a thickness of 5,000 to 10,000 layers using the D method. (FIG. 4(a)) Next, an opening 7 is formed in the oxide film 6.3.2 and the nitride film 5 by photolithography and anisotropic etching. Then, by anisotropically etching the substrate 1 through the opening 7 using the oxide film 6 as a mask, >Ba is formed on one side of the substrate active region. Even with this groove formation, the N-type diffusion N4 remains in the active region adjacent to the groove 8 to a predetermined length.

(Fig. 4(b)) Next, etching for cleaning inside the groove 8 was performed using HF/HNO.
3, the oxide film 6 is removed by HF water, and thermal oxidation is performed using the exposed nitride layer 5 as a mask to form an insulating film 15 on the inner wall of the trench 8.
A thermal oxide film 9 with a thickness of 0.00 to 3000 is formed (see Fig. 4).
C)). Thereafter, the nitride film 5 is removed using hot phosphoric acid.

Next, a contact hole 10 is opened in a part of the N-type diffusion layer 4 in the oxide film 3 on the surface of the substrate 1 in the active area by photolithography and etching (FIG. 4(d)).

Thereafter, a first conductive thin film with a thickness of 1000 mm is applied to the entire surface of the substrate 1 including the inside of a8 covered with the thermal oxide film 9 (insulating film).
~2000 polysilicon films 11 are grown by LPCVD, and POCj! t (4~6
x 10"cIll-').

At this time, in the contact hole 10 portion, phosphorus is diffused into the substrate 1 through the polysilicon film 11, and an N-type layer 12 is formed in combination with the N-type diffusion layer 4.

After this poc z is diffused, the polysilicon film 11 is patterned by photolithography and etching, so that the polysilicon film 11 is formed with one end connected to the N-type layer 12 and the N-type diffusion layer 4 through the contact hole 10. is left in the groove 8 to form the storage electrode of the capacitor.

(Fig. 4(e)) Next, after growing a dielectric film 13 on the entire surface including the surface of the polysilicon film 11 (i-product electrode), polysilicon yA14 is grown as a second conductive thin film on top of the dielectric film 13. This is then subjected to vapor phase diffusion of POCl 3 .

Next, by growing 7,000 to 10,000 embedding materials 15 and etching back the embedding material 15, the remaining grooves are filled with the embedding material 15 and flattened.

Thereafter, by patterning the polysilicon film 14, the dielectric film 13, and the oxide film 3, the polysilicon film 14 and the dielectric film 13 are left only in the capacitor formation region H including the groove, and serve as the cell plate of the capacitor. A dielectric film is used, and the oxide film 3 is removed from unnecessary parts. (FIG. 4(f)) After that, the polysilicon film 14 (cell plate) and the embedding material 15 are covered with a glabella insulating film 16, and the other side of the active area where the surface of the substrate 1 is exposed by removing the oxide film 3. Gate oxide film 17° gate electrode 1 in the area of
B. A transfer gate MOS transistor 20 is formed by forming a pair of N-type diffusion layers 19. After that, an intermediate insulating film 21 is formed on the entire surface, a contact hole 22 is opened, and the MO
A DRAM cell is completed by forming a bit line 23 connected to one N-type diffusion layer 19 of the S-type transistor 20 and finally covering the surface with a protective film 24. (FIG. 4(g)) Note that the other N-type diffusion layer 19 on the capacitor side of the MOS transistor 20 is connected to the N-type diffusion layer 4. Thereby, the storage electrode (polysilicon film 11) of the capacitor is connected to the other diffusion Jii19 of the MOS transistor 20 through the N-type layer 12 and the N-type plate diffusion JW4 (contact diffusion layer). Further, when forming the gate electrode 18 of the MOS transistor 20, a word line 25 (the illustrated portion is a word line of an adjacent cell) is formed by extending it.

(A! Problem to be solved by the invention) However, in the conventional DRAM cell manufacturing method as described above, the capacitor is formed by simply stacking the storage layer 1 and the cell layer 1- with a dielectric film in between. Because of this, the capacitance of the capacitor cannot be sufficiently increased (°), resulting in a disadvantage that only cells that are susceptible to soft errors can be obtained. In addition, as shown in FIG. 4 [g+], a distance ΔL is required between the groove and the contact hole 10 as a mask alignment margin, and a distance ΔLx is required between the ends of the polysilicon film 11 and 14 as a mask alignment margin. Therefore, there was a drawback that the cell area increased.

This invention eliminates the above-mentioned drawbacks that the capacitance of the capacitor is not sufficient for soft error resistance and the drawback that the cell area increases, and has a large capacitance that is resistant to soft errors.
It is an object of the present invention to provide a method for manufacturing a semiconductor memory device that can obtain a DRAM cell with a small cell area.

(Means for Solving the Problems) In the present invention, a first conductive thin film is formed in a groove formed in a semiconductor substrate and whose inner wall is covered with an insulating film. 1 dielectric film) second conductive thin film (
A capacitor is formed by stacking a storage electrode), a dielectric film (second dielectric film), and a third conductive thin film (second cell plate). Further, by utilizing the difference in the thickness of the oxide film, the oxide film is removed from the surface of the active region substrate immediately next to the groove to form a contact portion in which the surface of the contact diffusion layer is exposed. Furthermore, the second. The third conductive thin film and the dielectric film therebetween are sequentially patterned using the same mask, and are left in predetermined regions including the trench and the contact portion.

(Function) According to the above method, a capacitor is formed with a structure in which a storage electrode is sandwiched between a pair of cell plates from both sides with a dielectric film interposed therebetween, and the capacitance 1 is almost twice as large as that of a conventional capacitor. In addition, by exposing the surface of the contact diffusion layer right next to the groove, contact between the storage electrode (second conductive thin film) and the contact diffusion layer is realized right next to the groove.
The part corresponding to the conventional ΔL1 is no longer required, and by patterning using the same mask, the second cell plate (third conductive thin film) is formed with its edges aligned on the storage electrode, which is different from the conventional one. The portion corresponding to ΔL2 is also unnecessary.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 ta+ to +hl are process sectional views of an embodiment of the present invention.

First, the surface of a P-type silicon substrate 31 is separated into an active region and a field region by a field oxide film 32 with a thickness of 4500 to 6000 Å selectively formed on the surface, and a groove is formed in the substrate on one side of the active region. 33 is formed, the inner wall of this groove 33 is covered with a thermal oxide film 34 (insulating film) of 1,500 to 3,000 layers, and the substrate surface of the active SJTM (hereinafter referred to as transistor formation region) other than the groove is covered with a layer of 301). A structure covered with a thermal oxide film 35 of about 100 mL is manufactured (FIG. 1(a)). This structure is the same as the conventional structure shown in FIG. 4(C) except that there is no N-type diffusion layer, and is manufactured in the same manner as the conventional structure.

Next, the thermal oxide film 35 on the substrate surface in the transistor formation region is removed by etchback using the difference in thickness with the oxide films 32 and 34, and after exposing the substrate surface in the transistor formation region, the thermal oxide film 35 is removed by etchback. A first polysilicon film 36 containing N-type impurities at a high concentration is applied as a first conductive thin film over the entire surface including the inside of the trench 33 whose inner wall is covered with the film 34.
The dielectric film 37, for example, a nitride film, is grown on the surface of the dielectric film 37 by 300 to 500 films (FIG. 1).

Next, a resist pattern 38 was formed by normal gluing lithography technique so as to cover the necessary portion on the field region and the groove portion on the opposite side of the transistor formation region (first
After that, the first polysilicon film 36 and the dielectric film 37 are patterned by anisotropic etching using the resist pattern 38 as a mask. The first cell plate and the first dielectric film of the capacitor are left only in the trench and a predetermined part of the field clay, and the dielectric film 37 and the first dielectric film are left entirely on the substrate 31 in the transistor formation region.
The structure is such that the polysilicon film 36 is removed (FIG. 1(d)). At this time, if the resist pattern 38 does not completely cover the bottom of the trench in half of the trench as shown in FIG. It is etched as shown in Figure (, 11).

Then, in the figure, the first polysilicon film 36 is divided into two parts on the left and right.
Although the first polysilicon film 36 appears to be separated into two parts, all of the first polysilicon films 36 are connected through the first polysilicon film on the trench sidewall portion. Note that if the resist pattern 38 is formed within the groove 33 so that it reaches half the depth of the groove 33, as shown in FIG. Dielectric film 3 in
Etching of the first polysilicon film 7 and the first polysilicon film 36 is prevented.

Next, after removing the resist pattern 38, oxidation treatment is performed in a wet oxygen atmosphere at 850° C. to 900° C. By this oxidation treatment, the first
An oxide film 39 having a thickness (or width) of 500 to 750 layers is formed on the exposed portion of the polysilicon film 36 . At the same time, due to the difference in oxidation rate, the exposed surface of the silicon substrate 31 in the transistor formation region, which is a single SI, has a
An oxide film 40 having a thickness of 150 layers is formed. (Figure 1(e)
) Next, a resist pattern 41 is formed to expose the adjacent portions of the il$33 and the transistor formation region and cover the other portions.
By ion-implanting N-type impurities at a high concentration using 1 as a mask, a contact diffusion layer 42 of N' is formed in the transistor formation region immediately next to the trench 33 (see FIG. 2(e)).
)). At this time, if a resist pattern 38 as shown in FIG. 1 ff1 is formed and the first polysilicon film 36 remains at the entire bottom of the groove 33 as shown by the peak in FIG. As shown in FIG. 3(C), within a33, a resist pattern 41 is defined to half the depth, and the remaining portion of the resist pattern 41 in the trench is used to cover the first polysilicon film at the bottom of the trench. It is necessary to completely cover all 36 so that the N-type impurity for forming the contact diffusion layer is not ion-implanted into that portion.

Thereafter, by performing anisotropic etching of the oxide film using the resist pattern 41 as a mask, only the oxide film 40 is removed using the difference in thickness from the oxide [39], and the surface of the contact diffusion layer 42 is exposed. A contact portion 43 is formed immediately beside the groove 33 (FIG. 1 ff1).

Thereafter, a second polysilicon film 4 containing a high concentration of N-type impurities is formed as a second conductive thin film over the entire surface including the inside of the groove 33.
4 is grown by 1,000 to 1,500 layers, and a dielectric film 45 made of a nitride film is grown by 300 to 500 layers on the surface thereof.

Thereafter, after separating the dielectric film 45 and the second polysilicon film 44 between adjacent cells, oxidation is performed in a wet oxygen atmosphere at 850°C to 900°C to remove the second polysilicon film exposed by the separation. 800 at the end of the silicon film 44
Form an oxide film 46 with a width of ~900 mm (FIG. 1(f))
.

next,? A third polysilicon film 4 containing a high concentration of N-type impurities is applied as a third conductive thin film over the entire surface including the inside of 1t33.
Grow 7 by 1000-1500 people.

Further, on top of that, an oxide film 48 is formed with a film thickness of 2000 to 2500% by LPCVD so as to fill the remaining part of the trench 33.
Grow into a person. Furthermore, a resist pattern 49 is formed on this oxide film 48 by a known lithography technique. Using this resist pattern 49 as a common mask, the oxide film 48. Third polysilicon film 47. The dielectric film 45 and the second polysilicon film 44 are sequentially etched and patterned using an anisotropic etching technique, and the oxide film 40 on the substrate surface in the transistor formation region is etched and removed (FIG. 1(a), As a result, the second polysilicon film 44, the dielectric film 45, and the third polysilicon film 47 remain only in the capacitor formation region including the trench and the contact part 43, Film 36) First dielectric film (dielectric film 37) on the surface
A storage electrode of the capacitor, a second dielectric film, and a second cell plate are formed overlapping the first and second electrodes. Further, the end portion of the storage electrode (second polysilicon MQ44) is connected to the contact diffusion layer 42 at the contact portion 43 immediately beside the groove 33.

Thereafter, a gate oxide film 50 is formed in the transistor forming region adjacent to the contact diffusion layer 42 where the surface of the substrate 31 is exposed by removing the oxide film 40. Gate electrode 51. A transfer gate MOS transistor 53 is formed by forming a pair of source/drain N type diffusion layers 52 (one of which is connected to the contact diffusion N42). At this time, the word line 54 (the illustrated portion is the word line of the adjacent cell) is formed by extending the gate electrode 51. Then, apply the first layer to the entire surface. Second intermediate! forming fI membranes 55 and 56;
A contact hole 57 is opened, and this contact hole 5
A bit line 58 is formed to be connected to the other N-type diffusion layer 52 through j! The DRAM cell is then completed by covering the surface with a protective film 59. (FIG. 1(h)) FIG. 3 shows an equivalent circuit diagram of the DRAM cell completed in this way.

(Effects of the Invention) As detailed above, according to the manufacturing method of the present invention, the storage electrode is placed in the groove of the semiconductor substrate whose inner wall is covered with an insulating film from both sides with a dielectric film interposed therebetween. Since the capacitor is formed with a structure in which it is sandwiched between a pair of cell plates, the capacitance of the capacitor can be increased nearly twice as much as that of conventional capacitors, making it a DRAM that is resistant to soft errors.
You can get cells. In addition, by taking advantage of the difference in the thickness of the oxide film and removing the oxide film from the substrate surface immediately next to the groove to expose the surface of the contact diffusion layer, the contact between the contact diffusion layer and the storage electrode can be placed directly next to the groove. It can be realized horizontally, and the part corresponding to the conventional ΔL can be eliminated. Furthermore, the third. By sequentially patterning the second conductive thin film and the dielectric film therebetween using the same mask, the second cell plate (third conductive thin film) is placed on the storage electrode (second conductive thin film). It can be formed with the ends aligned, and the conventional ΔL! The part corresponding to can be eliminated. By eliminating ΔL1 and ΔL2, according to the manufacturing method of the present invention, the cell area can be reduced and higher density can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor memory device of the present invention, FIG. 2 is a process cross-sectional view showing a partial modification of the manufacturing method of the invention, and FIG. DRA completed by an embodiment of ? Equivalent circuit diagram of I cell, 4th
The figure is a process cross-sectional view showing a conventional DRAM cell manufacturing method. 31... P-type silicon substrate 232... Field oxide film, 33... Groove, 34... Thermal oxide film, 36...
First polysilicon film, 37... Dielectric film, 39...
- Oxide film, 40... Oxide film, 42... Contact diffusion layer, 43... Contact portion, 44... Second polysilicon film, 45... Dielectric film, 47... No. 3 polysilicon film, 49...resist pattern, 52...
・N-type diffusion layer, 53...transfer gate-FMOS
type transistor. (of
-To Noro
- Portrait of Tomari - Implementation of the manufacturing method of the present invention Fig. 1 53 = Transfer gate MO5 type transistor Equivalent circuit diagram of the DRAM cell according to the present invention 1 Fig. 3 Conventional manufacturing method Fig. 4

Claims (1)

[Claims] (a) After selectively forming a field oxide film on the surface of a semiconductor substrate to separate the substrate into an active region and a field region, grooves are selectively formed in the substrate portion of the active region. (b) forming a first conductive thin film on the entire surface including the inside of the groove; (c) patterning the conductive film and the first conductive thin film to form the first dielectric film and the first conductive thin film of the capacitor in a predetermined area including the groove. (d) forming an oxide film on the ends of the first conductive thin film exposed by the patterning; (e) Thereafter, a step of forming a contact diffusion layer on the substrate portion of the active region immediately next to the trench; (f) After that,
At the same time in the oxide film forming step, the oxide film formed on the surface of the active region substrate other than the groove is removed immediately next to the groove by utilizing the difference in thickness from the oxide film at the end of the first conductive thin film. (g) After that, a second conductive thin film is formed on the entire surface including the inside of the groove, and a dielectric layer is formed on the surface of the second conductive thin film. (h) growing the film and further forming a third conductive thin film thereon;
By sequentially patterning the conductive thin film, the dielectric film, and the second conductive thin film using the same mask, they are applied to the second cell plate of the capacitor, the second conductive thin film, and the second conductive thin film in a predetermined area including the groove portion and the contact portion. (i) After that, the second conductive thin film serving as the storage electrode is left as the second dielectric film and the storage electrode, and the end portion of the second conductive thin film as the storage electrode is connected to the contact diffusion layer. A method of manufacturing a semiconductor memory device, comprising the step of connecting one of the drain diffusion layers to the contact diffusion layer to form a transfer gate MOS type transistor.