JPH01276776A - Semiconductor device for detecting pattern and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable high-accuracy light beam position detection to be made and light pattern to be detected by placing and forming a plurality of semiconductor elements for detecting position in a short fence shape and by constituting one device. CONSTITUTION:An n-type layer 22 is subject to crystal growth on the surface of a p-type semiconductor substrate 21 and a plurality of high concentration p<+> areas 24 in long frame shape reaching the surface of the substrate 21 for the layer 22 are provided and divided. A plurality of short fence shaped p-type layers 23 are formed at each area of surface of an n-type layer 22. Then, a pair of electrodes 25 and 26 are formed at two short sides which oppose each other on the surface of each p-type layer 25, Then, they are divided into each device by mechanical or chemical treatment at the part of the p<+> area 24.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device for pattern detection, which detects a pattern of an object to be inspected, etc., by an incident light beam irradiated onto the surface of a semiconductor element, and a method for manufacturing the same. It is.

[Conventional technology] Semiconductor beam position detection element (hereinafter referred to as P, S, D).

：Po5ition 5sensitive Dete
A semiconductor sensor (referred to as a semiconductor sensor) is a type of semiconductor sensor whose main function is to detect the position of an incident beam irradiated onto the surface of a semiconductor element.

The principle of light beam position detection using P, S, and D is the "Lateral Photo Effect" on the semiconductor surface.
The outline of the method is as follows.

In other words, a current is generated in the semiconductor device by the energy of light incident on the device, and when this current flows toward at least two electrodes provided at the end of the device with the same polarity, , the magnitude of the current is determined in inverse proportion to the distance to the electrode, so if we measure the magnitude of the generated photocurrent at each electrode separately and perform a simple calculation, we get:
The position of the incident light beam can be known.

Solid-state imaging devices such as CCDs and MO3 type image sensors, which are familiar to video cameras, have been conventionally used for the purpose of determining the position of an incident light beam. However, these devices use detection elements (pixels) from tens to hundreds of blades.
and sequentially scan it to extract the signal, ■The signal readout circuit is complex, ■The detection speed is determined by the scanning speed (frame time) and higher time resolution cannot be obtained, ■There is a dead area between pixels. ■Determined by positional resolution or pixel size. There are other problems.

In addition, manufacturing is difficult because complex signal processing circuits, tens of blades, and millions of pixels are usually formed on the same chip.
Variations in element characteristics between chips are making it difficult to provide a stable supply of spare parts in application fields with strict product specifications.

On the other hand, P, S, and D methods detect the position of the irradiated light using a single detection element without scanning, and have become widely used in recent years.

FIG. 4(a) is a plan view for explaining conventional P, S, and D, and FIG. 4(b) is a sectional view taken along line BB in FIG. 4(a).

In FIG. 4, the first
A square 3 portion of the p-type layer 2 is formed on the surface, and this square 3
is the light-receiving surface, and the opposite ends of the P-shaped square 3 are
A highly concentrated P+ region 4.5 is formed along the sides, and a metal electrode 7.8 is provided on the surface of the P+ region 4.5 to serve as an output electrode.
At least p of the first surface consisting of squares 3 other than this electrode
A transparent insulating layer 6 is formed at the -n junction. Then, an n0 layer 9 is formed on the back side of the first surface of the n-type semiconductor wafer l, and an electrode 10 is provided on a part of this n0 layer 9.

Therefore, the two sides of p-type square 3 without electrodes 11.1
Since a p-n junction surface is formed in 2, assuming that the specific resistance outside the square 3 is virtually infinite, the photocurrent due to the received light exceeds 11.12, and the current flows to the outside n region. It doesn't flow. Since the pn junction appearing on the first surface is protected by the transparent insulating layer 6, no leakage current occurs.

As a result, P, S, and D in FIGS. 4(a) and (b).

The center of the light-receiving surface is the origin O, and the two sides 11.1 without electrodes
2, the Y axis is parallel to electrode 7.8, and the distance between electrodes 7 and 8 is 2L, then point Q (x,
When point-shaped light is incident on y), does it flow to each electrode 7.8? ft style 1. ．． I, is I, +l, = I.

Then, I? =IO(1-X/L)/2Ie=To(1+x/L)/
It becomes 2.

16-17=Io” x/L X = L (Ia - 1t) / I.

Therefore, the position coordinate X can be found from x=L(Ill-I7)/(ha+t7).

In addition, P, S, and D in FIG. 4 are obtained by providing electrodes on the n3 layer 9 of the n-type semiconductor wafer 1 on two opposing sides different from the sides of the electrodes 7.8, and determining the y coordinates. It can be used as a two-dimensional optical position detector.

[Problems to be Solved by the Invention] Conventional position detection semiconductor devices such as P, S, and D described above suffer from defects in semiconductor crystals, damage caused by thermal cycles during the manufacturing process, and the presence of impurities (contaminants). There were problems such as leakage currents occurring due to crystal defects, etc., and defects in the crystal making it impossible to form a uniform resistance layer, making it impossible to detect the light beam with sufficiently high precision. .

Further, although conventional devices can detect the position of spot light from an object to be inspected, there is a problem in that when light having a linear or other shape is incident, only the position of the center of the light can be detected.

This invention was made in order to solve such conventional problems, and is a pattern detection device that can detect a light beam position with high precision by laminating high-quality semiconductor crystals, and can also detect a light pattern. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same.

[Means for Solving the Problems] In order to achieve the above object, a semiconductor device for pattern detection of the present invention includes a plurality of semiconductor elements for position detection that are capable of highly accurate position detection formed in a strip shape. It is a device that is arranged to form one device, and a method for manufacturing the same.

[Function] According to the present invention, highly accurate pattern detection can be performed without scanning, and there is no need to provide electrodes in one axial direction by simply arranging the strip-shaped elements side by side.

[Embodiment] FIG. 1(a) is a perspective view showing an embodiment of a semiconductor element which is a component of the semiconductor device for pattern detection of the present invention, and FIG. 1(b) is a perspective view showing the line in FIG. 1(a). It is a sectional view taken along AA.

In FIGS. 1(a) and (b), 21 is a p-type semiconductor substrate, 22 is an n-type layer laminated on this p-type semiconductor substrate 21, and 23 is a p-type layer formed in this n-type layer 22. mold layer, 24
is a highly doped p0 region provided around the n-type layer 22;
5.26 is a pair of electrodes that are in contact with the p-type layer 23 provided at the end portion of the surface (second surface) of the p-type layer 23, and 27 is a ground electrode.

Next, a method for manufacturing the pattern detection semiconductor device shown in FIGS. 1(a) and 1(b) will be described.

First, an n-type layer 22 having a thickness of IOH, for example, is formed by epitaxial growth on the first surface (surface) of a p-type semiconductor substrate 21 made of S. A plurality of high-concentration p+ regions 24 are provided and divided into at least one elongated frame shape by a diffusion method, reaching the first surface of the p-type semiconductor substrate 21.
A width of 50 mm is formed by ion implantation or thermal diffusion into each portion of the second surface of the n-type layer 22 divided into four regions.
A plurality of rectangular p-type layers 23 each having a length of 0 μ-9 and a length of 7 sl are formed. Next, the second layer of each of these rectangular p-type layers 23 is
A pair of electrodes 25 and 26 that contact the rectangular p-type layer 23 are formed on two short sides facing each other on the surface. Thereafter, the p''-region 24 is divided into individual devices by mechanical processing using a saw or the like or chemical processing such as etching.

FIG. 2(a) is a perspective view showing one element of the present invention;
b) Each of the divided rectangular elements weighs 20g.
FIG. 2 is a plan view of a semiconductor device for pattern detection according to the present invention, which is configured by combining 16 semiconductor devices at intervals of m.

FIG. 3 is a schematic explanatory diagram of a semiconductor device for pattern detection when detecting a pattern of a test object using curved incident light from the test object according to the present invention, where 30 is a semiconductor device for pattern detection, and 31 is a laser. A light source, 32, 34 a lens that is an optical system, 33 an object to be inspected, 35 a signal processing circuit that processes electrical signals from the pattern detection semiconductor device 30, 36
is a display device, and 37 is a calculation result from the signal processing circuit 35.

In FIGS. 1 to 3, a pattern detection semiconductor device 3
By applying a reverse bias voltage to the p-type layer 23 and n-type layer 22 at 0, that is, applying a negative voltage to the p-type layer 23 and a positive voltage to the n-type layer 22, the surface (second surface) of the P-type layer 23 is applied. When light corresponding to the pattern of the test object 33 is irradiated from the laser light source 31 through the lens 32 and through the lens 34, a photocurrent flows through the depletion layer of each pn junction in the pattern detection semiconductor device 30.

Now, assuming that the distance between the electrodes 25 and 26 is 2L, when a point of light is incident on the point Q' (x,) on the light-receiving surface of the L element, a photocurrent flows through the depletion layer of the p-n junction. is p-type layer 23
reach each electrode 25.26. If Io=Izs+I2a is the current I2S+I2M flowing through the electrodes 25 and 26, then I211=IO(L XI )/2LII26=IO
(L+Xl)/2L, so xs = L (I2S-1tg) / (I2S+I
26), the coordinates X of point Q' can be found.

Similarly, each of the other elements x2. x3. ...X16 is obtained, a curve connecting them is obtained, and the signal processing circuit 35
is calculated and displayed on the display device 36.

In the manner described above, the curve of the light-receiving surface is determined, and the pattern of the object to be inspected can thereby be detected.

In addition, at this time, the ground electrode 27 was drawn out from the back surface of the p-type semiconductor substrate 21, or the ground electrode 27 was drawn out from the second surface (
If you decide to pull it out from the surface).

The lead wires of each electrode can be taken out from the same direction.

Although a signal processing circuit that processes the signal current obtained from each electrode is not shown, known processing such as converting the output current obtained from each electrode into voltage, calculating and detecting the output, etc. How can it be done?

Fig. 5 is a characteristic diagram of the pattern detection device of this embodiment shown in Figs. It is a characteristic curve showing the pattern detection performance showing the detection position of the element.

As is clear from FIG. 5, according to this embodiment, the center position of the light-receiving surface exhibits a nearly linear state with high accuracy, and the error range is approximately 0.1% to several percent.

Further, in the above embodiment, the semiconductor substrate 21 made of S was used as the substrate, but the semiconductor substrate 21 made of S, G, G, A, etc. was used as the substrate.

Inp, CMT (CD, H8, Te), amorphous silicon, or the like may be used, and in particular, when G or A is used, there is an advantage that leakage current to the substrate is small. It is also possible to use an n-type semiconductor substrate instead of a p-type semiconductor substrate, and if an n-type semiconductor substrate is used, the position detection semiconductor device is not a pnp device as in the above embodiment. , -npn, and an n3 region may be formed in place of the p+ region 24, which is a peripheral isolation region.

Furthermore, it is possible to use an insulating substrate such as sapphire instead of the semiconductor substrate 21. However, when an insulating substrate is used, it must be possible to laminate high-quality semiconductor crystals on the insulating substrate by epitaxial growth.

When an insulating substrate is used, since the substrate itself is not a conductive layer, there is an advantage that there is no leakage current to the substrate.

FIG. 6(a) shows pattern detection when a pin-type semiconductor device is used as another example, and FIG. 6(b) shows pattern detection when an insulating substrate is used instead of the semiconductor substrate in FIG. 6(a). 1 is a diagram schematically showing the configuration of one element of a semiconductor device for use in the semiconductor device;

In FIG. 6(a), an n-type 6
A plurality of buried layers 63 are formed by epitaxial growth on the first surface of a p-type semiconductor substrate in which a plurality of n-type layers are buried. Next, a p-type semiconductor substrate 61
A plurality of high concentration p9 regions 65 extending from the tJS1 surface at the peripheral edge of the layer 63 to the second surface of the layer 63 are provided and divided, and a plurality of high concentration P0 regions 65 are divided into A high concentration n3 region 66 extending from the peripheral end of the second surface of the layer 63 to the n-type layer embedded in the substrate is formed by thermal diffusion, and surrounded by this high concentration n0 region 66. A plurality of rectangular p-type layers 64 are formed in each region of the second surface of each layer 63 by ion implantation or thermal diffusion. Next, a pair of electrodes 67 and 68 that contact the rectangular p-type layer 64 are formed on the two opposing short sides of the second surface of each of the rectangular p-type layers 64, respectively.

Thereafter, the high concentration p9 region 65 is divided into each device by mechanical processing using a saw or the like or chemical processing such as etching.

Further, in FIG. 6(b), an n-type layer 62' is attached to the surface of an insulating substrate 61', and an i-layer 63' is formed on the tjS1 surface of this n-type layer 62' by epitaxial growth. Then, a high-concentration leakage region 65' reaching the n-type layer 62' from the peripheral end of the second surface of this i layer 63' is formed by ion implantation, and the i layer surrounded by this n-type region 65' is layer 63
A rectangular p-type layer 64' is formed in the region of the second surface of the rectangular p-type layer 64' by ion implantation or thermal diffusion.
A pair of electrodes 66' and 67' are provided on the second surface (surface) of 4'.
(not shown).

Sixteen elements formed as shown in FIGS. 6(a) and 6(b) are arranged in parallel to form a semiconductor device for pattern detection as shown in FIG. 2(b).

Then, by applying a reverse bias voltage to the pin junction surface of the pattern detection semiconductor device configured in this way,
The light incident on the p-type layer 64 or 64', which is the light-receiving surface, is converted into electrical energy and generated as a current at each electrode 67, 68.
(not shown) or 67', 6B' for pattern detection and that nip may be used instead of pin, as in the previous embodiment.

In addition, in the above embodiment, the p◆ viewing area 24, which is a separation region, was provided once, but by providing it twice or more to the extent that the light-receiving surface (the p-type layer 23 in the embodiment) does not become narrow, each device can be etched or By machining, it can be avoided from the effects of cracks and crazing during separation.

In addition, since this highly doped p0 region or n1 region has the same conductivity type as the substrate, the upper surface of this highly doped region (second
There is no need to provide an electrode on the back side of the substrate since the third electrode can be taken out from the other side.

Note that the axial orientation of the semiconductor substrate is not specified, and the semiconductor substrate may be formed by being pulled up using a seed crystal by the CZ (Czochralski) method, or by uniformly doping impurities into the crystal by the FZ (floating zone) method.

Moreover, the epitaxial growth of this invention is based on molecular beam epitaxial growth, or CV D (Che+5ical
A high-quality crystal layer is formed by vapor deposition. As a result, unlike resistive films such as amorphous silicon, a p-n junction made of high-quality semiconductor crystal is used as a resistive layer, which converts incident light into photocurrent, allowing for highly accurate position detection. can be done.

[Effects of the Invention] By having the configuration as explained above, the semiconductor device for pattern detection of the present invention detects light directly on the element surface, so a continuous position signal can be obtained, and the position resolution is high and the response speed is high. is fast.

In addition, the structure is simple, so the manufacturing method is simple, the surrounding signal processing circuit is also simple, pattern detection accuracy is not affected by changes in light intensity, and light beams in a wide wavelength range from X-rays to near-infrared rays can be used. It is possible to detect not only point-like light positions but also two-dimensional patterns without scanning, and precise positioning with respect to the object to be inspected is not required.

[Brief explanation of the drawing]

FIG. 1(a) is a perspective view showing an embodiment of one semiconductor element which is a component of the semiconductor device for pattern detection of the present invention;
FIG. 2(b) is a cross-sectional view taken along line A-A in FIG. 2(a), FIG. 2(a) is a perspective view showing this divided L element, and FIG. Each element is 20
FIG. 3 is a plan view of a semiconductor device for pattern detection of the present invention configured by combining 16 semiconductor devices at intervals of Bi*, which detects a pattern of a test object using curved incident light from the test object according to the present invention. 4(a) is a plan view for explaining conventional P, S, and D, and FIG. 4(b) is a line taken along B-B in FIG. 5 is a characteristic diagram of the pattern detection device of this embodiment shown in FIGS. 1, 2, and 3. FIG. 6(a) is a cross-sectional view of another embodiment using a pin type semiconductor device. In this case, FIG. 5B is a diagram schematically showing the configuration of one element of each pattern detection semiconductor device when an insulating substrate is used in place of the semiconductor substrate in FIG. In the figure. 2: Semiconductor substrate 22: N-type layer 23: P-type layer 24: p'' region 25.26: Electrode agent Patent attorney 1) Haru Kitatake Figure 1 (G) (b) Figure 2 Figure 3 (a) ) (b) Figure 4

Claims (8)

[Claims] (1) First conductivity type semiconductor substrate 21 having a grounding electrode
, a second conductivity type layer 22 formed on the upper surface (first surface) of this first conductivity type semiconductor substrate 21 , and this second conductivity type layer 22
A rectangular first conductivity type layer 23 formed in the center region of the upper surface (second surface) and a region reaching from the first surface to the second surface at the peripheral end of the second conductivity type layer 22. A first conductivity type region 24 of at least one circumference is provided, and a first conductivity type region 24 of the rectangular first conductivity type layer 23 is provided on two mutually opposing short sides on the second surface of the rectangular first conductivity type layer 23. For pattern detection, characterized in that a plurality of rectangular semiconductor elements each consisting of a pair of electrodes 25 and 26 that are in contact with one conductivity type layer 23 are arranged so that their long sides are in contact with each other. Semiconductor equipment. (2) Insulating substrate and the top surface (first surface) of this insulating substrate
a first conductivity type layer 22 of a semiconductor formed in the first conductivity type layer 22; a rectangular first conductivity type layer 23 formed in the central region of the upper surface (second surface) of the first conductivity type layer 22; a first conductivity type region 24 of at least one rotation provided in a region extending from the first surface to the second surface of the peripheral end of the mold layer 22; A plurality of rectangular semiconductor elements each having a pair of electrodes 25 and 26 provided on two opposing short sides on the second surface and in contact with the rectangular first conductivity type layer 23 are connected to each other. A semiconductor device for pattern detection, characterized in that the semiconductor devices are arranged so that their long sides are in contact with each other. (3) First conductivity type semiconductor substrate 61 having a grounding electrode
, a second conductivity type layer 62 embedded in the upper surface (first surface) of the first conductivity type semiconductor substrate 61 , and the first conductivity type layer 62 of the first conductivity type semiconductor substrate 61 and the second conductivity type layer 62 . an intrinsic semiconductor layer 63 formed above, a rectangular first conductivity type layer 64 formed at the center of this intrinsic semiconductor layer 63, and the first conductivity type layer 64 formed at the peripheral end of the first conductivity type semiconductor substrate 61. A first conductivity type region 65 of at least one circumference provided in a region reaching the upper surface (second surface) of the intrinsic semiconductor layer 63 from the surface thereof, and a first conductivity type region 65 embedded in the first conductivity type semiconductor substrate 61. a high concentration second conductivity type region 66 provided in a region extending from the peripheral edge of the upper surface (first surface) of the conductivity type layer 62 to the second surface of the intrinsic semiconductor layer 63; 2 facing each other on the upper surface (second surface) of the first conductivity type layer 64
A plurality of rectangular semiconductor elements each consisting of a pair of electrodes 67 and 68 provided on one short side and in contact with the rectangular first conductivity type layer 64 are arranged so that their long sides are in contact with each other. A semiconductor device for pattern detection, characterized in that it is configured by: (4) An insulating substrate 61', a first conductivity type layer 62' of a semiconductor laminated on the surface of this insulating substrate 61', and an upper surface (first surface) of this first conductivity type layer 62'. The formed intrinsic semiconductor layer 63', the rectangular first conductivity type layer 64' formed in the center of this intrinsic semiconductor layer 63', and the periphery of the first surface of the second conductivity type layer 62'. A first conductivity type region 65' provided in a region extending from the end to the upper surface (second surface) of the intrinsic semiconductor layer 63' and an upper surface (second surface) of the rectangular first conductivity type layer 64'. This rectangular first conductivity type layer 64 is provided on two short sides facing each other in
A semiconductor device for pattern detection, characterized in that a plurality of rectangular semiconductor elements each having a pair of electrodes 66' and 67' in contact with each other are arranged so that their long sides touch each other. . (5) A second conductivity type layer 22 is formed on the upper surface (first surface) of the first conductivity type semiconductor substrate 21 by epitaxial crystal growth, and a part of this second conductivity type layer 22 is formed by a thermal diffusion method. , the first conductivity type semiconductor substrate 21 is divided by providing a plurality of first conductivity type regions 24 in the shape of at least one long frame reaching the first surface, and the first conductivity type semiconductor substrate 21 is divided into a plurality of first conductivity type regions 24. A plurality of rectangular first conductivity type layers 23 are formed in each region of the upper surface (second surface) of the second conductivity type layer 22 in each region by ion implantation or thermal diffusion. A pair of electrodes 25 and 26 are formed on two opposing short sides of the second surface of the conductivity type layer 23 to contact each of the rectangular first conductivity type layers 23, respectively. A method of manufacturing a semiconductor device for pattern detection. (6) A first conductivity type layer 22 of a semiconductor is formed by epitaxial growth on the surface of an insulating substrate, and this second conductivity type layer 2
A part of 2 is removed from the upper surface (first surface) of the substrate by thermal diffusion method.
The upper surface (second surface) of the first conductivity type layer 22 of the plurality of regions divided into the first conductivity type regions 24 is divided by providing a plurality of first conductivity type regions 24 each having a long frame shape reaching at least once. ), a plurality of rectangular first conductivity type layers 23 are formed by ion implantation or thermal diffusion, and these rectangular first conductivity type layers 23 are opposed to each other on the second surface. The first conductivity type layer 23 of each rectangular shape is provided on the two short sides.
A method of manufacturing a semiconductor device for pattern detection, characterized in that a pair of electrodes 25 and 26 are respectively formed in contact with the semiconductor device. (7) A plurality of buried layers of the first conductivity type layer 62 are formed on the upper surface (first surface) of the first conductivity type semiconductor substrate 61 by ion implantation or thermal diffusion method, and a plurality of buried layers of the second conductivity type layer 62 are formed on the upper surface (first surface) of the first conductivity type semiconductor substrate 61. An intrinsic semiconductor layer 63 is formed by epitaxial growth on the first surface of the first conductivity type semiconductor substrate 61 in which the semiconductor substrate 61 is embedded, and the intrinsic semiconductor layer 63 is formed from the first surface of the peripheral end of the first conductivity type semiconductor substrate 61. The layer 63 is divided by providing a plurality of first conductivity type regions 65 in the shape of at least one elongated frame reaching the upper surface (second surface), and the plurality of intrinsic semiconductor layers are divided into the first conductivity type regions 65. A first conductivity type region 66 extending from the peripheral end of the second surface of the substrate 63 to the first conductivity type layer 62 embedded in the substrate is formed by a thermal diffusion method. A plurality of rectangular first conductivity type layers 64 are formed by ion implantation or thermal diffusion in each region of the second surface of each intrinsic semiconductor layer 63 surrounded by . For pattern detection, a pair of electrodes 67 and 68 are formed on two opposing short sides of the second surface of the pattern layer 64, respectively, to contact each of the rectangular first conductivity type layers 64. A method for manufacturing a semiconductor device. (8) A semiconductor second conductivity type layer 62' is laminated on the surface of the insulating substrate 61', and the upper surface of this second conductivity type layer 62' (first
An intrinsic semiconductor layer 63' is formed by epitaxial growth on the upper surface (second surface) of the intrinsic semiconductor layer 63', and a second conductivity type region extends from the peripheral end of the upper surface (second surface) of the intrinsic semiconductor layer 63' to the first conductivity type layer 62'. 65' is formed by a thermal diffusion method, and a plurality of strips are formed by ion implantation or a thermal diffusion method into each region of the second surface of each intrinsic semiconductor layer 63' surrounded by the second conductivity type region 65'. A first conductivity type layer 64' is formed on each of the rectangular first conductivity type layers 64' on two opposing short sides of the second surface of each of the rectangular first conductivity type layers 64'. A method of manufacturing a semiconductor device for pattern detection, characterized in that a pair of electrodes 66' and 67' are formed in contact with each other.