JPH01276717A - Exposure of semiconductor - Google Patents

Abstract

PURPOSE:To avoid pattern thinning or pattern mismatching by enlarging a pattern width of one of an adjoining pair of regions and by extending a pattern length of the other region when a pattern is exposed after devided into a plurality of regions. CONSTITUTION:When exposing a pattern of a large area devided into a plurality of regions, the following procedures are applied; As for wiring patterns L1-l6 crossing over each of boundaries I-X-IV-X of devided regions A-D, a pattern width of at least one region is enlarged to form first margin patterns L1m-L6m. A pattern at the side of the other region is extended to the side of the former region by a fixed length to form second margin patterns L1l-L6l. Troubles such as pattern thinning and pattern mismatching can be avoided in this way even when matching errors of regions develop caused by moving accuracy of a stage.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor exposure method, the purpose is to divide a predetermined pattern into a plurality of regions with the aim of performing divided exposure of a large area pattern without causing pattern separation if the pattern becomes thin. In a semiconductor exposure method in which a predetermined pattern is transferred by repeating exposure for each region, for a pattern that crosses the boundary between a pair of adjacent regions, the width of the pattern on at least one region side is slightly enlarged.
forming a margin pattern, and extending a pattern on the other region side to one region side to form a second margin pattern, and including these first and second margin patterns in the predetermined pattern. It is configured to be transcribed.

[Industrial application field]

The present invention relates to a semiconductor exposure method for pattern transfer in a semiconductor manufacturing process.

In general, optical exposure technology that transfers a design pattern onto a wafer through a mask is divided into two types: a contact type in which the mask and wafer are exposed in close contact with each other, and a projection type in which the mask and wafer are exposed separately. Can be divided.

In the projection type, the photomask does not come into close contact with the wafer, so the photomask can be used semi-permanently, except for wear and tear due to handling, including cleaning.

[Conventional technology]

FIG. 3 is a schematic diagram of a reduction projection transfer apparatus used in a conventional semiconductor exposure method. In Fig. 3, 1 is a light source;
2 is a reticle on which a pattern is formed, 3 is an optical lens with a magnification of m (where m is 1), 4 is a wafer, and 5 is a stage.

The light transmitted through the reticle 2 is condensed by the optical lens 3 and formed into an image on the stage 5, which is reduced to m times the pattern size.

[Problem that the invention seeks to solve]

However, in such a conventional semiconductor exposure method, the light transmitted through the reticle 2 is focused by the optical lens 3 and formed into an image on the stage 5, so that the exposure size is smaller than that of the stage 5. This is uniquely determined by the lens aperture, and for example, it has been impossible to expose a chip with a large area exceeding the above exposure size. This poses a major manufacturing problem, such as the inability to adapt to the recent manufacturing of large-chip semiconductor devices, and has become an issue that must be resolved immediately.

The above problem can be solved to some extent by increasing the lens aperture of the stage 5, but there is a limit to increasing the lens aperture, and the increase in lens aberrations and lens periphery Although the aperture is made larger, it is not expected to have such an effect due to the reduction in resolution.

By the way, the most effective method is to move the stage 5 in steps in the X-axis and Y-axis directions and expose each part of the pattern separately, thereby ultimately transferring a large area of the pattern. However, this method has the following problems and has not yet been implemented. That is, in this method, the pattern is divided into a plurality of regions for divisional exposure, and the exposure is performed for each region. However, when moving from region to region, the accuracy of the drive mechanism for moving the stage 5, etc. Therefore, so-called alignment errors that occur between regions are unavoidable. As a result, there were problems such as the bonding surfaces of patterns that exceeded the boundaries of regions being shifted (pattern thinning) or not bonding (pattern separation), and could not be applied to exposure of large-area patterns.

The present invention was made in view of these problems, and
To provide a semiconductor exposure method capable of performing divided exposure of a pattern without causing pattern thinning or pattern separation even if a region alignment error occurs by devising a pattern shape near a region boundary. The purpose is to

[Means to solve the problem]

In order to achieve the above object, the present invention provides a semiconductor exposure method in which a predetermined pattern is divided into a plurality of regions, and exposure is repeated for each region to transfer the predetermined pattern. For patterns exceeding
forming a margin pattern, and extending a pattern on the other region side to one region side to form a second margin pattern, and including these first and second margin patterns in the predetermined pattern. It is configured to be transcribed.

[For production]

In the present invention, first and second margin patterns are formed near the boundaries of patterns that cross the boundaries of each region.

Therefore, even if an alignment error occurs between regions, as long as this error does not exceed the first and second margin patterns, pattern separation is avoided if the pattern becomes thinner, and divisional exposure of a large area pattern can be performed. .

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing an embodiment of the present invention, and FIG. 1 is a schematic diagram of an exposure apparatus thereof.

In FIG. 1, the reduction projection exposure apparatus includes a light source 1, a reticle (dry plate) 2 on which a pattern is formed, an optical lens 3 with a magnification of m (however, m<1), and a wafer 4 fixedly mounted on the upper surface. The stage 6 receives the driving force PX and the driving force P7 from the drive mechanism 7,
It can be moved freely in the Y-axis direction. In addition,
In the figure, F indicates the pattern of the reticle 2 imaged on the wafer 4 by the optical lens 3, and this pattern F is
This region corresponds to one of a plurality of regions into which a predetermined pattern is finally transferred onto the wafer 4.

FIG. 2 is an enlarged view showing a pattern near the boundaries of arbitrary four areas A to D among the plurality of divided areas. In FIG. 2, L+, Lx cross the boundary I-X and area A,
The wiring pattern arranged between L3. L4 is boundary II
- Area A beyond X.

The wiring pattern arranged between 0 and L is the boundary] 111-
Wiring pattern arranged between areas C and D beyond X, L
6 is a wiring pattern extending beyond the boundary IV-X and disposed between 8.

For wiring patterns that touch the border between the left side and the bottom side of each area, the pattern width is slightly expanded (for example, by 1 part of the pattern width).
．． 25 times), and the enlarged portions form the first margin patterns L1 to L6m.

In addition, the wiring pattern in contact with the boundary between the right side and the top side of each area extends to the adjacent area by a predetermined length l, and the extended portion forms the second margin pattern L1f-L, 6. ing.

Next, the effect will be explained.

The first and second wiring patterns that extend beyond the boundaries of the area are
The pattern data in which the margin pattern is formed is created by, for example, a CAD system.

Then, a reticle 2 is manufactured according to this pattern data, and the reticle 2 is mounted on a reduction projection type exposure apparatus shown in FIG. The reduction projection type exposure apparatus focuses the light from the light source 1 that has passed through the reticle 2 using the optical lens 3, forms an image on the wafer 4, and performs the first transfer of the area A. Then 2
The stage 6 is moved to perform the second transfer of area B. At this time, if an area alignment error due to the movement accuracy of the stage 6 occurs, for example, in the direction of the arrow indicated by Z in the figure, the area B side will be , L2 are transferred to the wafer W with a shift in the Z direction by an alignment error from L+ and Lz of the area A that has already been transferred onto the wafer W.

However, since the first margin pattern Ll1m+LZII is formed in the wiring patterns L, , L on the area B side, the alignment error is caused by this first margin pattern L.
As long as the width does not exceed the width of llI+Lem, pattern separation will not occur if the pattern becomes thinner at the joint surface of the wiring patterns LL and Lz on the area A side and the area B side.

Also, due to the alignment error in the Z direction, the area B moves away from the area, and the wiring pattern L6 tries to move away from the boundary ■-X, but the second margin patterns L, f and the first margin pattern Lu1l are overlapped by a predetermined length 2, so as long as the alignment error does not exceed the predetermined length l, the wiring pattern L6 will not be separated.

In this way, according to this embodiment, the area A-
Wiring pattern L exceeding each boundary 1-X to IV-X of D,
~L6, expanding the pattern width on at least one region side to form first margin patterns L1~L,
Furthermore, the pattern on the other region side is extended to the one region side by a predetermined length to form a second margin pattern L+f.
1. Even if a region alignment error occurs due to the movement accuracy of the stage 6, this alignment error will cause the first margin pattern Lllll to Lhl to be formed.
width o of ha and second margin pattern L, f to L, f
Predetermined length! As long as the pattern is not exceeded, it is possible to avoid problems such as patterns becoming thinner or separated from each other. Therefore, a large-area pattern can be subjected to divided exposure, and it is possible to meet the recent demands for manufacturing large-chip semiconductor devices.

In addition, in this embodiment, the first region is placed on one side of the boundary.
Although the first margin pattern is provided, the first margin pattern is not limited to this, and the first margin pattern may be provided on both region sides.

Further, the second margin pattern extending from the other region side to the one region side may also extend to both sides, or the first margin pattern may be provided to both sides, and
This first margin pattern may be extended to also have the function of a second margin pattern.

Furthermore, in this embodiment, the pattern that crosses the boundary is used as a wiring pattern; however, it is not limited to this, and other semiconductor patterns,
Of course, it may be a resistance pattern.

Further, in this embodiment, the number of regions is four, A to D, but it goes without saying that the number is not limited to this number. Further, in this embodiment, wafer exposure is used as an example, but other materials other than wafers may be used as long as exposure is repeated for each region to finally obtain a large-area transfer pattern.

〔Effect of the invention〕

According to the present invention, the pattern width of at least one region of a pair of bordering adjacent regions is slightly expanded, and the pattern of the other region is extended to extend toward the one region. Therefore, even if a 35-region alignment error occurs, as long as the error does not exceed the enlarged width of the pattern or the extended bone, pattern separation can be avoided if the pattern becomes thinner.

Therefore, it becomes possible to carry out divided exposure of a large area pattern, and it is possible to realize a semiconductor exposure method that meets the recent demands for manufacturing large-chip semiconductor devices.

[Brief Description of the Drawings] Fig. 1 is a schematic diagram of an exposure apparatus used in an embodiment of the present invention, and Fig. 2 is a pattern diagram of the main part near the boundary of the area showing an embodiment of the present invention. FIG. 3 is a schematic diagram of an exposure apparatus used in a conventional semiconductor exposure method. A-D...area, 1-X~IV-X...boundary, L1~Lb...wiring pattern, L Ill~L
6m...First margin pattern, L, f-L
, f... Second margin pattern. The present invention - Musume 4 da f 11; Meisetsu in the name 3 to use! 0
Throwing Yuin Figure 1

Claims (1)

[Claims] In a semiconductor exposure method in which a predetermined pattern is divided into a plurality of regions and exposure is repeated for each region to transfer the predetermined pattern, at least The pattern width on one area side is slightly expanded to form a first margin pattern, and the pattern on the other area side is extended to one area side to form a second margin pattern.
A method for exposing a semiconductor, comprising: forming a margin pattern, and transferring the first and second margin patterns while being included in the predetermined pattern.