JPH01276636A - Light input integrated circuit - Google Patents

Light input integrated circuit

Info

Publication number
JPH01276636A
JPH01276636A JP63106967A JP10696788A JPH01276636A JP H01276636 A JPH01276636 A JP H01276636A JP 63106967 A JP63106967 A JP 63106967A JP 10696788 A JP10696788 A JP 10696788A JP H01276636 A JPH01276636 A JP H01276636A
Authority
JP
Japan
Prior art keywords
light
bonding pad
metal layer
intercepted
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63106967A
Other languages
Japanese (ja)
Inventor
Noriyasu Oonishi
徳靖 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63106967A priority Critical patent/JPH01276636A/en
Publication of JPH01276636A publication Critical patent/JPH01276636A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor device with few erroneous operations due to external rays of light at a low cost, by providing a metallic layer to a bonding pad so that the leakage of light from the periphery of the bonding pad is intercepted. CONSTITUTION:The third metallic layer 10 is formed on a bonding pad 2 as well as on an insulating layer 5 for protection so that a part which is not intercepted by a metallic layer 6 for shielding the light can be intercepted. Since a light having the direction almost horizontal is intercepted by the third metallic layer 10 from a vertical direction with respect to the chip surface of an external light 8, the circuit operation of this device is not affected by the external light and no erroneous operations are induced by the external light. Further, the components which intercept the light at the outside can be omitted; besides, the need for separating the bonding pad from a circuit part is eliminated as well and thus a compact chip size is obtained at a low cost.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は光が入射する位置に！！袈された光入力集積
回路に関し、特に外部接続９１子（以下、ボンディング
パッドという）の構造に関するものである。[Detailed Description of the Invention] [Industrial Field of Application] This invention is applicable to the position where light enters! ! The present invention relates to a capped optical input integrated circuit, and particularly to the structure of an external connection 91 (hereinafter referred to as a bonding pad).

〔従来の技術〕[Conventional technology]

第２図は従来の光が入射する位置に実装され−た光入力
集積回路のボンディングパッド周辺の断面図である。FIG. 2 is a sectional view of the vicinity of a bonding pad of a conventional optical input integrated circuit mounted at a position where light is incident.

図において、（１）は半導体チップの接地電位拡散層、
（２）は接続用金属端子（ボンディングパッド）、（３
）はボンディングパッド（２）に接続された接続線（以
下ワイヤという）　、＋４）は半導体チップと配線用金
属層（図示していない）又はボンディングパッド（２）
層を絶縁する絶縁層、（５）は配線用金属層又はボンデ
ィングパッド（２）又は絶縁層（４）上の絶縁膜、（６
）は絶縁膜（５）上の遮光用金属層、（７）はボンディ
ングパッド（２）と遮光用金属層（６）のすきま、（８
）はすきま（７）に入射する光線、（９）は遮光用金４
層（６）上の保護絶１Ｌα１）は絶縁層（４）下の牛尋
体部分である。In the figure, (1) is the ground potential diffusion layer of the semiconductor chip;
(2) is a metal terminal for connection (bonding pad), (3
) is the connection wire (hereinafter referred to as wire) connected to the bonding pad (2), +4) is the semiconductor chip and the metal layer for wiring (not shown) or the bonding pad (2)
An insulating layer for insulating the layers, (5) is an insulating film on a metal layer for wiring or a bonding pad (2) or an insulating layer (4), (6)
) is the light-shielding metal layer on the insulating film (5), (7) is the gap between the bonding pad (2) and the light-shielding metal layer (6), (8
) is the light beam incident on the gap (7), (9) is the light shielding metal 4
The protective layer 1Lα1) on the layer (6) is the cow's body part under the insulating layer (4).

従来のものは金属層（６）によって半導体チップの大部
分を遮光することにより、外部光による素子の誤動作を
防いでいた。In the conventional semiconductor device, most of the semiconductor chip is shielded from light by a metal layer (6), thereby preventing the device from malfunctioning due to external light.

ただし１、金属層（６）のすきｆ（７）より半導体チッ
プ内に入射した光のエネルギーは近くのｐ　−ｎ接合な
どで電流に変換され、回路の各部分に外部光線による余
分な電流が入力されていた。However, 1. The energy of the light that enters the semiconductor chip through the gap f (7) in the metal layer (6) is converted into current at a nearby p-n junction, etc., and excess current due to external light is generated in each part of the circuit. It was entered.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の光入力集積回路のボンディングパッド部周辺は以
上のように構成されていたので、ボンデイングパツド周
辺に金属層のすきまができ、そこに外部光線が入射する
と誤動作する可能性があるため、光入力集積回路を外部
の別のケースに入れて外部光線を遮光するなどの対策を
せねばならず装置が高価になるばかシでなく、ボンディ
ングパッドと回路部をある程度離さなければならなかっ
たため、チップサイズが大きくなってしまうという課題
があった。Since the area around the bonding pad of a conventional optical input integrated circuit is configured as described above, there is a gap in the metal layer around the bonding pad, and if external light enters there, there is a possibility of malfunction. Rather than having to take measures such as placing the input integrated circuit in a separate external case to block external light, which would make the device more expensive, the chip There was a problem with the large size.

この発明は上記のよ５な課電を解消するため釦なされた
もので、外部光線の遮光が光入力集積回路単体で行うこ
とができ、外部で遮光をするためのケースなどの部品を
省略でさるとともに、ボンディングパッドと回路部を離
す必要のない安価で小型なチップサイズの小さい光入力
集積回路を得ることを目的とする。This invention was developed to eliminate the above-mentioned 5 types of electrification, and it is possible to block external light by using a single optical input integrated circuit, and it is possible to omit parts such as a case for external light blocking. Another object of the present invention is to obtain an optical input integrated circuit that is inexpensive, small in size, and has a small chip size without requiring a separation between a bonding pad and a circuit section.

〔課題’ｆＬ４決するだめの手段〕 この発明に係る光入力集積回路は遮光用金属層で遮光で
きない部分をボンディングパッド上ならびに保護用絶縁
層上に第３金属層を形成したものである。[Means for resolving problem 'fL4] In the optical input integrated circuit according to the present invention, a third metal layer is formed on the bonding pad and on the protective insulating layer in the areas where light cannot be blocked by the light-shielding metal layer.

〔作用〕[Effect]

この発明における光入力集積回路は第３金属層により外
部光線、チップ面に対して垂直な方向はもちろんとシわ
け水平に近い方向の光線を逍ぎるので、外部の光の影響
が回路動作に影響せず、外部の光によって誤動作しない
。In the optical input integrated circuit of this invention, the third metal layer emits external light, not only in a direction perpendicular to the chip surface but also in a direction close to horizontal, so the influence of external light affects the circuit operation. and will not malfunction due to external light.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図において、（１）は半導体チップの接地電位拡牧層、
（２）はボンディングパッド、（３）はワイヤ、（４）
は絶縁層、（５）は絶縁膜、（６）は遮光用金属層、（
８）は外部光線、（９）は保護用絶縁膜、Ｑｌは第３金
属層、■は絶縁層（４）下の早沸体部分である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is the ground potential spreading layer of the semiconductor chip;
(2) is a bonding pad, (3) is a wire, (4)
is an insulating layer, (5) is an insulating film, (6) is a light-shielding metal layer, (
8) is an external light beam, (9) is a protective insulating film, Ql is a third metal layer, and ■ is an early boiler portion under the insulating layer (4).

この実施例によればボンディングパラ）’（２１ト遮光
用金属層（Ｇ）とのすきマ（７）より入射する外部光線
（８）の大部分を第３金属層（８）によって辿ぎること
かできるので、回路の各部分に余分な電流が入力される
ことがない。According to this embodiment, most of the external light rays (8) incident through the gap (7) between the bonding layer (G) and the light-shielding metal layer (G) can be traced through the third metal layer (8). Therefore, no extra current is input to each part of the circuit.

尚、特に半導体チップ（ロ）の一部分を光センサとして
使用したい場合はその部分のみ遮光用金属層（６）をな
くせば良い。In addition, especially when it is desired to use a part of the semiconductor chip (b) as an optical sensor, it is sufficient to eliminate the light-shielding metal layer (6) only in that part.

なお、上記実施例ではボンディングパッド（２）と遮光
用金属層（６）とのすきま（力に第３金属層（８）を設
けた場合を示したが、チップ内に光センサを有する場合
には、光センサ周辺部に第３金属層を設けることにより
、チップ面に対して水平に近い方向に入射する光線（８
）を遮ぎることかできる。In addition, in the above example, the case where the third metal layer (8) was provided in the gap between the bonding pad (2) and the light-shielding metal layer (6) was shown, but when the chip has an optical sensor, By providing a third metal layer around the optical sensor, the light rays (8
) can be blocked.

また、ボンディングパッド（２）や光センサ周辺部に限
らず、チップ面に対して、水平に近い方向の光線（８）
による誤動作が問題となる場合には、上記実施例と同様
の構造にすれば同一の効果を奏する。In addition, light rays (8) in a direction nearly horizontal to the chip surface are not limited to the bonding pad (2) and the surrounding area of the optical sensor.
If malfunction due to this problem becomes a problem, the same effect can be obtained by using a structure similar to that of the above embodiment.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、遮光用金属層で遮光で
きない部分の大部分を第３金属層で遮光できるように構
成したので、外部光線による誤動作の少ない安定な半導
体装置を安価に得られる効果がある。As described above, according to the present invention, most of the portions that cannot be blocked by the light-blocking metal layer can be blocked by the third metal layer, so a stable semiconductor device with less malfunction caused by external light can be obtained at a low cost. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例による光入力半導体装置を
示す断面図、第２図は従来の光入力半導体装置を示す断
面図である。 図において、（２）はボンディングパッド、（３）はワ
イヤ、（６）は遮光用金属層、（７）は金属層間のすき
ま、（８）は外部光線、（１１は第３金属層である。 なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a sectional view showing an optical input semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional optical input semiconductor device. In the figure, (2) is a bonding pad, (3) is a wire, (6) is a light-shielding metal layer, (7) is a gap between metal layers, (8) is an external light beam, and (11 is a third metal layer). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　半導体のチップに光が入射する位置に実装された光入
力集積回路において、ボンディングパッド周辺より漏れ
込む光を遮ぎるようにボンディングパッド上に金属層を
設けたことを特徴とする光入力集積回路。An optical input integrated circuit mounted on a semiconductor chip at a position where light is incident, characterized in that a metal layer is provided on a bonding pad so as to block light leaking from around the bonding pad.
JP63106967A 1988-04-27 1988-04-27 Light input integrated circuit Pending JPH01276636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63106967A JPH01276636A (en) 1988-04-27 1988-04-27 Light input integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63106967A JPH01276636A (en) 1988-04-27 1988-04-27 Light input integrated circuit

Publications (1)

Publication Number Publication Date
JPH01276636A true JPH01276636A (en) 1989-11-07

Family

ID=14447085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63106967A Pending JPH01276636A (en) 1988-04-27 1988-04-27 Light input integrated circuit

Country Status (1)

Country Link
JP (1) JPH01276636A (en)

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