JPH01274193A - Image processor - Google Patents

Abstract

PURPOSE:To speed up operation by reading out image data which are written previously when writing image data in two storage means used alternately for writing and displaying in order according to priority, and writing low- priority image data corresponding to data indicating transparency. CONSTITUTION:When image data are written, the image data which are written previously are read out through 1st terminals SO0-SO3 of means M1 and M2 equipped with 1st terminals SO0-SO3 for output and 2nd terminal D0-D3 for input and when read image data is image data indicating transparency, image data having low priority are written through the terminals D0-D3 of the storage means M1 and M2. Consequently, the image data are read out and written in parallel through the terminals SO0-SO3 and D0-D3 of the storage means M1 and M2, and image data having priority of display are encoded into a television signal of an image at a high speed according to the priority.

Description

[Detailed description of the invention] [Industrial use! I! F] The present invention relates to an image processing device for displaying a plurality of images each having a display priority according to the priority.

[Prior Art] Conventionally, there are the following two methods as image processing methods for displaying a plurality of moving images each having a display priority according to the priority.

The first image processing method uses video random access memory (hereinafter referred to as VR
It's called AM. ), and the image data for one frame is stored in a frame buffer memory.

With this method, when storing a video with a priority higher than 1 later, even if the image data of the previous video with a lower priority is stored in one address of the frame buffer memory, the previous image data Overwrite it on top of
That is, the image data of the previous moving image is deleted and the image data of the moving image with a higher priority to be stored later is stored.

The second image processing method is to store moving pictures in the frame buffer memory in order of priority, using a read-modify-write method. In this method, when storing a video with a lower priority later, the image data of the video stored at one address of the frame buffer memory to be stored is read out, and the priority of the image data is determined. Only when the priority of the previously stored image data is lower than the priority of the image data to be stored from now on, the image data to be stored from now on is stored at the address of the frame buffer memory.

[Problems to be Solved by the Invention] However, in the first image processing method described above, the number of videos to be displayed is large (if the number of videos to be displayed is large, the image data of all the videos to be displayed is There was a problem in that there were videos that could not be stored and displayed between the two.

In addition, the second image processing method requires not only writing time but also reading time, which is approximately twice as long as the first image processing method, and is similar to the first image processing method. However, there was a problem in that the number of videos that could be displayed was severely limited.

A first object of the present invention is to solve the above-mentioned problems, and to encode image data, each having its own priority, into an image television signal based on the priority at a higher speed than the conventional image processing method. The object of the present invention is to provide an image processing device that can perform the following tasks.

A second object of the present invention is to solve the above-mentioned problems and encode image data, each having its own priority, into an image television signal based on the priority at a higher speed than the conventional image processing method. An object of the present invention is to provide an image processing device that can display the image.

[Means for Solving the Problems] The present invention provides a first image data storage system that stores a plurality of image data, each of which has a display priority, consisting of data indicating transparency and data indicating the color or gradation of the image. storage means for storing the image data stored at the input address in response to the input address and the first control signal;
Image data output from the terminal and input from the second terminal is stored at the input address, and the image is stored at the input address in response to the input address and the second control signal. a second storage means for outputting data from the first terminal; and a first control signal when the data output from the first terminal of the second storage means is data indicating that the data is transparent. and determining means for outputting a second control signal when the data output from the first terminal of the second storage means is not data indicating that the image data is transparent; After sequentially reading the image data stored in the first storage means starting with the image data having the higher priority, the sequentially read image data and the addresses corresponding to the display positions of the read image data are sequentially read out from the second storage means. The address of the image data stored in the second storage means is output to the second storage means when reading the image data.
and an encoding means for encoding the image data outputted from the second storage means into a television signal when reading the image data.

Furthermore, the image processing apparatus is characterized in that it further includes display means for displaying an image of the television signal output from the encoding means.

[Operation] With the above configuration, the first storage means stores a plurality of images each including data indicating that the image is transparent and data indicating the color or gradation of the image, each having its own display priority. the second storage means outputs the image data stored at the input address from a first terminal in response to the input address and the first control signal; The image data input from the input address is stored at the input address, and the image data stored at the input address is output from the first terminal in response to the input address and a second control signal. . Next, the determination means outputs a first control signal when the data output from the first terminal of the second storage means is data indicating that the second storage means is transparent; A second control signal is output when the data output from the first terminal is not data indicating transparency. Furthermore, the control means sequentially reads the image data stored in the first storage means starting from the image data having a higher priority when writing the image data, and then reads out the image data stored in the first storage means sequentially from the image data that has been read sequentially and the read image data. Sequentially outputting addresses corresponding to display positions of the image data to the second storage means, and outputting addresses of the image data stored in the second storage means to the second storage means when reading the image data. After that, the encoding means encodes the image data outputted from the second storage means when reading the image data into a television signal.

As a result, it is possible to obtain a television signal of an image composed of a plurality of image data stored in the first storage means according to the display priority order.

Furthermore, by providing the display means, it is possible to display an image of the television signal output from the encoding means.

[Embodiment] FIG. 1 is a block diagram of an image processing apparatus that is an embodiment of the present invention.

The image processing apparatus of this embodiment includes two frame buffer memories Ml, each of which is a two-port random access memory (hereinafter referred to as a random access memory RAM) and is used alternately as a write memory and a display memory; M2, and as in the second image processing method, when writing image data, the image data is written in order from the image data having the highest priority.
The previously written image data at a certain address is read out, and only when 4-bit image data of "1111" indicating transparency is read out, an L level write signal is output to the frame buffer memory and the next write is executed. The feature is that it writes image data with a lower priority than the other image data.

In FIG. 1, a control device 1 is a circuit that controls each circuit of this image processing device, and this control device 1 stores, for example, 256 square moving image data of 8 dots vertically and 8 dots horizontally. A pre-stored read-only memory (hereinafter referred to as ROM) 2 and a signal generator 3 which generates a switching signal of frequency 60) (z) are connected. Image data per dot is 4-pit color data. The color data of "111 bits" indicates transparency, and the other color data indicates a predetermined color other than transparency.

As mentioned above, the frame buffer memories Ml and M2 are VRAMs that are called two-bottom RAMs and store color data for one frame, and have data input terminals Do to D3 for writing and data input terminals for reading. data output terminals S○0 to SO3, address input terminals AO to A7, and a write enable terminal WE.

The frame buffer memories M1 and M2 are alternately and repeatedly used as a write memory and a display memory based on a switching signal output from the signal generator 3. That is, when the switching signal is at the H level, the frame buffer memories Ml and M2 are respectively used as the writing memo 1 and the display memory, while when the switching signal is at the L level, the frame buffer memories Ml and M2 are used as the memory for displaying the memo 1 for writing.
are used as display memory and write memory, respectively. Furthermore, frame buffer memories Ml, M2
are each reset by the control device 1 before the moving image color data is stored, and as a result, data "1111" is stored in all addresses.

Based on the switching signal output from the signal generator 3, the control circuit 1 outputs a read control signal to the ROM 2, and then outputs address data to the ROM 2 to select the highest priority video to be displayed. The color data of the moving image with the highest priority is read out from the ROM 2, and the color data of the moving image with the next highest priority is read out from the ROM 2 in the same manner. The control circuit 1 outputs the 4-bit parallel color data of the moving image read from the ROM 2 to the write input terminals DO to D3 of the frame buffer memory Ml via the a side of the switch 10, and
Frame buffer memory M via the b side of the switch 10
It outputs to the write input terminals DO to D3 of No.2. Simultaneously with outputting this color data, the control circuit 1, based on the switching signal, writes 8-bit address data corresponding to the display position of the moving image to a frame buffer memory used as a writing memory. J M l also i1M
Output to address input terminal 2. Further, based on the switching signal, the control circuit 1 outputs 8-bit address data corresponding to the display position of the moving image to the address input terminal of the frame buffer memory M1 or M2 used as a display memory.

Readout output terminal S0 of frame buffer memory M1
0 to SO3 are connected to the a side of the 4-bit switch 13 and to the b side of the 4-bit switch 14. Also, a readout output terminal So of the frame buffer memory M2.

to SO3 are connected to the b side of the switch 13 and to the a side of the switch 14.

The 4 bits on the common side of the switch 13 are the Nant gate NΔ
Connected to the four input terminals of the ND, the Nant gate NAN
The output terminal of D is connected to the a side of switch 11 and the b side of switch 12. b side of switch 11 and switch 1
Both a sides of 2 are connected to an H level DC 74 source Vcc, which is, for example, +5V. The common side of the switch 11 is the write enable terminal W of the frame buffer memory Ml.
The common side of switch 12 is connected to write enable terminal WE of frame buffer memory M2. Here, the switches 10 to 14 are each switched to the a side when the switching signal output from the signal generator 3 is at H level, and are switched to the b side when the switching signal is at L level.

The 4-bit parallel color data output from the common side of the switch 14 is input to the television signal encoder 4. The television signal encoder 4 stores input 4-bit parallel color data for one frame in a ROM, and refers to a lookup table 5 in which color data and data related to the television signal corresponding to the color data are stored in advance, for example. N
After being encoded into a television signal such as a TSC television signal or an RGB separated television signal, the encoded television signal is output to the display device 6 for display.

The operation of the image processing apparatus configured as above will be described below. Here, it is assumed that the frame buffer memory M2 stores color data for one frame in the previous frame processing. Furthermore, as shown in FIG. 2, the color data of the image 21 of "Airplane" which has the highest priority (hereinafter referred to as the first priority) and the color data of the second image 21 which has a lower priority than the above image 21 are used. Color data of an image 22 of "clouds" which has a priority order, and color data of an image 23 of "Mt. Fuji Pa" which has a third priority order lower than the above image 22 are stored.

First, when the switching signal output from the signal generator 3 is at H level, the switches 10 to 14 are both switched to the a side, and the frame buffer memory M1 is used as a write memory, while the frame buffer memory M2 is used as a write memory. Used as display memory. At this time,
The control device 1 first resets the frame buffer memory M1 to store the color data of °'1111'' in all addresses, outputs a read control signal to the ROM2, and selects the priority video to be displayed from now on. After outputting the address of the color data of the image 21 of "Airplane" with the highest rank to the ROM 2 and reading out the color data of the image 21, the color data of the read image 21 is sent to the ROM 2 via the a side of the switch 10. Write input terminal DO
At the same time, the address of the frame buffer memory M1 corresponding to the display position where this image 21 is displayed is output to the address input terminals AO to A7 of the frame buffer memory M1. In response to this, the frame buffer memory M1 transfers the color data previously stored at the address input to the address input terminals SOO to A7 from the readout output terminals SOO to SO3 to the a side of the switch 13. It is output to the input terminal of the NAND gate NAND via the NAND gate. This frame buffer memory M1
Since the frame buffer memory Ml has been reset as described above, the color data outputted from the readout output terminals SoO to SO3 is n ill p, and at this time, the L level is output from the output terminal of the Nant gate NΔND. The data is written to the frame buffer memory M1 via the a side of the switch 11.
is input. Therefore, the color data of the image 21 inputted from the control device l to the write input terminal of the frame buffer memory M1 via the a side of the switch 10 is transmitted from the control device l to the address input terminals ΔO to A7 of the two-frame buffer memory M1. are stored sequentially at the addresses input to the .

After the image 21 is stored in the frame buffer memory IJ M l, a read control signal is output to the ROM 2, and the address of the color data of the image 22 of the cloud with the second priority to be displayed is sent to the ROM 2. After outputting and reading the color data of the image 22, outputting the read color data of the image 21 to the write input terminals Do to D3 via the a side of the switch 10, and displaying the image 22. The address of the frame buffer memory Ml corresponding to the position is outputted to the address input terminals AO to A7 of the frame buffer memory M1.In response, the frame buffer memory Ml:
The image 210 color data previously stored at the address input to the address input terminals AO to Δ7,
Switch 1 from read output terminal SoO or SO3
It is output to the input terminal of the Nandt gate NΔND via the a side of 3. The color data output from the readout output terminals S00 to SO3 of the frame buffer memory M1 is color data other than '1111°° at the address where the color data of the "airplane" image 21 is stored. Therefore, at this time, the H level data output from the NAND gate NAND is sent to the write enable terminal W of the frame buffer memory Ml via the a side of the switch 2.
The color data input from the control device 1 through the a side of the switch 1o is not written, and therefore the color data of the original "°°plane" image 21 is stored in the frame buffer memory M1. On the other hand, the readout output terminal So of this frame buffer memory M1
The color data output from O to SO3 is the reset color data of °'+111'' at the address where the color data of the image 21 of °゛plane °° is not stored, so at this time, Nantes Gate NAND
The L level data output from the controller 1 is input to the write enable terminal WE of the frame buffer memory M1 via the a side of the switch 11, and
The writing of color data input through the a side of the cloud is performed, and therefore only addresses where the color data of the original "airplane" image 21 is not stored have the second priority level. The color data of the °° image 22 is stored in the frame buffer memory M1.

Furthermore, in the same way, °° having the above third priority
The color data of the image 23 of "Mt. Fuji" is sent to the readout output terminal S of the frame buffer memory M1.

Only at addresses where the data output from O to SO3 is "lit", that is, the above image 21.
22 color data is stored only at addresses where it is not stored. By the above steps, the first to third
If the images 21 to 23 are stored in the same address according to the priority order, the color data of the image 21 or 22 with the higher priority will be stored. Color data for one frame including the stored images 21 to 23 is stored in the frame buffer memory Ml.

On the other hand, in response to the address input from the frame buffer memory M21:L and control unit 1, the color data for one frame is sent to the switch 14 from the readout output terminal.
The signal is output to the television signal encoder 4 via the side. In response to this, the television signal encoder 4 stores the input 4-bit parallel color data for one frame in the ROM, and creates a lookup table 5 in which the color data and data related to the television signal corresponding thereto are stored in advance. In reference to,
For example, after being encoded into a television signal such as an NTSC television signal or an RGB separated television signal, the encoded television signal is output to the display device 6 for display.

Next, when the switching signal output from the signal generator 2)3 becomes L level, the switches IO to 14 are both switched to the b side, and the frame buffer memory Ml
is used as a display memory, while frame buffer memory M2 is used as a write memory. At this time, the control device 1 first resets the frame buffer memory M2 to store the color data of "tzt"° in all addresses, and also sends the readout control signal to the ROM2.
At the same time, the color data of the video to be displayed from now on is read out from the ROM 2 in the order of highest priority in the order of priority, and then the read data is sent to the frame buffer memory via the b side of the switch 10. M
At the same time, the address corresponding to the display position of the moving image is output to the address input terminals AO to A of the frame buffer memory M2.
Output to 7. Hereinafter, in the same machine as described above, only when the color data output from the readout output terminals SOQ to S03 of the frame buffer memory M2 is "1111", the color data of the image with a lower priority is determined by the address corresponding to that color data. Stored. As a result, the color data of a plurality of moving images are stored in the frame buffer memory M2 in accordance with the priority order.

On the other hand, the frame buffer memory M1 outputs color data for one frame from the read output terminal to the television signal encoder 4 via the b side of the switch 14 in response to an address input from the control device l. Ru. In response to this, the television signal encoder 4 converts the input 4-bit parallel color data for one frame into the ROM, and stores the color data and data related to the corresponding television signal in a look-up table in advance. 5, for example N
'After encoding into a television signal such as an SC television signal or an RGB separated television signal, the encoded television signal is output to the display device 6 for display.

Thereafter, in the same manner, the frame buffer memories M1 and M2
correspond to the level of the switching signal outputted from the signal generator 3, that is, every frame at a cycle of 1/60 seconds, and alternately become a writing memory and a display memory, respectively, and the frame buffer memories Ml, Writing and reading out the color data of the moving image to M2 and displaying the color data are repeated.

As explained above, when writing moving image color data to the frame buffer memory M1 or M2 used as a writing memory, frames are selected from moving image color data having a higher priority as in the first image processing method described above. Write to buffer memory M1 or M2,
Moreover, "1111" indicates that the color data previously written at the address to be written is transparent.
The color data of the moving image is written only when the output data of the NAND gate is at L level and the write enable state is reached. The color data of the desired moving image can be written to the frame buffer memories Ml, M2 at twice the speed compared to the second image processing method, that is, when the size of the moving image is constant, the second image processing method It is possible to write twice as many videos as the image processing method.

This can prevent a situation where a certain number of moving images cannot be displayed as in the conventional example. According to the inventor's experiments, one frame buffer memory M1
Alternatively, in the conventional example, only 128 moving pictures can be written to M2, whereas in this embodiment, 256 moving pictures can be written every time.

Compare the 4-bit data written to the write input terminal Do or D3 of the frame buffer memory M1 or M2 with the 4-bit data output from the read output terminal SoO or SO2 of the frame buffer memory M1 or M2. By determining whether or not they are the same, the advantage is that, for example, in a video game device such as a gun, it is possible to easily perform the so-called Oi collision determination, which determines whether or not a ball ejected from a gun hits a target. be.

In the above embodiment, a so-called two-frame buffer method is used, which is equipped with two frame buffer memories Ml and M2, but the present invention is not limited to this. The writing may be performed during the vertical blanking period of the television signal, and the above-described data reading and display processing may be performed during the video signal period after the vertical blanking period.

In the above embodiment, a frame buffer method is described in which display is performed using a frame buffer memory. The moving image may be written, read out, and displayed repeatedly every horizontal period by using the same configuration as in the above-described embodiment.

In the above embodiments, the case of an image processing device in which the image data is color data is described, but the invention is not limited to this, and the 4-bit data "1111"° is transparent, and the other data An image processing apparatus that performs black-and-white image processing may be configured such that the data represents the gradation of gradation of a black-and-white image. Further, although the data indicating transparency is "1111", the data is not limited to this, and other data may be used.

[Effects of the Invention] As described in detail above, according to the present invention, when writing image data, the first terminal of the second storage means having the first terminal for output and the second terminal for input When the read image data is image data indicating transparency, the image data having a higher priority is read out from the second storage terminal. Since writing is performed through the second terminal of the means, reading and writing of the image data can be performed in parallel through the first and second terminals of the second storage means, and the display A plurality of image data having priority orders of It has the advantage of being possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing device according to an embodiment of the present invention, and FIG. 2 is a front view showing an example of a moving image stored in the ROM of the device shown in FIG. ■... Control device, 2... Read-only memory (ROM), 3... Signal generator, 4... Television signal encoder, 5... Lookup table, 6... Display device, 10 to 14...Switch, Ml, M2...Frame buffer memory, NAND/
... Nantes Gate.

Claims (2)

[Claims] (1) A first storage means for storing a plurality of image data each having a display priority including data indicating transparency and data indicating color or gradation of the image, and an address to be input and In response to the first control signal, the image data stored at the input address is outputted from the first terminal, and the image data input from the second terminal is stored at the input address, and the image data stored at the input address is outputted from the first terminal. a second storage means for outputting the image data stored at the input address from the first terminal in response to the input address and a second control signal; A first control signal is output when the data output from the terminal is data indicating that the data is transparent, and on the other hand, the data output from the first terminal of the second storage means indicates that the data is transparent. determining means for outputting a second control signal when the image data is not data; The read image data and the address corresponding to the display position of the read image data are sequentially output to the second storage means, and the address of the image data stored in the second storage means is read when the image data is read. It is characterized by comprising a control means for outputting to the second storage means, and an encoding means for encoding the image data output from the second storage means into a television signal when reading the image data. Image processing device. (2) The image processing apparatus according to claim 1, further comprising display means for displaying an image of the television signal output from the encoding means.