JPH01273348A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the frequency of soft errors caused by alpha rays, by structurally adding a capacity to a grounding conductor to the cell node of a static semiconductor storage device. CONSTITUTION:A groove is made in a silicon substrate 104 with a contact hole, which is made in a thick insulating film 103 on said silicon substrate 104, used as a mask. An opposite conductivity type diffusion layer area 105 is formed on the surface of the silicon substrate 104 in the groove, a first polycrystalline polysilicon film 101 is grown continuously on the inner surfaces of both a contact and the groove, and a thin nitride film 107 and a second polycrystalline silicon film 108 are formed to make a capacitor comprising the first and second polycrystalline silicon films 101 and 108 and the nitride film 107. This maintains the second polycrystalline silicon film 108 at constant potential.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a cell structure of a static semiconductor memory device.

[Prior Art] Conventionally, in a load resistance type static semiconductor memory device, no device structural measures have been taken against soft errors caused by α rays.

[Problems to be Solved by the Invention] In recent years, as semiconductor memory devices have become highly integrated, soft errors due to alpha rays have become a problem not only in dynamic memory but also in static memory devices due to a decrease in node capacity due to a reduction in the area of cell nodes. It is becoming.

[Differences between the invention and the prior art] In the conventional static semiconductor memory device described above, no countermeasures were taken against the reduction in the capacitance of the cell node to the ground line due to the miniaturization that accompanies integration. The static semiconductor memory device according to the present invention has a difference in that the capacitance of each cell node to the ground line can be increased at will, regardless of the miniaturization of the pattern.

[Means for Solving the Problems] The present invention provides a semiconductor device formed on a silicon substrate of one conductivity type, in which a contact hole formed in a thick insulating film on the silicon substrate is used as a mask to form a contact hole in the silicon substrate. a dug groove, an opposite conductivity type diffusion layer region formed on the surface of the silicon substrate in the groove, and a first polycrystalline silicon film continuously grown on the inner wall of the contact and the inner wall surface of the groove. , a thin nitride film and a second polycrystalline silicon film;
The gist is that the polycrystalline silicon film is kept at a constant potential.

oral example Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 2 is an equivalent circuit diagram showing one memory cell of a static random access memory to which the present invention is applied.

In Figure 2, memory cell selection MO5) transistor Q
A word line W is commonly connected to the gates of I and Q4,
A bit line IBI and a bit line 2B2 are connected to the drain (or source) diffusion layers of these transistors, respectively. Flip-flop MOS) transistor Q2. configured by cross-coupling. The drain of Q3 and the sources (or drains) of transistors Ql and Q4 are connected at nodes N1 and N2, respectively.

Nodes Nl and N2 are connected to a power supply line via load resistors R1 and R2, respectively. Transistor Q2. The sources of Q3 are commonly connected to the ground line. In this embodiment, both the capacitance from the nodes Nl and N2 to the ground line and the diffusion layer capacitance from the substrate to the substrate are increased by the capacitances CI and C2. FIG. 3 is a plan view of a cell showing the structure of the static random access memory shown in FIG. 2. In this example, the word line W is made of second layer polycrystalline silicon N302, the power line and the load resistance layer are made of second layer polycrystalline silicon N302, the ground line is made of the third layer polycrystalline silicon layer, and the bit line 1 is made of aluminum wiring. The contact hole 303 for line 1 connects to the N+ diffusion layer, and the bit line 2 is similarly connected to the contact hole 304 for bit line 1. The load resistors R1 and R2 are connected to the cell note via the node 1 contact and the node 2 contact, respectively, and the ground line of the third polycrystalline silicon layer is arranged to cover the node 1 contact and the node 2 contact, Further, the source diffusion layers of the transistors Q2 and Q3) are connected to the 3N polycrystalline silicon layer for the ground line by contacts 1, 2, 305, and 306 for the ground line.

In order to structurally explain the increase in the capacitance to ground line of the cell node portion and the increase in the diffusion layer capacitance due to the increase in the total diffusion area of the cell node N, which are the features of the present invention, the cross-sectional structure of the section A-A' in FIG. Examples of the manufacturing method are shown in FIGS. 1 and 4(a) to (f), respectively. The cross-sectional structure of the embodiment is as shown in FIG.
1 to the connected node of the gate poly of the Q1 transistor and Q2) transistor through the node contact 102
This node contact 102 has a cylindrical groove 3 μm deep and 1 μm diameter dug in the silicon substrate 104 using a self-line from a contact hole to the glabellar oxide film 103. On the side wall of the silicon trench, a node N0 diffusion N105 is formed with a depth of 0.2 μm, effectively increasing the total area of N0 diffusion at the node to approximately three times, and also approximately three times the capacitance of the diffusion layer at the node. It has increased to . A resistive polysilicon layer 106 is formed on the inner wall of the node contact hole and the silicon groove.
In particular, the inner wall of the silicon groove is connected to the power supply line through the resistive polysilicon 106. The resistive polysilicon surface inside the silicon trench has an additional 200
A solid silicon nitride film 107 is grown, and polysilicon doped with phosphorus fills the silicon trench and is connected to a ground line 108 in the surface layer. For this purpose, a capacitor is formed by sandwiching silicon nitride film 107 between the node N1 diffusion layer 105, the trench resistance polysilicon 106, and the ground line 108. As described above, the node has a structure in which both an increase in the N+ diffusion layer capacitance and the capacitance in the groove and contact between the ground line and the ground line are added as additional capacitances CI and C2.

An example of the manufacturing method of the embodiment will be described below. After patterning the gate polysilicon 3 for word lines and transistors by a normal manufacturing method as shown in FIG. 4(a), source/drain diffusion layers are formed by ion implantation,
As shown in FIG. 4(b), after forming a glabellar film 4 with a thickness of about 1.0 μm using an oxide film using a vapor phase growth method, a node contact 5 is opened and then silicon etching is performed using a self-aligning method. Depth 0°5μm
The node groove 6 is formed to a certain extent. Further, an in-trench N1 diffusion layer region is formed by diagonally implanting ions into the trench. As shown in FIG. 4(d), the polycrystalline silicon layer 7 and the groove resistor polycrystalline silicon 10 are simultaneously deposited in a vapor phase to connect the power supply line to the node of the cell via a load resistor having a high resistance of approximately ITΩ. Grow about 1000 people using the growth method and pattern them. After growing a thin nitride film of about 200 layers over the entire surface, it is patterned leaving only the necessary areas. At this time, the note portion of the cell, that is, the node contact portion, is covered with a thin nitride film 8 (FIG. 4(d)).

Next, a polycrystalline silicon film for a grounding line is grown on the gold surface after the contact hole for the grounding line at the periphery of the cell, and a capacitance is formed between the thin nitrided wire 8 and the polycrystalline silicon for the load resistance. It is also patterned so that it can be used as a grounding wire. After growing the second interlayer film, the semiconductor device of the present invention is formed by opening a contact hole and patterning the aluminum wiring.

[Effects of the Invention] As described above, the present invention can make soft errors caused by α rays less likely to occur by structurally adding a new ground line capacitance to the cell node of a static semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of an embodiment, FIG. 2 is an equivalent circuit diagram of a cell portion of a static semiconductor memory device to which the present invention is applied, and FIG. 3 is a plan view showing the structure of an embodiment. Fourth
Figures (a) to (f) are cross-sectional views following the manufacturing process of one embodiment. 101...Resistance polysilicon, 102...Node contact, 103...Interlayer film, 104...Substrate, 105...Node N1 diffusion layer, 106...Inside groove Resistor polysilicon, 107...
Thin insulating film, 108...Ground line, 301...Word line, 302...Power line, 303...Bit line 1 contact, 304...
・Contact for bit line 1, 305...Contact for ground line 1.306...Contact for ground line 2゜Patent applicant Kiyoshi Kuwai, agent of NEC Corporation, patent attorney - 303 Bit line 1 Contact Fig. 3 Fig. 4, a) 1 ρ-type silicon I
Sheet Fig. 4 (b) Fig. 4 (C) No. 4” (d> Fig. 4 (e) /13 Aluminum plate Fig. 4 (0

Claims (2)

[Claims] (1) In a semiconductor device formed on a silicon substrate of one conductivity type, using a contact hole drilled in a thick insulating film on the silicon substrate as a mask, a groove dug in the silicon substrate and inside the groove are formed. an impurity region of opposite conductivity type formed on the surface of the silicon substrate, a first polycrystalline silicon film continuously grown on the inner wall of the contact and the inner wall of the trench, a thin insulating film, and a second polycrystalline silicon film. 1. A semiconductor device comprising a silicon film, the second polycrystalline silicon film being maintained at a constant potential. (2) The thick insulating film has a thickness of 1.0 μm or more,
2. The semiconductor device according to claim 1, wherein the groove has a depth of 0.3 μm or more, and the thin insulating film has a thickness of 300 Å or less.