JPH01273294A - Electrically writable and erasable memory device - Google Patents

Abstract

PURPOSE:To prevent excessive fatigue of the title memory device caused by the stress of an electric field and to reduce the writing and erasing time of the device by additionally providing a circuit which discriminates whether a cell is in the writing or erasing state and another circuit which controls the write and erasure. CONSTITUTION:At the time of erasing a cell 9, the cell 9 is erased by the period when a voltage VPP and signals, W, E, and CO the inverse of are respectively a high voltage and '0', '1', and '1'. During the period when the signal CO of the inverse of is '0', transfers (YF) 17 and 26 are turned of so as to make an AND 1 to become '1' and a transistor (Tr) 24 is turned off so as to apply a voltage of VDD-VTN across the cell 9. If the threshold of the cell 9 is lower than the voltage VDD-VTN, the cell 9 is turned on and the output of a sense amplifier 26 is held by a latch 27 after setting the output to '1'. The value '1' is compared with an anticipated value at a comparator circuit and outputs of an EXNOR 21 and NAND 23 are respectively set to '0' and '1', while a TF 25 is kept in a turned-on state. Then the signal of the inverse of CO becomes '1' and the cell 9 is erased. The above- mentioned operations are repeated until the signal of the inverse of CO' becomes '0' and the threshold of the memory cell 9 exceeds the voltage VDD-VTN. Even when the signal of the inverse of CO becomes '1', no high voltage is applied across the gate of the cell 9 and the erasure is interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, and particularly to electrically programmable and erasable memories.

[Prior Art] Conventionally, electrically erasable/writable memories (elect
orically Erasable Progra
mable Read Only Memory
When erasing/writing an EEPROM (hereinafter referred to as EEPROM), it is performed according to the basic timing shown in Figure 5.The erasing/writing width depends on the control signal, and the threshold value (shift amount) of the cell is saturated. Up until then, erasing and writing had been performed.

Next, a conventional technique will be explained with reference to the drawings. Second
The figure shows an example of a current mirror type sense amplifier, which outputs "1" at OUT when current flows through IN, and outputs "0" at OUT when no current flows.

Figure 3 shows an example of a level shifter. When the ground potential is input to IN, "0" is output to OUT, and the power supply voltage ("1")
This circuit outputs a high voltage (VPP) to OUT when it is input.

FIG. 4 is an example of the prior art. First, the case of erasing an EEPROM cell (hereinafter referred to as cell) 62 will be explained as an example. Table 1 is an example of signal levels for writing, erasing, and reading.

Table 1 From Table 1, VPP is at a high voltage (around 20V) during erasing.
The signal E becomes '1', the signal W becomes '0', and the cell 62
In order to select, the Y selector signal YS cell select signal C5I is set to "1". At this time, the state of each transistor is that the level shifter L13 is 0" and the transfer 72 is off, the level shifter L14 is high voltage and the transfer 71 is on, and the level shifter L13 is 0" and the transfer 72 is off. L10.L11 is at high voltage, transistors 60, 61, 63 are turned on, high voltage is applied to the gate of cell 62, ground potential is applied to the source, electrons are injected into the floating gate of cell 62, and the threshold value is (The threshold value rises to point a shown in Figure 6).

Next, the case of writing to the cell 65 will be explained as an example. Table 1
When writing, VPP is at a high voltage (around 20μ), and signal E
Is it +10+? , signal W becomes 11199, and cell 6
In order to select 5, the Y selector signal Y85 and cell select signal CS2 are set to "1".

At this time, the state of each transistor is that the level shifter L13 is at high voltage and the transfer 72 is on, the level shifter L14 is at 0" and the transfer 71 is off, the OR 70 is 1" and the transistor 67 is on, and the level shifter LIO and L12 are at high voltage and the transistor 60, 64, and 66 are turned on, ground potential is applied to the gate of cell 65, and high voltage is applied to the drain, holes are injected into the floating gate of cell 65, lowering the threshold value of the cell (Fig. 6). b shown in
(the threshold falls to the point where the threshold reaches negative territory).

When writing, write when the data input signal is 1".
When the flag is 0'', no writing is performed.

During reading, the transistor 67 is turned on, so the potential applied to the gate of each cell becomes the ground potential, and if the cell threshold is higher than the ground potential, it is in the erased state, and the OUT of the sense amplifier 72 is “02”.゛If it is lower than the ground potential, it is in the write state, and the OUT of the sense amplifier 72 is “1”.
” is output.

[Problems to be Solved by the Invention] The conventional EEPROM described above has a sufficient write/erase width even for variations in cell characteristics, so the cell threshold voltage reaches saturation, as shown in Figure 6. Since high voltage is continuously applied to the drain or gate of the cell for a long time up to points a and b), excessive fatigue occurs due to electric field stress on the oxide film, reducing the reliability and number of rewrites of the EEPROM. have.

[Means for Solving the Problems] The EEFROM of the present invention includes a control signal generation circuit that repeats writing and erasing in a shorter time than the normal writing and erasing time, and a control signal generation circuit that checks whether the read value matches the expected value. It has a comparison circuit for discrimination and a high voltage supply cutoff circuit for stopping the supply of high voltage to the memory cell when the value matches the expected value.

[Example code] Next, the present invention will be explained with reference to the drawings.

In addition to the basic timing shown in FIG. 5, consider the signal Co (over par) shown in FIG. This may be created using an external signal or an example of a ring oscillator shown in FIG. The pulse widths of tpwl and 2·φ·n shown in FIG. 7 must be made sufficiently smaller than those of TPWW and TPWE shown in FIG. FIG. 1 shows an example of a circuit for setting the cell threshold voltage to 00-VTN (point C) during erasing and to the ground potential (point 6) during writing.

First, the case of erasing cell 9 will be explained.

From Table 1, VPP is high voltage, signal W is +10IT, signal E
is 1", cell 9 begins to be erased during the period when Co (over par) is 1" as in the conventional example.Next, during the period when Co (over par) is 'O', transfer 17.26 is turned off and the antenna is 1 becomes 1'', transistor 4 is turned on, and a voltage of VDD-VTN is applied to cell 9.At this time, if the threshold value of cell 9 is smaller than VDD-VTN, cell 9
is turned on, and the output of the sense amplifier 26 is set to 1'' and held in the latch 27. (FIG. 9 is an example of a latch in which Co (over par) is held at !Il+!).

The held value 111+1 is determined by a comparison circuit that determines whether the read value matches the expected value (this circuit consists of AND1, 2, transistors 4, 5, latch 27, E
EXNOR21 (consisting of 7
) The output is set to "II O", the NAND 23 is set to "1", and the transfer 25 is kept on. Next, Co (over par) becomes "1" and cell 9 is erased, Co (over par) becomes "0" and compared, the threshold value of cell 9 is VD
Repeat until D-VTN is exceeded. Co (over par) becomes Pa0゛2 and the threshold value of cell 9 becomes VDD-V
When TN is exceeded, cell 9 is turned off and sense amplifier 26
The output of EXNO is set to 0 and held in the latch 27.
The output of R is set to "1", the NAND 23 is set to 0°, and the transfer 25 is turned off.

Therefore, even if Co (over par) becomes "1" next time, no high voltage is applied to the gate of the cell, and erasing is interrupted.

The case of writing to cell 12 can be similarly explained. From Table 1, V
F'P is high voltage, signal W is 1'', signal E is 0°' and CO
The period when (over par) is ``1'' and D is °'1'' (
When the information to be written is D=1), writing is started in the same way as in the conventional example. Next, CO (over par) is “0”
During the month ``'', transfer 17.26 is turned off, AND2 becomes 1'', transistor 5 is turned on, and cell 1 is turned off.
A ground potential is applied to the gate of 2. At this time, if the threshold voltage of the cell 12 is higher than the ground potential, the cell 12 is turned off, the output of the sense amplifier 26 is set to "0", and the latch 27
to hold. The held value "0" is compared by a threshold voltage comparator circuit, and the output of EXNOR 21 is set to "O11", NAND 23 is set to "1", and transfer 25 is kept on. Next, Co (over par) becomes "1" and is written into the cell 12, and Co (over par) becomes "0" and the comparison is repeated until the threshold value of the cell 12 falls below the ground potential. When Co (over par) becomes "0" and the threshold of cell 12 falls below the ground potential, cell 12
is turned on and the output of the sense amplifier 26 is set to "1" and held in the latch 27. The held value Pa1"' is compared in a threshold voltage comparator circuit, and the output of EXNOR21 is set to 1.
1111, Nando 23 to "0pa", transfer 2
Turn 5 off.

Therefore, even if Co (over par) becomes 1'' next time, no high voltage is applied to the drain of the cell, and writing is interrupted.

Also, when the writing time is 0, AND 14 becomes 11111, turning on the transistor 13, inputting +l□I+ to the sense amplifier 26, and when Co (over par) is 0"', the operation is the same as when writing is completed. .

[Effects of the Invention] As explained above, the present invention improves the EEPR of semiconductor integrated circuits.
A circuit that determines whether the state of the cell in the OM is written or erased;
By adding a circuit for controlling programming and erasing, it is possible to automatically control programming and erasing, thereby preventing excessive fatigue due to electric field stress on the oxide film of the cell.

In addition, the output of the cell state determination circuit is signaled (NAND 2 in Figure 1).
3 output) as the next address you want to write or erase,
By controlling the data, it is also possible to shorten the write/erase time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a current mirror circuit, FIG. 3 is a circuit diagram of the level shifter shown in FIG. 1, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a waveform diagram showing the conventional basic timing, FIG. 6 is a graph showing the cell threshold, FIG. 7 is a waveform diagram showing the basic timing of the present invention, FIG. 8 is a circuit diagram showing the ring oscillator, and FIG. FIG. 9 is a circuit diagram of the latch circuit. 1, 2. 16゜18.14...AND circuit, 20.22...OR circuit, 3, 16. 19°54, 59. 73゜74.203,206...Inverter, Ll, L
2. L3. L4゜L5. L6. LIO,Lll
. L12. Ll3. Ll4...Level shifter, 50~5
3.55-5B, 60. 61. 63°64.6
6.67.68.4-8. 10. 11°13.24
...transistor, 17.25,26,71.72...transfer, 9,
12,62.65...EEFROM cell, 26.
72...Sense amplifier, 27...Latch, 23.200...NAND, 2l----EXNORl 201.204... -Resistance, 202.205... ·capacity. Patent applicant: Nippon Electric IG - Representative of Micom System Co., Ltd. Patent attorney: Kiyoshi Kuwai - Figure 2. ＃口bsoFigure 3Figure 6○tJT: Figure 4Figure 8Figure 9

Claims (1)

[Claims] In electrically writable/erasable storage devices, a control signal generation circuit repeats writing/erasing in a shorter time than the normal writing/erasing time, and determines whether the read value matches the expected value. a comparison circuit,
An electrically writable/erasable memory device comprising a high voltage supply cutoff circuit that stops supplying high voltage to a memory cell when the value matches an expected value.