JPH01273137A - Abnormality detecting system for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simply and surely detect the generation of a fault by detecting a fact that a clock waveform does not exist in a signal outputted from a semiconductor integrated circuit and deciding abnormality of the semiconductor integrated circuit. CONSTITUTION:The semiconductor integrated circuit is constituted so that a digital signal is outputted by adding a waveform of a clock signal at every machine cycle, and based on existence of a clock waveform which appears at every machine cycle of a signal outputted from this semiconductor integrated circuit, abnormality of the semiconductor integrated circuit is detected. That is, when the semiconductor integrated circuit which is integrated in as a system is broken down due to a mechanical impact, heat or a surge voltage, etc., a state of a signal in the inside and the outside of the semiconductor integrated circuit concerned is fixed to a high level or a low level, by which the clock waveform which is added to an output signal of the semiconductor integrated circuit in a normal state comes not to exist. In such a way, the generation of a fault related to the semiconductor integrated circuit or a prescribed signal is detected, and safety of the system can be secured instantly and surely.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to abnormality detection technology for semiconductor integrated circuits.

For example, it relates to a technique that is effective when applied to fail-safe (Fail 5afe) of microcomputer systems.

[Prior art]

Semiconductor integrated circuits incorporated into a system may be destroyed by mechanical shock, heat, or surges caused by static electricity, and such failures cause the system to stop or run out of control.

Systems where a system stop or runaway would have a serious impact;
For example, in microcomputer systems for engine control installed in automobiles, etc., abnormality detection technologies such as the iTchidog timer or heartbeat circuit have traditionally been the mainstream technology to monitor system stoppages and runaways. For example, a watchdog timer monitors abnormal program loops and runaways by resetting a counter at regular intervals. Abnormal conditions detected by this are transmitted to the outside.

Based on this information, system switching is performed to ensure system safety.

An example of a document describing abnormality detection in a system is "R Microcomputer Handbook" published by Ohm Publishing on December 25, 1985, pages 750 to 752.

[Problem to be solved by the invention]

However, since the abnormality detection by the watchdog timer is indirect, there is a limit to the reliability of abnormality detection, and since it is a comprehensive technology of software and hardware, its configuration is complex, and moreover, it is difficult to detect errors using a microcomputer. The inventor of the present invention has found that there is a problem in that it is difficult to apply the method to LSIs other than data processing LSIs.

An object of the present invention is to provide a system that can easily and reliably detect abnormalities in semiconductor integrated circuits.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, when a semiconductor integrated circuit is destroyed, the state of the signals inside and outside the circuit becomes high level.

Alternatively, by focusing on the fact that the digital signal is fixed at a low level, a predetermined clock waveform is added to each operating cycle in order to distinguish the state of the digital signal output from the semiconductor integrated circuit in the normal state from its destroyed state. A semiconductor integrated circuit is configured to output a digital signal, and an abnormality in the semiconductor integrated circuit is detected based on the presence or absence of a change in a clock signal that appears every operation cycle of the signal output from the semiconductor integrated circuit. It is something to do.

[For production]

According to the above-mentioned means, a failure condition regarding a semiconductor integrated circuit or its output signal is defined as the output signal being fixed at a low level or a high level. Furthermore, if the semiconductor integrated circuit is destroyed by a surge voltage, etc., the state of the signal inside or outside the semiconductor integrated circuit is fixed at a high or low level, which causes the signal to be added to the output signal of the semiconductor integrated circuit under normal conditions. Since the clock waveform no longer exists, it is possible to detect the occurrence of a failure in the semiconductor integrated circuit or a predetermined signal, thereby immediately ensuring the safety of the system.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 1 is a microcomputer, and an address output buffer circuit 2 and a data output buffer circuit 3 are representatively shown. The output terminal of the data output buffer circuit 3 is connected to a predetermined data signal line DL included in the data bus.
In addition, the output terminal of the address output buffer circuit 2 is coupled to a predetermined address signal line ALi included in the address bus. These data signal lines DLi and address signal lines ALi are also interfaced with peripheral circuits (not shown).

The address output buffer circuit 2 has an address signal Ai
an output buffer 4 which inputs the signal and outputs it to the address signal line ALi at a predetermined timing, and a clock signal 2.
It is constituted by an output buffer 5 which inputs φ and outputs it in a time-sharing manner with the output buffer 4 at a predetermined timing.

The output of the pair of output buffers 4 and 5 is controlled by a clock signal φ. Although this clock signal φ is not particularly limited, as shown in FIG. It is said to be a signal that defines the Although not particularly limited, the clock signal 2φ is a signal obtained by dividing the clock signal φ by two.

Here, in terms of the system, the address signal Ai is considered to be a signal that has meaning in the first half of one machine cycle, although it is not particularly limited, and is considered to be a substantially uncertain or meaningless signal in the second half. Accordingly, the output buffer 4 outputs the address signal A in response to the low level period of the clock signal φ corresponding to the first half of one machine cycle.
Take in i and output it. The output buffer 5 takes in the clock signal 2φ and outputs it in response to the high level period of the clock signal φ corresponding to the latter half of one machine cycle. As a result, the output signal Aouti of the address output buffer circuit 2 is output from the clock signal 2 in the latter half of one machine cycle, as shown in FIG.
It is assumed to be a digital signal to which φ is added.

The data output buffer circuit 3 includes an output buffer 6 that inputs data Di and outputs it to the data signal line DLi at a predetermined timing, and an output buffer 6 that inputs a clock signal 2φ and outputs it to the data signal line DLi at a predetermined timing. It is composed of an output buffer 7 that outputs time-divisionally between the two. The output of the pair of output buffers 6 and 7 is controlled by an inverted signal of the clock signal φ.

In terms of the system, the data Di is not particularly limited, but
The signal is considered to have meaning in the second half of one machine cycle, and the first half is considered to be substantially uncertain or meaningless. Accordingly, the output buffer 6 is
Data Di is taken in and outputted in response to the high level period of the clock signal φ corresponding to the latter half of one machine cycle. The output buffer 7 takes in the clock signal 2φ and outputs it in response to the low level period of the clock signal φ corresponding to the first half of one machine cycle. As a result, the output signal Do of the data output buffer circuit 3
As shown in FIG. 2, uti is a digital signal to which a clock signal 2φ is added in the first half of one machine cycle.

Note that the output buffers 4 and 6 can selectively take a high output impedance state by an internal control signal (not shown), although this is not particularly limited. Although not particularly limited, output buffers of other peripheral circuits (not shown) coupled to the data signal line DLi are also configured to be able to output data to which the clock signal 2φ is added at approximately the same timing as the data output buffer circuit 3. There is.

Similarly, when another path master module is connected to the address signal line ALL, the address output buffer included in the path master module also receives the clock signal 2φ at approximately the same timing as the address output buffer circuit 2. It is configured to be able to output data.

The address signal line ALi and data signal line DLi are provided with signals A o u ti and Douti output from the address output buffer circuit 2 and the data output buffer circuit 3.
The input terminal of a monostable multivibrator 8.9 for detecting the waveform of the clock signal 2φ included in the input terminal is coupled thereto. These monostable multivibrators 8 and 9 are not particularly limited, but due to the resistance and capacitance elements (not shown) included therein, a change in the input from rising to falling in a period shorter than one machine cycle causes a change in the high level output. Its oscillation characteristics are set so that it does not occur. Therefore, as shown in FIG. 2, the output signal A at each machine cycle.

Signal line D L from Uti, Douti and other peripheral circuits
As long as the signals output to L and ALi contain high-level pulses with a width shorter than one machine cycle, the outputs of the monostable multivibrators 8 and 9 maintain a high level.

In FIG. 1, reference numeral 10 denotes a monitoring circuit that detects the occurrence of a system failure or the destruction of a semiconductor integrated circuit included in the system based on the outputs of the monostable multivibrators 8 and 9. This monitoring circuit 10 is not particularly limited, but when it detects that the outputs of the monostable multivibrators 8 and 9 have changed to a low level, it switches the system to a backup system or issues an alarm, thereby improving the system. Stay safe.

Next, the operation of the above embodiment will be explained.

When the semiconductor integrated circuit included in the system is operating normally, the waveform of the clock signal 2φ added in the latter half of each machine cycle is displayed on the address signal line ALi by the action of the address output buffer circuit 2, etc. ing. In addition, a clock signal 2φ added to the data signal line DLi in the first half of each machine cycle is generated by the action of the data output buffer circuit 3 included in the microcomputer 1 and the data output buffer circuit (not shown) included in other peripheral circuits. A waveform appears. In this state,
The monostable multivibrators 8 and 9 have a clock signal 2
A high-level pulse with a width shorter than one machine cycle is given by the waveform of φ, and this causes the output of the monostable multivibrator 8゜9 to maintain a high level, thereby allowing the monitoring circuit 10 to check the normal state of the system. To detect.

For example, the microcomputer 1 included in this system
When it is completely destroyed by mechanical shock, heat, or even a surge voltage, its internal signal state is fixed at a high or low level as defined by the power supply voltage level. In response to this, the output signal Aouti,D
outi is also fixed at high level or low level. Then, the signal waveform appearing on the address signal line ALi is also fixed at high level or low level. In addition, when other peripheral circuits connected to the data signal line DLi are also destroyed, even if there are peripheral circuits that are not destroyed, the output signal Do of the destroyed microcomputer is
As a result of uti being fixed at high level or low level,
The level of the signal line DLi is substantially fixed at high level or low level. In this way, the level of the signal line ALit DLi is fixed at high level or low level, and each machine cycle does not include a valid high level pulse, so that the outputs of monostable multivibrators 8 and 9 become low level. By inverting and detecting this in the monitoring circuit 10, safety measures are taken to avoid runaway or stoppage of the system.

Monostable multivibrators 8, 9 are connected to individual signal lines DLi
, since the abnormality is detected in one-to-one correspondence with ALi,
゛It is also possible to detect a partial failure in which the valid lock signal 2φ waveform is no longer added to a predetermined signal line, and have the monitoring circuit 10 take countermeasures.

According to the above embodiment, the following effects can be obtained.

(1) In order to distinguish the state of a digital signal output from a semiconductor integrated circuit in a normal state from a destroyed state or a faulty state, the waveform of the clock signal 2φ is added to each machine cycle. A semiconductor integrated circuit is configured to output a digital signal, and an abnormality in the semiconductor integrated circuit is detected based on the presence or absence of a clock waveform that appears in each machine cycle of the signal output from the semiconductor integrated circuit. If a semiconductor integrated circuit built into a system is destroyed by mechanical shock, heat, or surge voltage, the state of signals inside and outside the semiconductor integrated circuit will be fixed at high or low levels, causing normal operation. In this state, the clock waveform added to the output signal of the semiconductor integrated circuit no longer exists, and as a result, it is possible to detect the occurrence of a failure regarding the semiconductor integrated circuit or a predetermined signal, and to ensure the safety of the system immediately and reliably. .

(2) As a result of the above-mentioned effects, safety design against failure or destruction of the system can be uniformly and easily performed.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, a method was explained in which the clock signal 2φ is added in a time-division manner. In addition, the clock signal to be added is not limited to the branch signal of the clock signal that defines the machine cycle, but if it is a clock signal with a high oscillation frequency, it may be a clock signal that is asynchronous with the operation reference clock signal. You can also do that. Further, the clock signal for abnormality detection does not need to be added to all signals, and can be selectively added to only some signals.

In the above explanation, the invention made by the present inventor was mainly applied to microcomputer systems, which is the background field of application, but the present invention is not limited thereto, and can be applied to various data processing systems. The present invention, which can be widely applied, can be applied to at least a digital signal to be outputted to the outside, provided with a condition that a clock signal waveform is added at a predetermined timing every operation cycle.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, in order to distinguish the state of a digital signal output from a semiconductor integrated circuit in a normal state from its destroyed state, a semiconductor integrated circuit is designed to output a digital signal by adding a clock signal waveform to each operation cycle. Since the semiconductor integrated circuit is configured to detect the absence of a clock waveform in the signal output from the semiconductor integrated circuit to determine an abnormality in the semiconductor integrated circuit, it is possible to prevent the occurrence of a fault related to the semiconductor integrated circuit or a predetermined signal. This has the effect that it can be detected easily and reliably. Moreover, it has the effect of contributing to the standardization and simplification of the fail-safe design of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing an example of the operation.

Claims (1)

[Claims] 1. A semiconductor integrated circuit including an output means for adding a clock signal waveform at a predetermined timing in each operation cycle to a digital signal to be outputted to the outside, and a semiconductor integrated circuit including an output means for adding a clock signal waveform to a digital signal to be outputted to the outside, and a signal output from the output means. 1. An abnormality detection system for a semiconductor integrated circuit, comprising: detection means for detecting an abnormality in the semiconductor integrated circuit based on a change in a clock signal that appears in each operation cycle. 2. The semiconductor according to claim 1, wherein the output means superimposes the clock signal at the predetermined timing or inserts the clock signal at the predetermined timing in a time division manner. Integrated circuit anomaly detection system. 3. The above-mentioned detection means is a monostable multivibrator, and a change in the input in a period shorter than the above-mentioned operation cycle does not cause a change in the output. An abnormality detection system for a semiconductor integrated circuit according to item 1 or 2.