JPH0127288Y2 - - Google Patents
Info
- Publication number
- JPH0127288Y2 JPH0127288Y2 JP1983032990U JP3299083U JPH0127288Y2 JP H0127288 Y2 JPH0127288 Y2 JP H0127288Y2 JP 1983032990 U JP1983032990 U JP 1983032990U JP 3299083 U JP3299083 U JP 3299083U JP H0127288 Y2 JPH0127288 Y2 JP H0127288Y2
- Authority
- JP
- Japan
- Prior art keywords
- agc
- circuit
- time constant
- stage
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 claims description 12
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Circuits Of Receivers In General (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
この考案は無線通信機におけるAGC
（Automatice Gain Control）回路の改良に関す
る。[Detailed explanation of the invention] [Industrial application field] This invention is used for AGC in wireless communication equipment.
(Automatic Gain Control) circuit improvement.
従来の無線通信機では強力な受信入力による回
路の飽和を防ぎ、また出力レベルをなるべく一定
に保つために、高周波増幅段と中間周波増幅段に
AGCを掛けるのが普通である。通常のAGCは検
波段に加わる信号を整流して得たAGC電圧を前
段の増幅段に加えて、AGC電圧の大きさと反比
例して増幅度を低下させる、一種の整流負帰還で
あるため、整流したAGC電圧をそのまま前段に
掛けたのでは負帰還のために信号の変調度が浅く
なつてしまうので、変調成分が負帰還されないよ
うに、AGC制御回路には変調成分を除去するた
めの積分回路あるいはLPFを設けてあるが、こ
の回路の時定数により帰還動作に遅延を生じ、そ
のままでは急激な入力信号強度の変動に追従でき
ない場合がある。またSSBやCW電波のように振
幅変動の激しい信号に用いるAGCは保持時定数
をより大きく設定する関係上、信号変化の立上り
部分のAGC制御が遅れてオーバーシユート的波
形となり、受信音質を悪化させるもので、これに
対応するために二重時定数回路等によりフアスト
アタツクスローレリーズAGCを実用しているが、
レリーズ時定数を大きくしてアタツク時を小さく
することには限度があつて妥協点を求めて設計す
る必要があつた。
In conventional wireless communication equipment, in order to prevent circuit saturation due to strong receiving input and to keep the output level as constant as possible, high frequency amplification stages and intermediate frequency amplification stages are used.
It is normal to apply AGC. Normal AGC is a type of rectified negative feedback in which the AGC voltage obtained by rectifying the signal applied to the detection stage is applied to the previous amplification stage, and the amplification degree is reduced in inverse proportion to the magnitude of the AGC voltage. If the AGC voltage is directly applied to the front stage, the degree of modulation of the signal will become shallow due to negative feedback.In order to prevent the modulation component from being negatively fed back, the AGC control circuit is equipped with an integrating circuit to remove the modulation component. Alternatively, an LPF is provided, but the feedback operation is delayed due to the time constant of this circuit, and it may not be possible to follow sudden fluctuations in input signal strength as it is. Furthermore, because AGC used for signals with large amplitude fluctuations such as SSB and CW radio waves has a larger holding time constant, AGC control at the rising edge of a signal change is delayed, resulting in an overshoot-like waveform, which deteriorates received sound quality. In order to cope with this, fast attack low release AGC is implemented using a double time constant circuit, etc.
There is a limit to increasing the release time constant and decreasing the attack time, so it was necessary to find a compromise in the design.
本考案は上述の点に鑑み行なわれたもので、
AGCの立上りの遅れや変調度の鈍りのない信号
を得るAGC回路の提供を目的とする。
This invention was developed in view of the above points.
The purpose of the present invention is to provide an AGC circuit that obtains a signal without AGC rise delay or modulation dullness.
並列に設けた二組の増幅段は、それぞれ独立し
たAGC回路を有し、かつ、該AGCは異つた時定
数により構成され、二組の増幅段と出力は合成さ
れることにより、帰還動作の遅延と信号の変調度
の鈍りを補償し得る特性を有する。
The two sets of amplification stages installed in parallel each have an independent AGC circuit, and the AGCs are configured with different time constants, and the two sets of amplification stages and outputs are combined to control the feedback operation. It has characteristics that can compensate for delays and dullness of signal modulation depth.
第２図は本考案の実施例のブロツク図で、図に
は入力部は省略して受信ミクサ１以後の段の構成
を示している。ミクサ１以前は高周波段であつて
も中間周波段であつても差しつかえ無い。中間周
波増幅段２と３はミクサ１の出力を増幅して、合
成出力を復調器４に供給し、復調出力は増幅器５
を通つて出力する。さらに中間周波増幅段２と３
の出力はそれぞれAGC増幅器６，７を通つて
AGC整流器８，９に加え、整流出力をそれぞれ
異る時定数回路１０，１１を通して中間周波増幅
段２，３、のゲイン制御端子に帰還しAGC動作
を行わせている。
FIG. 2 is a block diagram of an embodiment of the present invention, in which the input section is omitted and the structure of the stages subsequent to the receiving mixer 1 is shown. Before mixer 1, it does not matter whether it is a high frequency stage or an intermediate frequency stage. Intermediate frequency amplification stages 2 and 3 amplify the output of mixer 1 and supply the combined output to demodulator 4, and the demodulated output is sent to amplifier 5.
Output through. Furthermore, intermediate frequency amplification stages 2 and 3
The outputs of are passed through AGC amplifiers 6 and 7, respectively.
In addition to the AGC rectifiers 8 and 9, the rectified outputs are fed back to the gain control terminals of the intermediate frequency amplification stages 2 and 3 through different time constant circuits 10 and 11, respectively, to perform AGC operation.
この回路で前記のフアストアタツク・スローレ
リーズ特性を望む場合には、AGC時定数回路１
０の保持時定数を必要なだけ十分に大きく取つた
ならば、他の時定数回路１１の側は立上り時間の
みでなく保持時定数も極力小さく取るものであ
る。その結果として合成出力において第１図ｃに
示すように、AGC動作の遅れにより波形の立上
り部分にオーバシユートを伴うこと少ない、改善
された波形が得られることが実測された。 If you want the above-mentioned fast attack/slow release characteristics with this circuit, AGC time constant circuit 1
If the holding time constant of 0 is set as large as necessary, the other time constant circuit 11 should be set to have not only the rise time but also the holding time constant as small as possible. As a result, it was actually observed that an improved waveform with fewer overshoots in the rising portion of the waveform due to delays in the AGC operation was obtained in the synthesized output, as shown in Figure 1c.
以上に述べたように、本考案はAGC時定数の
異る複数のAGC付増幅回路を並列に設けて、そ
の出力を合成することにより、SSBやCWの急激
な変化に対応し、かつ、充分なAGCをきかせる
ことが出来るので実用上の効果は大きい。
As described above, the present invention provides multiple amplifier circuits with AGC with different AGC time constants in parallel and combines their outputs to cope with rapid changes in SSB and CW, and to provide sufficient It has a great practical effect because it allows you to use AGC.
第１図はAGC動作と出力波形図で、第２図は
本考案の一実施例を示すAGC回路のブロツク図
である。
１……ミクサ、２，３……中間周波増幅段、４
……復調器、５……低周波増幅器、６，７……
AGC増幅器、８，９……AGC整流器、１０，１
１……時定数回路。
FIG. 1 is a diagram of AGC operation and output waveforms, and FIG. 2 is a block diagram of an AGC circuit showing an embodiment of the present invention. 1... Mixer, 2, 3... Intermediate frequency amplification stage, 4
...Demodulator, 5...Low frequency amplifier, 6,7...
AGC amplifier, 8, 9...AGC rectifier, 10, 1
1...Time constant circuit.
Claims (1)
増幅段を並列に設け各出力を合成して出力すると
共に各増幅段のAGC制御時定数をそれぞれ異な
らしめたことを特徴とするAGC回路。 An AGC circuit for a radio communication device, characterized in that a plurality of signal amplification stages before a detection stage are arranged in parallel, the outputs of each are combined and output, and the AGC control time constants of each amplification stage are made different.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3299083U JPS59154917U (en) | 1983-03-08 | 1983-03-08 | AGC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3299083U JPS59154917U (en) | 1983-03-08 | 1983-03-08 | AGC circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59154917U JPS59154917U (en) | 1984-10-17 |
| JPH0127288Y2 true JPH0127288Y2 (en) | 1989-08-15 |
Family
ID=30163796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3299083U Granted JPS59154917U (en) | 1983-03-08 | 1983-03-08 | AGC circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59154917U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56134811A (en) * | 1980-03-24 | 1981-10-21 | Sony Corp | Gain control circuit |
| JPS57147308A (en) * | 1981-03-06 | 1982-09-11 | Maspro Denkoh Corp | Agc system of multichannel amplifier |
-
1983
- 1983-03-08 JP JP3299083U patent/JPS59154917U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56134811A (en) * | 1980-03-24 | 1981-10-21 | Sony Corp | Gain control circuit |
| JPS57147308A (en) * | 1981-03-06 | 1982-09-11 | Maspro Denkoh Corp | Agc system of multichannel amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59154917U (en) | 1984-10-17 |
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