JPH01270328A - Compound semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the making of low-frequency noise by a method wherein an n-type region is formed on the positions of contact surfaces on a substrate to form a substrate p-type region surrounding the inner surface of the n-type region. CONSTITUTION:The surface of a semi-insulating GaAs substrate 6A is coated with a photoresist 14A, a contact hole 15A is made in a photoresist 14A by etching process and Si ion is implanted through the hole 15A to form an n<+>-type region 13. First, after removing the photoresist 14A, the surface of the substrate 6A is coated with another photoresist 14B, another contact hole 15S is made in the photoresist 14B by etching process and Si ion is implanted through the hole 15B to form another n<+> region 9. Secondly, after removing the photoresist 14B, the surface of the substrate 6A is coated with the other photoresist 14C, the other contact hole 15C is made in the photoresist 14C by etching process, Be ions are implanted through the hole 15C to form a p-type region 10 surrounding the inner surface of the n<+>-type region 9. Finally, a resistor 17A, a MESFET 17B etc. are provided on the surface of the substrate 6A to form insulating layers 18, wirings 19A, 19B and 19C.

Description

[Detailed Description of the Invention] [Table of Contents]! ! ! Important industrial fields of application Prior art (Figure 6) Means for solving the problem to be solved by the invention (Figures 1 and 2.3) Working examples One example (Figure 4.5) ) Effect of extended invention [I! ! [Required] With regard to integrated circuits using compound semiconductor substrates, the purpose is to reduce low-frequency noise contained in output signals without making handling difficult and without reducing the effective depth area. In a compound semiconductor integrated circuit, a part of the wiring batts formed on the substrate contacts the top surface of the substrate, and a negative potential is applied to the contacting wiring with respect to the back surface of the substrate or the ground electrode. An n-type region is formed at the contact surface, and a p-type fn region is formed in the substrate so as to surround the inner surface of the n-type region, or a p-type region is formed at the contact surface of the substrate. In a compound semiconductor integrated circuit that is constructed by forming a tJ substrate, or in which the same potential or a positive potential is applied to the contacting wiring with respect to the back surface of the substrate or the ground W1 pole, an n-type region is provided at the contact surface of the tJ substrate. Form and compose.

[1'! Fields of use on Nu] The present invention relates to an integrated circuit using a compound semiconductor substrate.

``Prior art'' In integrated circuits using compound substrates, especially GaAs substrates, depending on the type of IC and the processing method of the substrate, low-frequency vibration noise of several 10 to 100 Ilz can be generated in the output signal. There is a problem that (GaAs + Ic 5
ysp, TechDig, ! 985, 31-
On page 34, the paper Lov-rraquency oscilla was published by 11i11er and 2 others.
LionGin GmAs lc++).

The cause of this low frequency vibration noise is that the negative first place is marked j11.
It is thought that the substrate current is caused by electrons being injected into the substrate from the contact surface between the wiring and the substrate, and these electrons moving within the substrate.

In other words, electrons injected into the substrate are captured in traps caused by lattice defects in the substrate crystal, then released from the traps due to thermal excitation, move within the substrate, and are captured by the hundred-degree trap. After repeating, it flows into the signal wiring and signal drive element, such as IIESFET, so
It is thought that this causes low frequency vibration noise to be mixed into the external output signal.

Conventionally, the following measures have been considered as methods for preventing the incorporation of such low-frequency vibration noise.

(2) Use a substrate whose thickness is reduced to about 10 μm, and attach a ground electrode to the back surface of the substrate.

The thickness of this board is % the distance from the negative potential t4 source wiring provided on the board to the signal wiring and circuit elements (usually several tens of microseconds)
Because the electrons injected into the GaAg substrate are relatively small, they are absorbed by the grounded Ml pole on the back of the substrate before they flow into the signal wiring or circuit elements (rlEPE TRA
NSACTIO! Is 01 ELEC DING RO! l
DEYICESJ Volume ED-34, No. 6, (19
Paper published by [)] 1ller and 1 other person in June 117) 11echaaismg forL
ow-Freque++cy OseillaLion
g in GaAs PET'g).

6. Also, as shown in FIG. 6, guard rings 4 and 5 are provided on the outer periphery of the circuit element 1 and on the upper surface of the substrate between the wiring 2 to which a negative potential is applied and the signal wiring Ia3, respectively. Electrons 7 injected into the substrate 6 from the signal wiring 3
Alternatively, it is collected by guard ring 4 or 5 at 11t flowing into circuit element 1.

[Problems to be Solved by the Invention] However, the above method (■) reduces the thickness of the compound semiconductor substrate by 1
If it is 0 μ-nlJ11', handling is not easy and n
Not suitable for tfR.

In addition, method (2) requires a relatively large area for arranging the guard ring, which significantly reduces the effective area and hinders high integration.

Therefore, it was hoped that a solution would be proposed that would prevent the occurrence of such a χ point.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a compound semiconductor integrated circuit that can reduce low-frequency noise contained in an output signal without making handling difficult or reducing the effective depth area. It is in.

[Means for Solving the Problems] Figures 1 to 3 are horizontal diagrams of the principles of the inventions 1 to 3, respectively, and show the main part configuration of a compound semiconductor integrated circuit.

In FIG. 1, 6 is a compound semiconductor substrate, for example a semi-insulating Ga
It is an As substrate.

A wiring 2 (including an electrode) is formed on the compound semiconductor substrate B, a part of which contacts the top surface of the compound semiconductor substrate 6, and a negative potential is applied to the back surface of the compound semiconductor substrate or the ground electrode.

S is an insulating layer.

Reference numeral 9 denotes an n-type region, which is formed at the contact surface of the compound semiconductor substrate 6.

IO is a p-type region and is formed in compound semiconductor substrate 6 so as to surround the inner surface of n-type region 9 .

In FIG. 2, 11 is a p-type region, and the compound semiconductor substrate 6
is formed at the contact surface with the wiring 2 to which the negative potential is applied. Other points are the same as those in FIG.

In FIG. 3, I3 is an n-type region, and the compound semiconductor substrate 6
．． It is formed at the contact surface with the wiring 12. The same potential or a positive potential is applied to this wiring 12 with respect to the back surface of the compound semiconductor substrate or the ground electrode. Other points are the same as those in FIG.

[Function] In the compound semiconductor integrated circuit shown in FIG. 1, since a negative potential is applied to the arrangement a2, a reverse voltage is applied to the pn junction, and the depletion layer becomes thick, and the n-type region is 9
The electrons injected into the substrate 6 are bounced off by the potential barrier for electrons formed by the p-type region 10.
injection into the body is prevented. Therefore, the occurrence of the above-mentioned low frequency noise can be significantly reduced.

In the compound semiconductor integrated circuit shown in FIG.
l itself acts as a potential barrier against electrons, preventing injection into the substrate 6.

Therefore, the occurrence of the above-mentioned low frequency noise can be significantly reduced. Although the configuration is simpler than the one shown in Diagram 1, the potential barrier for one child is higher in the configuration shown in FIG.

In the compound semiconductor integrated circuit shown in Fig. 3, n empty region! 3 itself forms a potential well for electrons in the substrate 6. Therefore, when electrons are injected into the substrate 6 from the wiring to which a negative potential is applied, they are absorbed by the n-type region 13, and the above-mentioned low frequency noise can be reduced.

[Example] An example of a compound semiconductor integrated circuit according to the present invention will be described based on the drawings.

(1)-Example FIG. 4 shows a cross-sectional structure of a main part of an iaAs integrated circuit.

FIGS. 5(A) to 5(D) show the manufacturing process of the main parts of this integrated circuit.

The configuration shown in FIG. 4 will be explained below along with the manufacturing process.

(A) A photoresist 14A with low ion beam transmittance is applied to the upper surface of the semi-insulating Ga1 customer substrate 6^, and a contact hole 15A for wiring connection is opened in the photoresist 14A by etching.

Next, Si ions are implanted through this contact hole 15A to form an n° type region 13. The beam energy and dose are, for example, 200 kaV.

There is 3X 1G "Cs-".

CB) Next, after removing the photoresist +4A, similarly apply a photoresist 148f on the upper surface of the semi-insulating GaAg substrate 6A.
Contact holes 15B for interconnection are formed in the photoresist 14B by etching.

Next, Si ions are implanted through this contact hole 15B to form an n9 type region 9. The beam energy and dose m are, for example, 120 keV.

IX I (1"cm-'.

(C) Next, after removing the photoresist 14B, a photoresist 14C is similarly coated on the upper surface of the semi-insulating G5As substrate 6A, and the photoresist 14C is deposited by etching! A contact hole 150 for connection is opened.

The area of this contact hole 15C is the contact hole 1
Contains an area of 5B.

Next, BO ions are implanted through the contact hole 15C to form a p-type region IO so as to surround the inner surface of the n''-type region 9.
form. The beam energy and dose m are as follows:
15OkeV, 2X 10"am-".

(Fig. 4) Next, circuit elements such as a resistor 17A and a l1llESFE are installed on the upper surface of the semi-insulating G1^S substrate 6^.
0th order with T17 n etc., insulation 518, wiring! 9A
% 19I3.19C is formed. For example, the wiring material is A
u, and the insulation H18 is a Sin layer. Also, 20
is a gate electrode made of l5Ix.

Here, the wiring connected above the n' type region +3! The contact surface of 9A has a similar shape to the outer surface 131 of the n'' type region +3, and the area of the contact surface of the wiring +9A is equal to or smaller than the area of the outer surface 131 of the n° type region!3. The contact surface of the wiring +9A is in contact with the outer surface 13 of the n° type region 13 in a manner that it is completely included in the outer surface 13. (not shown), a positive potential is applied.

Further, the area of the contact surface of the wiring 19B is
The area of the outer surface 91 of the n'' type region 9 surrounded by contact in a contained manner. This distribution! 19B includes semi-insulating Ga
The back potential or contact of the As substrate 6^! 11 of the 11α pole
A negative potential is applied to the potential.

Next, the operation of this embodiment configured as described above will be explained.

Record! ! Since a negative potential is applied to 9[1, a reverse voltage is applied to the pn junction below it, and the depletion layer becomes F
X <, and the electrons injected from the configuration 19B into the n'51' region 9 are in the p-type region! 0 is repelled by the potential barrier to the electrons formed by the semi-insulating G
Injection into the aAg substrate 6^ is blocked.

Therefore, since the above-mentioned cause of low frequency noise is removed from the output signal from the circuit element 17B etc., the output signal contains almost no low frequency noise.

Further, since a positive potential is applied to the wiring +9A, a potential well is formed for the electrons in the semi-insulating GaAs group [6^.

Therefore, even if the wiring Ia19 is applied with a negative potential,
If electrons are injected from B into the semi-insulating GaA@substrate 6, they are easily absorbed by the n'' type region 13, and low frequency noise can be further reduced.

When such a compound semiconductor integrated circuit was manufactured and tested, it was possible to reduce low frequency noise to 1/100 or less of the conventional level.

(2) Expansion Note that the present invention includes various other modifications.

For example, n'! ! : Without providing L area 9, this area is
A potential barrier against electrons may be formed as an MfA region.

Moreover, the effect of the present invention can be obtained even if only the n''11 region 9 and either the p-type region IO1 or the n°-type region 13 are formed.

Furthermore, the same potential as the back surface of the semi-insulating GaA@substrate 6A or the ground electrode may be applied to the wiring +9A.

[Effects of the Invention] As explained above, according to the compound semiconductor integrated circuit according to the present invention, a potential barrier against electrons is formed without newly securing a special area to prevent electron injection into the substrate. This eliminates the cause of low frequency noise,
Alternatively, there is no need to newly secure a special area (the injected electrons are collected in a potential well, and there is no need to make the substrate particularly thin, so handling is not difficult, and a guard ring etc. is installed on the chip surface). Since it is not necessary to provide this, it has the excellent effect of reducing low frequency noise contained in the output signal without reducing the area on the chip surface.

[Brief explanation of the drawing]

1 to 3 are principle configuration diagrams of a compound semiconductor integrated circuit according to the present invention, FIG. 4 is a vertical cross-sectional structural diagram of a main part of a compound semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 5 (A ) to (C) are main part manufacturing process diagrams of the first embodiment, and FIG. 6 is a diagram showing a conventional method for collecting electrons in a substrate of a compound semiconductor integrated circuit. In the figure, 2.19B is a negative potential application wiring 6, a compound semiconductor substrate 6A is a semi-insulating GaAs substrate 8.18 is an insulating layer 9, +3 is an n-type region (n'' type region 10.11 is a p-type region 14A) -C is photoresist 15A-C is contact, tact holes 16A and 16C are ion beam 17A, 17B is circuit element 2nd Figure 4 "#L'haGaAS base a6A A - Actual 819 early viewing process surface Figure 5

Claims (1)

[Claims] [1] A part of the wiring pattern formed on the compound semiconductor substrate (6) contacts the upper surface of the substrate (6), and the contacting wiring (2) ) In a compound semiconductor integrated circuit in which a negative potential is applied to a back surface or a ground electrode, an n-type region (9) is formed at the contact surface of the substrate (6), and within the n-type region (9) The substrate (6
1. A compound semiconductor integrated circuit characterized in that a p-type region (10) is formed in ). [2] A part of the wiring pattern formed on the compound semiconductor substrate (6) contacts the upper surface of the substrate (6), and the contacting wiring (2) is connected to the back surface of the substrate (6) or the ground electrode. A compound semiconductor integrated circuit to which a negative potential is applied, characterized in that a p-type region (11) is formed at the contact surface of the substrate (6). [3] A part of the wiring pattern formed on the compound semiconductor substrate (6) comes into contact with the upper surface of the substrate (6), and the contacting wiring (12) is connected to the back surface of the substrate (6) or the ground electrode. A compound semiconductor integrated circuit to which the same potential or a positive potential is applied, characterized in that an n-type region (13) is formed at the contact surface of the substrate (6).