JPH01269298A - Sample hold circuit - Google Patents

Abstract

PURPOSE:To obtain the output voltage of high accuracy at a high speed by making a potential change in the prescribed two points of a diode circuit opposite in polarity and equal in quality when operation is switched to sampling to holding. CONSTITUTION:When the potential relation of S<H is obtained between a sample signal terminal S and a hold signal terminal H, sample mode is obtained and in case of S>H, a hold mode is obtained. At the time of a transient condition from the sample to the hold, according to the turning-off of a constant current source T1 and a constant current absorbing circuit T3, diodes D1-D4 are turned off. According to the turning-off of a constant current source T4 and a constant current absorbing circuit T2, respective floating capacity Co of connecting points Va and Vb is charged. This charge is finished by the turning-on of clamp means D5-D8. For the respective potential changes of the points Va and Vb, the polarity is opposite and the quantity is equal. Accordingly, a noise at a transient time is suppressed through floating capacity Cd from an input terminal Vi to an output terminal Vo.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a sample and hold circuit.

[Summary of the Invention] The present invention provides a sample and hold circuit including a) a first connection point Vb to which a constant current source T1 that becomes active in the sample mode and a constant current sink circuit T2 that becomes active in the hold mode are connected; , b) a second connection point Va to which a constant current source T4 that becomes active in the hold mode and a constant current sink circuit T3 that becomes active in the sample mode are connected; (c) the first connection point Vb and the second connection point Vb; A plurality of diode series circuits D1, D2, D3, D4 connected between the connection point Va of and an input terminal V derived from the connection point of the plurality of diodes.
d) a plurality of diode series circuits D1, D2, D3, D4 connected between the first connection point Vb and the second connection point Va;
means for clamping the reverse voltage of D5, D6, D7. D
It is characterized by consisting of 8 parts.

1) In sample mode, constant current lacquer 1 flows from constant current source TI to constant current sinking circuit T3 via multiple diode series circuits Di, D2, D3, and D4, so that the output terminal ■0 is output from input terminal Vi. A signal is transmitted to

2) In the hold mode, the constant current 11 flows from the constant current source T4 to the constant current sink circuit T2 via the clamping means D5, D6, D7, and D8, so that the input terminal vi and the output terminal 0 are separated. .

3) In a transient state from sample mode to hold mode, first constant current source T1 and constant current sink circuit T3 are turned off, and multiple diode series circuits D are turned off.
1, D2, D3, and D4 are turned off, and the constant current source T4 and constant current sink circuit T2 are turned on, and the first connection point Vb
and the floating capacitance fiCc of the second connection point Va is charged.

The stray capacitance Cc is charged by clamping means D5, D6, D7,
The process ends when D8 is turned on.

The clamping voltage Vc of the clamping means is Vc = 2 * I l * T / Cc (where T is the charging time of the stray capacitance Cc), and the potential change at the first connection point Vb is -Vc / 2. The potential change at the second connection point Va is V c /2, which is opposite in polarity and equal in magnitude.
Noise during the sample-to-hold transition from b, V'a is suppressed.

With the above-described configuration, it is possible to prevent a pulse voltage from appearing at the input/output terminals Vi and Vo through the floating capacitance fiCd, and it is possible to generate a highly accurate output voltage.

[Prior Art] An example of a conventional sample-and-hold circuit is shown in FIGS. 1 and 2 of Practical Dimensions Publication No. 61-38159. The sample and hold circuit shown in FIG. 1 drives a guiode bridge with transistors having a differential amplifier configuration. The sample and hold circuit shown in FIG. 2 is an improved example of the one shown in FIG. That is, diode D1. D2, D3,
There is a stray capacitance Cd including the junction capacitance of D4 (guiode bridge), which causes the pulse voltage to leak to the input/output terminals Vi, 0 as an error voltage component. The problem was solved by adding an additional book and changing the load resistance of the transistor in the differential amplifier configuration to a constant current source.

[Problem to be solved by the invention]

However, in the prior art shown in FIG. 2, the connection point Va,
Vb is driven by the input voltage Vi+■f or Vi-Vf (D potential (however, Vf is the forward voltage of the diode). Therefore, in the hold mode, delda■0 = deltaVi*2* A human input signal with a value calculated by Cd/C (where C is the capacitance value of the hold capacitor) leaks from the input terminal Vi to the output terminal Vo.By the way, this occurs in the prior art shown in Fig. Since the value is: delta Vo=delta vi*Cd/C, the prior art shown in FIG. 2 has a problem in that it is degraded by 6 dB compared to FIG. 1.

The present invention is intended to solve these problems, and its objectives are: (1) to prevent the pulse voltage for controlling sample and hold from appearing on the input/output terminals Vi and Vo through the stray capacitance Cd.

2) Preventing leakage of the input signal from the input terminal Vi to the output terminal vO in the hold mode.

3) Make the voltage range in which the output signal can follow the input signal approximately equal to the power supply voltage.

4) Increase the operating speed of sample and hold.

As described above, the object of the present invention is to provide a sample-and-hold circuit that generates a high-speed and highly accurate output voltage.

[Means for Solving the Problems] The sample and hold circuit of the present invention includes: a) a first circuit connected to a constant current source T1 that becomes active in the sample mode and a constant current sink circuit T2 that becomes active in the hold mode; Connection point Vb, b) A second connection point Va to which the constant current source T4, which becomes active in the hold mode, and the constant current sink circuit T3, which becomes active in the sample mode, are connected.
, (c) a plurality of diode series circuits D1 . connected between the first connection point Vb and the second connection point Va. D2, D3,
D4 and a diode bridge consisting of an input terminal Vi and an output terminal ■0 derived from the connection point of the plurality of diodes; and d) a plurality of diode bridges connected between the first connection point Vb and the second connection point Va. Diode series circuit D1, D2, D3, D4
means for clamping the reverse voltage of D5, D6, Dl, D
It is characterized by consisting of 8 parts.

[For use] According to the above configuration of the present invention, 1) In the sample mode, a constant current is supplied from the constant current source Tl to the constant current sink circuit T3 via the plurality of diode series circuits D1, D2, D3, and D4. As the lacquer l flows, a signal is transmitted from the input terminal Vi to the output terminal VO.

2) In the hold mode, a constant current II flows from the constant current source T4 to the constant current sink circuit T2 via the clamping means D5, D6, Dl, and D8, so that the input terminal Vi and the output terminal vO are separated.

3) In a transient state from sample mode to hold mode, first constant current source T1. As the constant current sink circuit T3 turns off, a plurality of diode series circuits D
1, D2, D3, and D4 are turned off, and the constant current source T4 and constant current sink circuit T2 are turned on, and the first connection point Vb
and the respective stray capacitances Cc of the second connection point Va are charged.

The stray capacitance Cc is charged by the clamping means D5. D6, Dl,
The process ends when D8 is turned on.

The clamp voltage Vc of the clamping means is Vc=2*11*T/Cc (where T is the charging time of the stray capacitance Cc).The potential change at the first connection point Vb is -Vc/2, The potential change at the second connection point Va is V c /2, which is opposite in polarity and equal in magnitude.
Noise during the sample-to-hold transition from b, Va is suppressed.

[Embodiment] FIG. 1 is a circuit diagram of a sample and hold circuit in an embodiment of the present invention. Tl, T4, Tll, T14, T21
．． T24 is P N, P l-transistor, T2, T3,
T12, T13, T22, and T23 are NPN l-transistors, which will be abbreviated as transistors below unless necessary for the explanation. Dl, D2, D3, and D4 are diodes that constitute a diode bridge, and D5, D6, Dl, and D8 are diodes that are means for clamping the reverse voltage applied to the diode bridge. ■+ is a positive power supply, ■- is a negative power supply, and 11 is a constant current source. vi is an input terminal.

■0 is the output terminal, Vb, Va are the first and second connection points, C
is a hold capacitor, S is a sample signal terminal, and H is a hold signal terminal.

1) Sample mode When the potential relationship between the sample signal terminal S and the hold signal terminal H is set to S>H, the sample mode is activated.

The current of constant current source 1 flows through transistors T23 to 721, and then flows through transistors T21. A current value 11 flows from transistor Tll of the current mirror circuit composed of transistors T11 and Tl to T13, and a current value of 11 flows from transistor T3 of the current mirror circuit composed of transistors T13 and T3 (constant current sink circuit that becomes active in sample mode) to multiple diodes. A signal is transmitted from the input terminal Vi to the output terminal Vo by a current value 11 flowing through the series circuits D1, D2, D3, and D4 to the transistor (constant current source that becomes active in the sample mode) Tl.

2) Hold mode When the potential relationship between the sample signal terminal S and the hold signal terminal H is set to S<H, the hold mode is activated.

The current of constant current source ■1 flows from transistors T22 to T24, and the current value It flows from transistor T14 to 712 of the current mirror circuit composed of transistors T24, T14, and T4, and the current value It flows from transistor T14 to 712, and the current mirror circuit composed of transistors T12 and T2. from the transistor (constant current sink circuit that becomes active in hold mode) T2 to the diode (
Means for clamping the reverse voltage of a plurality of diode series circuits D1, D2, D3, D4) D5, D6, D7, D8
A current value 11 flows through the transistor (constant current source that becomes active in the hold mode) T4, thereby separating the input terminal Vi and the output terminal VO.

Next, the transient state from the sample mode to the hold mode will be explained using FIG.

FIG. 2 is a circuit diagram for explaining the principle of the sample and hold circuit of the present invention. Switch S1 and constant current source 1
Constant current source Tl becomes active in sample mode by switch S2 and constant current source 1, constant current sink circuit T2 becomes active in hold mode by switch S3 and constant current source 11, constant current sink becomes active in sample mode by switch S3 and constant current source The circuit T3, the switch S4, and the constant current source (1) each provide a constant current source T4 that becomes active in the hold mode.

Capacitor Cd is a stray capacitance including junction capacitance of diodes D1 to D4. Capacitor CC is connected to the first connection point V
b and the second connection point Va (collector capacitance of a transistor, etc.), and a separate capacitor may be provided in parallel to set the operating constant.

3) From sample mode to hold mode In FIG. 2, switch S1. As S3 turns off, the bias electric lacquer 1 of diodes D1, D2, D3, and D4 is cut off, and as switches S2 and S4 turn on, the first
The stray capacitances Cc of the connection point Vb and the second connection point Va are charged.

The charging of the floating capacitance Cc ends when the connection points Va and Vb reach a potential difference that turns on the clamping means D5 to D8. The clamping potential difference Vc of the clamping means is Vc=2*I l *T/Cc (where T is the charging time of the stray capacitance Cc), and if the forward voltage of the diode is Vf, then Vc= N*Vf (where N is the number of diodes connected in series as the clamping means), and in FIG. 1.2, N=4. In addition, the change in potential of the contact points Va and Vb when changing from the sample mode to the hold mode is ±(Vc+Vf).The change in potential of the 1.2 connection points Vb and Va is opposite in polarity. Since the sizes are equal, the first and second connection points V connect to the input terminal Vi and the output terminal Vo via the stray capacitance Cd.
Noise during the sample-to-hold transition from b, Va is suppressed.

In addition, in the hold mode, as shown in FIG. 2 of the prior art, the connection points Va and Vb are not driven by the potential of the input voltage Vi+Vf or Vi-Vf, so the input signal from the input terminal Vi to the output terminal vO is also Its value is: Delta Vo=Delta Vi*Cd/C. For this reason, we have improved both the characteristics during sample-hold switching and the characteristics during hold. That is, it is possible to prevent a pulse voltage or an input signal from appearing at the output terminal Vo through the stray capacitance Cd, and to generate a highly accurate output voltage.

The current mirror circuit used in Fig. 1 may be a Wilson current mirror circuit, for example, and the current ratio of the current mirror circuit does not have to be 1, with a constant current source active in the sample mode and a constant current source active in the hold mode. The current ratio of the constant current source may be other than 1, and it is advantageous to set the switching time to the sample mode or the hold mode to different times.

Therefore, the operation time during sample hold can be set arbitrarily, and the operation speed during sample hold can be increased.

For example, by doubling the transistor size of transistors T1 and T3 and setting the value of the constant current source to 2 * 1, the operating speed during sampling can be doubled during hold. The voltage range that the output signal can follow is from [positive power supply voltage V+) - (collector saturation voltage) - vf to (negative power supply voltage V-) + (collector saturation voltage) - Vf, so it is almost the power supply voltage. equals range.

FIG. 3 is a circuit diagram of a sample and hold circuit according to another embodiment of the present invention.

In FIG. 3, the transistors Tl01T20 . A buffer amplifier is configured using T30 and T40 in sample mode.

Additionally, Zener diodes D9 and DI are used as clamping means.
Since OIDll is used, the clamp potential difference Vc is as follows: Vc=N*Vz (where Vz is the Zener breakdown voltage of the Zener diode), and the number N of diodes connected in series is required to be three or more. If it is configured with N=2, the guide bridges D1 to D4 and the transistors Tl01T20, T30, T
Zener diodes with uniform forward voltage and forward directionality between the 40 pace emitters are required.

[Effects of the Invention] As described above, the present invention has the following effects.

l) When switching operation from sample to hold,
Since the potential changes at the first connection point Vb and the second connection point Va have opposite polarities and are equal in magnitude, the pulse voltage that controls sample and hold appears at the input/output terminals Vi and Vo through the stray capacitance Cd. This prevents this and generates a highly accurate output voltage.

2) Even if the characteristics of 1) above are improved, as in the conventional technology,
In hold mode, input terminal Vi to output terminal Vo
The leakage of input signals to the input signal does not increase.

3) The voltage range in which the output signal can follow the input signal is approximately equal to the power supply voltage.

4) Since the operating currents for each of the sample operation and hold operation can be set arbitrarily, it is easy to increase the operation speed of the sample and hold operation.

As described above, a sample-and-hold circuit that generates a high-speed and highly accurate output voltage can be provided.

Further, the present invention can be used as a simple analog switch, and is also effective as a reset switch during the integration period, for example.

Since the present invention makes extensive use of current mirror circuits, it is also suitable for integrated circuits.

According to the present invention, even if a plurality of current mirror circuits are provided in parallel and a plurality of sample and hold circuits are provided, only one set of transistors T21 to T24 for controlling the sample and hold is required.Especially in the embodiment shown in FIG. (
This eliminates the need for input/output (both input and output), making it convenient for integrating many analog switches onto one chip.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the sample and hold circuit of the present invention. FIG. 2 is a circuit diagram for explaining the principle of the sample and hold circuit of the present invention. FIG. 3 is a circuit diagram of another embodiment of the sample and hold circuit of the present invention. T1. T4... Constant current sources T2, T3... Constant current sink circuit Vb... First connection point Va... Second connection points D1 to D4... Multiple diode series circuit Vi
...Input terminal Vo ...Output terminals D5 to D8...Means for clamping Applicant: Seiko Epson Corporation

Claims (1)

[Claims] (a) A first connection point Vb to which a constant current source T1 that becomes active in sample mode and a constant current sink circuit T2 that becomes active in hold mode are connected; (b) Hold mode (c) between the first connection point Vb and the second connection point Va, to which a constant current source T4 that becomes active in sample mode and a constant current sink circuit T3 that becomes active in sample mode are connected; A plurality of diode series circuits D1, D2, D3, D connected to
4 and a diode bridge consisting of an input terminal Vi and an output terminal Vo derived from the connection point of the plurality of diodes; and (d) a plurality of diode bridges connected between the first connection point Vb and the second connection point Va. Diode series circuit D1, D2, D3, D
means D5, D6, D7, for clamping the reverse voltage of 4;
A sample and hold circuit comprising D8.