JPH01268307A - Channel selecting device - Google Patents

Channel selecting device

Info

Publication number
JPH01268307A
JPH01268307A JP9551188A JP9551188A JPH01268307A JP H01268307 A JPH01268307 A JP H01268307A JP 9551188 A JP9551188 A JP 9551188A JP 9551188 A JP9551188 A JP 9551188A JP H01268307 A JPH01268307 A JP H01268307A
Authority
JP
Japan
Prior art keywords
division ratio
frequency
voltage
frequency division
frequency divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9551188A
Other languages
Japanese (ja)
Inventor
Tsugio Itagaki
次雄 板垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9551188A priority Critical patent/JPH01268307A/en
Publication of JPH01268307A publication Critical patent/JPH01268307A/en
Pending legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To stably execute the reception against a variation of a receiving frequency by varying a frequency division ratio of a frequency divider by synchronizing with a vertical synchronizing signal. CONSTITUTION:For instance, in case a receiving channel is shifted to the lower side against a normal frequency, a controller 3 judges whether an output voltage of an AFC circuit 5 exceeds a threshold for some prescribed period or not, and if said voltage exceeds, the controller detects a signal from a vertical synchronization generator 13, and raises a frequency division ratio of a variable frequency divider 7 by '1' synchronously in an edge or output period of its signal. Such a procedure is repeated, and when an AFC output voltage becomes between the first and the second threshold voltages, the variation of the frequency division ratio of the variable frequency divider 7 is stopped. In such a way, since the timing for varying the frequency division ratio is executed in a vertical blanking interval, a disturbance on a screen can be reduced.

Description

【発明の詳細な説明】 〔殖東上の利用分野〕 本発明は、テレビ受f8愼寺に使用されるyI!4局装
置に関し、特にpLL周波数シンセサイザ方式を用いた
選局装置に関するものである。
[Detailed Description of the Invention] [Field of Application of Shokutojo] The present invention is applied to the yI! The present invention relates to a four-station device, and particularly to a channel selection device using a pLL frequency synthesizer method.

〔従来の孜術〕[Traditional Keijutsu]

従来の装置は、特公昭56−45524  号に配植の
ように、受信周波数を微調しようとする場合、単VcA
FC回路の出力電圧に応答し℃可変分周器の分周比を可
変する方式を採るのが一般的であった。
Conventional devices use a single VcA when attempting to finely tune the receiving frequency, as was the case in Japanese Patent Publication No. 56-45524.
It has been common practice to vary the frequency division ratio of the °C variable frequency divider in response to the output voltage of the FC circuit.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術は、可変分周器の分周比を可変するタイミ
ングについてはFUt 141.がされておらず、通常
の受1g状態で受信周波数を補正した場合、すぐに応答
してしまい、画面上で横縞寺の妨害が出たり、分周比を
短時間に上下に変化してしまういわゆるハンチング塊成
が生じてしまうといつ問題かあった。符に衛星放送受傷
の場合、座外のコンバータユニットで一度中間周波数に
震侠する方式では、敵しい県境変化による周i数のドリ
フトを無視できなく、受信周rHL叙の補正回数が多く
なり、また梵送彼のf調方式がFM方式のため受信周波
数を変化させた場合画面上で妨害か見えやすいなどの問
題があった。本発明の目的は、かかる従来技術の欠点を
除去し、受信周波数の変化に対して安定に受信できるi
!4@鉄直を提供することにある。1〔課題を解決する
ための手取〕 上記目的達成のため、本発明では、受信した信号の垂直
同期毎号または垂直同期パルスを発生する垂直同期発生
回路とAFC回路の出力を連続釣に監祝し、その出力レ
ベルがある一定のスレッシホールド電圧を一定期間に殴
って越えているか否かを判断する手段と垂直同期信号に
同期して分周器の分周比を一度化させる手段を備えた。
In the above-mentioned conventional technology, the timing for varying the frequency division ratio of the variable frequency divider is determined by FUt 141. If this is not done and the receiving frequency is corrected under normal receiving conditions of 1g, it will respond immediately, causing horizontal interference to appear on the screen, or changing the frequency division ratio up or down in a short period of time. There was always a problem when so-called hunting agglomeration occurred. In the case of satellite broadcasting damage, using a method in which the converter unit outside the station vibrates to the intermediate frequency once cannot ignore the drift of the frequency i due to changes in the prefectural border, and the number of corrections for the reception frequency RHL increases. Furthermore, since Bonshō's f-key system was an FM system, there were problems such as interference being easily visible on the screen when the receiving frequency was changed. It is an object of the present invention to eliminate the drawbacks of the prior art and to enable stable reception against changes in reception frequency.
! 4@Providing direct service. 1 [Measures for solving the problem] In order to achieve the above object, the present invention continuously monitors the output of a vertical synchronization generation circuit and an AFC circuit that generate each vertical synchronization issue of a received signal or a vertical synchronization pulse. , means for determining whether the output level exceeds a certain threshold voltage in a certain period of time, and means for making the frequency division ratio of the frequency divider equal to one in synchronization with the vertical synchronization signal. .

〔作用〕[Effect]

受信周波数か変化した場合、AFC回路は、変化した周
tL数に相当する電圧を出力する。その電圧が、ある一
定のスレッシ1ホールド電圧を一定期間九渡って越えた
場合は、世@1町期侶勺または垂直同期パルスVC,同
期して分周器の分周比を1だけ変化させる。この時、分
周比を変化させるタイミングか垂直帰線期間内で行なわ
れるため画面上の妨害を軽減できる。
When the receiving frequency changes, the AFC circuit outputs a voltage corresponding to the changed number of cycles tL. If the voltage exceeds a certain threshold 1 hold voltage for a certain period of time, a vertical synchronization pulse or a vertical synchronization pulse VC is used to synchronize and change the division ratio of the frequency divider by 1. . At this time, since this is done at the timing of changing the frequency division ratio or within the vertical retrace period, disturbances on the screen can be reduced.

〔実施例〕〔Example〕

以下、第1図に例示した実施例により、本発明を具体的
に説明する。帛1図において、1は選局用キーボード、
2は偽えは2桁のチャンネル表示装置、6はコン)o−
ラ、4はチューナ、5はAFC回路、6はチ纂−す40
局部発振出力を分周する固定分周器、7は固定分周器6
&Cより分局された局部発掘出力をさらに分周し、コン
トローラ5からの出力により分周比を変えることができ
ろ可変分周器、8は固定分周器6j可震分周器7で分周
された周波数と基準周波数とな比軟し、この周波数か同
じになるように誤差′電圧を出力する位相比較器、9は
位相比較器8の誤走電圧からlt波成分を取り出す低域
フィルタ、1oは羞準発盪器11の出力を分局する固定
分周器、12は前記AFC回路の出力を判別するための
第1及び第2のスレッシュホールド電圧を有するAFC
判別回路、15は党イ9した信号の垂@同期佃号または
垂直同期パルスを発生する垂直同期発生回路、14は映
像@号入力A子である。今、選局キーボード1よりある
チャンネル査号を入力すると、そのチャンネルに相当す
るデータがコントローラ3から可変分周器7に入力され
る。これによって可変分周器7に:a局されたチャンネ
ルに対応した分周比が設定される。
Hereinafter, the present invention will be specifically explained using an example illustrated in FIG. In Figure 1, 1 is the keyboard for tuning,
2 is a fake 2-digit channel display device, 6 is a con)o-
4 is the tuner, 5 is the AFC circuit, 6 is the circuit 40
A fixed frequency divider that divides the local oscillation output, 7 is a fixed frequency divider 6
The frequency of the local excavation output divided from &C is further divided, and the frequency division ratio can be changed by the output from the controller 5.A variable frequency divider, 8 is a fixed frequency divider 6j, and a vibration frequency divider 7 is used for frequency division. 9 is a low-pass filter that extracts the LT wave component from the error voltage of the phase comparator 8; 1o is a fixed frequency divider that divides the output of the photostimulator 11, and 12 is an AFC having first and second threshold voltages for determining the output of the AFC circuit.
15 is a vertical synchronization generation circuit which generates a vertical synchronization signal or a vertical synchronization pulse of the signal that has been input, and 14 is a video signal input terminal A. Now, when a certain channel code is inputted from the channel selection keyboard 1, data corresponding to that channel is inputted from the controller 3 to the variable frequency divider 7. As a result, the frequency division ratio corresponding to the channel assigned to the a channel is set in the variable frequency divider 7.

次いで、固定分周器6.可変分周器71位相比較器8.
低域フィルタ9からなる位相同期ループによるフィード
バーツクにより、チューナ40局部発振周阪数は#J菫
チャンネルに相当する周波数に設定される。
Then fixed frequency divider 6. Variable frequency divider 71 phase comparator 8.
Feedback by the phase-locked loop consisting of the low-pass filter 9 sets the local oscillation frequency of the tuner 40 to a frequency corresponding to the #J violet channel.

このようにして設定された正規周波数に対して、受信チ
ャンネルの周波数がずれ1いる場合について説明する。
A case will be described in which the frequency of the reception channel is shifted by one from the normal frequency set in this manner.

一般に−AFC回路の周波数に対する出力電圧特性は第
2図に示されているように逆S1字形である。ここで受
信チャンネルが正規周波数に対して低目側にすれている
場合、A F CIgIR1I5の出力電圧は第1のス
レッシュホールド電圧VTR&より市くなり受信周波数
をアップしようとする賛求がコントローラ3へ与えられ
る。ここで、AFC出力には一般にリップルが言まれて
おり、これらのリップルにより誤った情檄が与えられる
可能性かある。このため、ある−是期間スレッシュホー
ルドを越えているがどうか判断し、もし越え℃いれは、
次に世直同期発生器13がらの信号を検出し、その信号
のエツジまたは出力期間中に同期して可変分周器70分
周比を1だけアップさせる。
In general, the output voltage characteristic of the -AFC circuit with respect to frequency is an inverted S1 shape, as shown in FIG. Here, if the reception channel is lower than the normal frequency, the output voltage of A F CIgIR1I5 will be lower than the first threshold voltage VTR&, and the request to increase the reception frequency will be sent to the controller 3. Given. Here, ripples are generally said to be present in the AFC output, and there is a possibility that these ripples may give a false impression. For this reason, it is necessary to determine whether a certain period threshold has been exceeded, and if it has been exceeded,
Next, a signal from the serial synchronization generator 13 is detected, and the frequency division ratio of the variable frequency divider 70 is increased by 1 in synchronization with the edge or output period of the signal.

このような手順をくり返し、AFC出力電圧が第1およ
び巣2のスレッシ1ホールド電圧VTM+ *Vri2
の間になると可変分周器70分周比の変化を停止させる
。このようVcして、受信チャンネルが正規周波数に対
して島目仙jにずれていても同様に動作する。なお、最
初の選局動作時は垂直同期信号とは非同期にして、すば
やく周波数のずれを補正し、その後のドリフト等による
周波数のすれに対しては垂直同期信号と同期するような
動作をさせることもできる。第5図は、垂直同期信号(
α1と受信周波数変化(blのタイミング関係を示した
ものである。
By repeating these steps, the AFC output voltage becomes the threshold 1 hold voltage of the first and nest 2 VTM+ *Vri2
When the frequency is between 1 and 2, the variable frequency divider 70 stops changing the division ratio. With Vc in this manner, the same operation will occur even if the receiving channel deviates from the normal frequency to Shimame Senj. In addition, during the first channel selection operation, it should be asynchronous with the vertical synchronization signal to quickly correct frequency deviations, and then synchronize with the vertical synchronization signal in response to frequency deviations due to subsequent drift, etc. You can also do it. Figure 5 shows the vertical synchronization signal (
This shows the timing relationship between α1 and reception frequency change (bl).

〔発明の効果〕〔Effect of the invention〕

本発明によれは、通常の受信状態において受信周波数の
ずれを補正するように受信周波数を変化させても、その
変化させるタイミングが垂直帰線期間内で行なわれるた
め画面上の妨害を軽減できるとともに、補正(glaも
減らすことができる。
According to the present invention, even if the receiving frequency is changed to correct the deviation of the receiving frequency in a normal receiving state, the timing of the change is performed within the vertical retrace period, so that interference on the screen can be reduced. , correction (gla can also be reduced).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
ANC出力電圧変化に対するスレッシ1ホールド電圧の
関係を示す波形図、第3図は王☆部のタイムチャートを
示す図である。
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing the relationship of threshold 1 hold voltage to ANC output voltage change, and Fig. 3 is a diagram showing a time chart of the main part. .

Claims (1)

【特許請求の範囲】 1、チューナの局部発振周波数を分周して、基準発振器
との周波数および位相を比較し、チューナの同調電圧を
制御するPLL周波数シンセサイザ方式を用いた選局装
置において、コントローラ、該コントローラにより分周
比が制御される可変分周器、前記チューナに接続された
AFC回路、前記AFC回路のS字出力を判別するため
に第1及び第2のスレッシュホールド電圧を有するAF
C判別回路、および受信した信号の垂直同期信号または
垂直同期パルスを発生する垂直同期発生回路を具備し、
前記AFC回路の出力電圧が前記第1のスレッシュホー
ルド電圧より高い場合には、前記可変分周器を前記垂直
同期発生回路からの信号のエッジまたは出力期間中に同
期して微調により分周比を上げるように制御し、第1の
スレッシュホールド電圧以下になったとき、前記可変分
周器の分周比の変化を停止させ、一方、前記AFC回路
の出力電圧が第2のスレッシュホールド電圧より低い場
合には、同様に垂直同期信号に同期して分周比を下げる
ように制御し、第2のスレッシュホールド電圧以上にな
ったとき、前記可変分周器の分周比の変化を停止するこ
とを特徴とする選局装置。 2、請求項1に記載の選局装置において、前記AFC回
路の出力電圧がある一定期間第1のスレッシュホールド
電圧より連続して高い場合またはある一定期間第2のス
レッシュホールド電圧より連続して低い場合に、前記可
変分周器の分周比を変化させることを特徴とする選局装
置。
[Claims] 1. In a tuning device using a PLL frequency synthesizer method that divides the local oscillation frequency of the tuner, compares the frequency and phase with a reference oscillator, and controls the tuning voltage of the tuner, the controller , a variable frequency divider whose frequency division ratio is controlled by the controller, an AFC circuit connected to the tuner, and an AF having first and second threshold voltages for determining the S-shaped output of the AFC circuit.
C discrimination circuit, and a vertical synchronization generation circuit that generates a vertical synchronization signal or a vertical synchronization pulse of the received signal,
When the output voltage of the AFC circuit is higher than the first threshold voltage, the variable frequency divider is finely adjusted to adjust the frequency division ratio in synchronization with the edge or output period of the signal from the vertical synchronization generating circuit. and when the voltage falls below a first threshold voltage, the change in the division ratio of the variable frequency divider is stopped, while the output voltage of the AFC circuit is lower than the second threshold voltage. In this case, the frequency division ratio is similarly controlled to be lowered in synchronization with the vertical synchronization signal, and when the voltage exceeds the second threshold voltage, the change in the frequency division ratio of the variable frequency divider is stopped. A channel selection device featuring: 2. In the channel selection device according to claim 1, the output voltage of the AFC circuit is continuously higher than the first threshold voltage for a certain period of time or continuously lower than the second threshold voltage for a certain period of time. A channel selection device characterized in that the frequency division ratio of the variable frequency divider is changed in the case of the present invention.
JP9551188A 1988-04-20 1988-04-20 Channel selecting device Pending JPH01268307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9551188A JPH01268307A (en) 1988-04-20 1988-04-20 Channel selecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9551188A JPH01268307A (en) 1988-04-20 1988-04-20 Channel selecting device

Publications (1)

Publication Number Publication Date
JPH01268307A true JPH01268307A (en) 1989-10-26

Family

ID=14139608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9551188A Pending JPH01268307A (en) 1988-04-20 1988-04-20 Channel selecting device

Country Status (1)

Country Link
JP (1) JPH01268307A (en)

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