JPH01267763A - System for transferring data between processors in parallel processors - Google Patents

Abstract

PURPOSE:To execute the efficient data transfer of one to many, namely, a broadcasting by dividing a transferring destination processor number as sending destination information in a message and adding information to indicate whether the message passes through a message transfer path corresponding to each or not. CONSTITUTION:Corresponding to respective switches to compose the transfer path, a sending destination processor address in the message is divided into a limited number of parts, and means to indicate whether the message passes through the corresponding switches or not are provided for respective divided partial processor address. Consequently, since the fact that the message passes trough a data transfer path related to the corresponding processor address can be known, the message can be sent to a sending destination processor without executing a redundant data transfer and making an error at the time of broadcasting. Thus, even in the case of the transfer path between processors in which the transfer path of the message is not uniquely specified, the data transfer between all processors, namely, the broadcasting can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a particularly efficient inter-processor data transfer system in a parallel processor composed of a plurality of processors.

[Conventional technology]

As an inter-processor data transfer method in parallel processors consisting of multiple processors.

A message transfer method is known in which a message is prepared by combining sending optical information such as a destination processor number and data to be transferred, and the message is transferred. Note that the data to be transferred here means data in a broad sense, and is everything other than the sending light information in the message (including, for example, tag information, identification information, etc.).

Issues with message forwarding methods include the following.

(1) Realization of a one-to-multiple data transfer function, a so-called broadcasting function, in which the same data is sent from one processor to all processors. Conventionally, the broadcast function has been realized by using a host computer, such as the University of Tsukuba's FAX.

However, the use of a message transfer method via a network with multiple routes is unknown.

(2) In order to transfer messages efficiently, the length should be kept as short as possible. One solution to this problem is to replace the destination processor number in the message with the source processor number in the inter-processor transfer path.

A system that eliminates the need to have a dedicated source processor number field in a message was published in Japanese Patent Application Laid-Open No. 58-222.
641.

[Problem a that the invention attempts to solve]

The above two problems could only be used in cases where the change of destination address is uniquely determined, such as in a crossbar switch network or an omega network.

For example, for the first problem, as shown in FIG. Assume a parallel processor consisting of

Processor numbers are expressed in binary for simplicity. Transfer a message from processor 0O (200-1) to all processors. In other words, consider the case of broadcasting.
At this time, an example of the structure of the message is shown in FIG. 5, and the fact that field B 211 in message 210 is 1 indicates that this message is in broadcast mode. X area Y
The area also indicates the destination processor number in the case of normal transfer (not in broadcast mode), but has no meaning in the case of broadcast mode (or the source processor number is retained). In FIG. 4, processor 00 (2
The message sent from switch 0 (00-1) is sent from switch 0 (
In order to perform efficient broadcasting via switch 1 (201'-1) and switch 2 (201'-1),
01-3). Each switch connects processor 01 (200-2) to processor 10 (2
00-3), and further sends a message to switch 3. Therefore, switch 3 (201-
4) is switch 1 (200-1) and switch 2 (
Switch 3 (200-2) receives a message, and redundant forwarding is performed.Furthermore, it cannot be determined whether it is necessary to forward the message from switch 3 (200-4) to another switch.

A first object of the present invention is to enable data transfer, that is, broadcasting, between all processors even in the case of an inter-processor transfer path in which a message transfer path cannot be uniquely determined.

For the second problem, for example, a parallel processor as shown in FIG. 4 is assumed. Processor 0O (200-1)
Let's consider the case where a message is to be transferred from the processor 11 (200-2) to the processor 11 (200-2).The message is structured as shown in FIG. Used for switching. However, this data transfer path has a loop structure (for example, switch 40 (2
01-1) to switch 0 again via another switch.
), therefore, it is not possible to replace the X area and Y area with the source processor number on the network.

A second object of the present invention is to make it possible to replace the destination processor address with the source processor address even in the case of an inter-processor transfer path where the change order of destination processor addresses in a message cannot be uniquely determined. That's true.

[Means to solve the problem]

The above two objectives are to divide the destination processor address in a message into a finite number of pieces corresponding to each switch that makes up the transfer route, and to check whether each divided partial processor address has passed through the corresponding switch. This is achieved by providing a means to indicate whether the

[Effect]

For the first purpose, by providing a means to indicate whether a message has passed through a switch or not, it is known that a message has passed through a data transfer path related to its corresponding processor address, thereby eliminating redundant data transfer during broadcasting. There is nothing to do. Furthermore, for the second purpose, it is possible to distinguish whether the corresponding processor address is a destination processor address or a source processor address. Furthermore, since it is known that the data transfer path related to the corresponding processor address is being passed, the message can be sent to the destination processor without making a mistake.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an embodiment of a parallel processor consisting of a plurality of processors that can transfer information between arbitrary processors via messages using the present invention. In the figure, 1-1 to 1-9 are processors that can each independently process instructions;
5 is a message transferred between processors, and in the message, 5-1 is a B field that specifies broadcasting, and 5-2 or 5-3 are fields that indicate a processor address, where the upper part of the processor address is X and the lower part is Y. Divided into two fields, 5-4 and 5-5 respectively correspond to the upper (assumed as address part Bits 5-6 indicating whether or not are data.

2-1 to 2-9 are relay switches connected to the corresponding processors and also connected to the crossbar switch;
4-1 to 4-3 are Y crossbar switches that perform switching corresponding to the lower part (address part Y) of the processor part, and 3-1 to 3-3 are switching parts corresponding to the upper part (address part X) of the processor part. This shows an X crossbar switch that performs the following.

In this embodiment, first, a case will be described in which a message is broadcast from processor X a Y h.

The structure of a message transferred from processor XaYal-1 to relay switch 2-1 via line QIO is shown in FIG. 7. In message 220, B field 221 indicates that this message transfer is in broadcast mode. ,X
Since the mode is broadcast mode, the transfer destination processor address is not necessary, and the Y field indicates the transfer source processor address X a Y a from the beginning. x and y
Fields 224 and 225 also indicate that this message has not passed through the X and Y crossbar switches, respectively.

The message arrived at relay switch 1-1.

For efficient broadcasting, it is sent to the X crossbar switch 3-1 via line Q18 and to the Y crossbar switch 4-1 via 1iAQ20. The message on line 018 is shown in FIG. 8, compared with the message in FIG.
Change field 234 from 0 to 1. This is to indicate that the message broadcast by the X crossbar switch 3-1 is erroneously transferred again to the X crossbar switch 1-1 from the relay switches 2-4 to 2-7. On the other hand, the message on line 1220 is shown in FIG. 9, compared to the message of FIG.

The X field 244 and the Y field 245 change from 0 to 1. This means that the message broadcast by the Y crossbar switch 4-1 is sent to the relay switch 2-2.
This is to indicate that the message is erroneously transferred to the X crossbar switch or the Y crossbar switch again from 2-3. Note here that there is no need to forward messages to the X crossbar switch as well as the Y crossbar switch.

Messages that pass through the Y crossbar switch are broadcast,
It is sent to relay switch 22 and relay switch 23.

As shown in FIG. 9, the message that has arrived at the relay switch 22 has both -Xv''j fields set to 1, so the message is sent to the corresponding processor 1-2 without being forwarded to either the X or Y crossbar switch. Then, the relay switch 2-3 also sends a message only to the corresponding processor 1-3.

On the other hand, the message that has passed through the X crossbar switch is broadcast and sent to relay switch 2-4 and relay switch 2-7. As shown in FIG. 8, the message arriving at relay switch 2-4 has an X field of 1, so it is called an X crossbar switch.

Send a message to the corresponding processor 1-4.

Similarly, the relay switch 2-7 also has the X crossbar switch 4.
-3 and the corresponding processor 1-7.

Furthermore, Y crossbar switch 4-2.4-3 operates simultaneously with Y crossbar switch 4-1, and relay switch 2-5.2-6.2-8 broadcasts messages from them.
and 2-9 is the relay switch 2-2 explained earlier.
The same operation as above is performed for each corresponding processor.

Next, from processor X a Y a to processor X b
The case where a message is transferred to Yb will be explained.

From processor XaYal 1 via line Q10.

The configuration of the message to be transferred to relay switch 2-1 is
In the message 250 shown in Figure 0, B field 2
51 is 0, indicating that this message is a normal transfer, not a broadcast, and the X and Y fields actually indicate the transfer destination processor address X b Y a.

A zero in the X and X fields 254,255 indicates that the message has not yet passed through the X and Y crossbar switches, respectively.

Message 5 is sent to relay switch 2-1 via 1210.
sent to.

The relay switch 2-1 determines whether the upper processor address X and lower processor address Y indicate the destination or the source (that is, whether the processor address has passed through the X crossbar switch or the Y crossbar switch). Based on the information, the message is sent to the X crossbar switch, Y crossbar switch, or processor.

In Figure 1, the source processor address X a Y a
Since only the upper X of the processor address differs between the destination processor address XbYa and the destination processor address XbYa, the relay switch transfers the message 5 to the X crossbar switch 4-1 via the line Q12. The message at this time is shown in FIG. 11, where the X field 264 is changed from 0 to 1. This indicates that it has been decided that the message 260 will pass through the crossbar switch X. When the message 260 is input to the X crossbar switch 4-1, it is switched using the upper Output. At this time, the message is as shown in FIG. 12, where the upper X field 272 of the processor address is the destination processor address
to the source processor address X&.

Next, message 270 is input to relay switch 2-7. In the relay switch 2-7, the X field 272 and Y field 272 indicate that the upper and lower processor addresses in the message 270 indicate the upper and lower processor addresses of the source and destination processors, respectively.
This is because the fields 273 are 1 and O, respectively. The message is therefore sent via line Q17 to the destination processor X b Y a.

Processor X b Y a that received the data checks the processor address X field and Y field in the received message, and the processor X a that sent the message.
You can know that Y a.

Details of the relay switch and the X crossbar switch will be shown below.

First, FIG. 2 shows the detailed configuration of the relay switch. In the figure, 40 to 42 are input registers, 46 and 47 are registers that hold the upper X & of the processor address X a Y a of the processor connected to the relay switch in FIG. 2, and 48 and 49 are the registers that hold the lower Y a 50 to 53 are comparison circuits, and 56 to 59 are inverter circuits.

63 is a priority order determining circuit for switching; 38
40 to 40 are selectors, and 41 to 43 are output registers.

In this embodiment, the relay switch 2-1 is used, and the same applies to other relay switches.

Messages sent from processor X a Y a via line Qll are set in input register 40;
During the message, the upper X field 40-2 of the destination processor address is compared with register 46 and the result of a match is sent to priority ordering circuit 63 via line Q71.
sent to. Similarly, the lower Y field 40-3 of the source processor address is compared with register 48, and the result of whether or not they match is sent to priority order determining circuit 63 through line 1272. Further, a B field 40-1 indicating whether or not to broadcast the message is sent to the order determining circuit 63 through Q70.

The message sent from the X crossbar switch via Mfl19 is set in the input register 19.
In the message, the high-order X field 41-2 of the processor address is as follows: bit 41-4 indicates 1;
The lower Y field 41-3 of the 6 processor addresses indicating the upper order of the source processor address is in register 4.
7, and bits 41-5 (whether or not everything has passed through the Y crossbar switch, that is,
(indicating whether the lower Y field 41-3 of the processor address means the destination or the source) is negated and the result is sent to the priority order determining circuit 63 via 1Q74.

The message sent from the Y crossbar switch via line Q21 is set in the manual register 42. In the message, the lower Y field 42-3 of the processor number is as shown by bit 42-5 indicating 1. Shows the lower part of the source processor address. The upper X field 42-2 of the processor address is compared with the contents of the register 49, and the upper X field 42-2 of the processor address (indicates whether it means the source or the source),
The result is sent to the priority order determining circuit 63 via McQ76.

Control signals on line Q71 and line Q76 indicate whether the message on input register 4o and the message on input register 42, respectively, need to be routed to the X crossbar switch.

Control signals on lines 11172 and Q74 indicate whether the messages on input register 40 and input register 41, respectively, need to be routed to the Y crossbar switch.

Line Q70. Line Q73. Line Q75 feeds the contents of the B field indicating the broadcast of input registers 40-42, respectively.

If the B field is 1, the information in the x and y fields is ignored.

Priority order circuit 63 connects lines Q70 to t? , Q76 as input, and selector 60 through line Q77.
Or change the selector 62°.

The priority order circuit 63 is similar to the priority order circuit in a normal crossbar switch. However, there are restrictions on the path from the input register to the output register.

A flowchart of the priority order circuit 63 is shown in FIG.

The message selected by the selector 60 is sent to the output register 4.
Set to 3. During this message.

Processor number fields 43-2 to 43-3 indicate the source and are connected to processor X a Y via line Q11.
Sent to a.

The message selected by the selector 61 is sent to the output register 4.
Set to 4. During this message.

Bit 42-4 indicates 1, indicating that processor number X field 42-2 is the source processor address when the message is input to the primary relay switch via the X crossbar switch.

The message selected by the selector 62 is sent to the output register 4.
Set to 5. In this message, bits 45-5
indicates 1, indicating that the processor address Y field 45-3 is the source processor address when the message is input to the primary relay switch via the Y crossbar switch.

When a message in broadcast mode (B field is 1) is input from line Q10, selector 61 is input from line Q77.
and 62 are selected. At this time, in order to avoid redundant transfers, lines Q78. Set one side of line f179 to O and the other to 1
6 Figure 3 shows the detailed configuration of the X crossbar switch 6 In this embodiment, the X crossbar switch 3-1 is shown, but the same applies to the other X crossbar switches 6 In Figure 3, 80 to 82 are input Registers 86 to 88 hold the higher order of the processor address of the input light corresponding to the input registers; 92 is a priority order determining circuit;
9 to 91 are selectors, and 83 to 85 are output registers.

Among the messages set in input register 80, the upper X field 80-2 of the destination processor address is sent to priority order determining circuit 92 via line Q101 as a switching address.

Similarly, for messages set in other input registers 81 and 82, the upper X fields 81-2 and 82-2 of the destination processor address are connected to the line Q10.
3 to mQ105 to the priority order determining circuit 92.

Furthermore, the contents of B fields 80-1 to 82-1 indicating broadcasts in input registers 80 to 82 are sent to the priority order determining circuit. If the B field is 1, the information in the X field is ignored.

The priority order determining circuit 92 is similar to the priority order determining circuit in a normal crossbar switch.

The flowchart of the operation of the priority order determining circuit 92 is shown in the fourteenth
As shown in the figure.

Messages 80 to 82 on the input registers are sent to selectors 89 to 91, but at this time, the high-order X fields 80-2 to 82-2 of the processor address in the message are the high-order processor numbers of the transfer source processor number corresponding to the input register, respectively. are replaced with registers 86 to 88 that hold .

Therefore, the messages on output registers 83-85 are respectively
2 to 85-2 indicate the source processor address.

The Y crossbar switch can also be configured in the same way as the X crossbar switch.

Although this embodiment shows a case where there are two data transfer paths using an X crossbar switch and a Y crossbar switch, the present invention can also be applied to a case where there are two or more arbitrary data transfer paths.

〔Effect of the invention〕

According to the present invention, in a parallel processor composed of a plurality of processors connected by a data transfer path having a plurality of paths, a bit indicating whether or not the data transfer path has been passed is provided. One-to-many data transfer, that is, broadcasting, can be performed. Furthermore, it is possible to divide the processor address field in a message into multiple parts and distinguish whether each field indicates part of the destination processor address or part of the source processor address, so information about the source processor address can be included in the message. Even if you want a message, there is no need to have a dedicated field and there is no need to increase the message length too much.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a parallel processor to which the present invention is applied, FIG. 2 is a diagram showing details of a relay switch, FIG. 3 is a diagram showing a detailed configuration of an X crossbar switch, and FIG.
The figure shows an example of a parallel processor to which the present invention is applied;
5 to 12 are diagrams showing examples of messages transferred by the device shown in FIG. 1, FIG. 13 is a diagram showing the flowchart of the operation of the priority order circuit, and FIG. 14 is a diagram showing the flowchart of the operation of the priority order circuit C.
It is a figure which shows the flowchart of operation|movement.

Claims (1)

[Claims] 1. A plurality of processors, a message including destination information such as a destination processor number and data to be transferred, and a message transfer path having a plurality of paths connecting the processors; and the message. In a parallel processor equipped with a message transfer means that transfers data between processors using An inter-processor data transfer method for parallel processors, characterized in that information indicating whether or not the data is transferred is added. 2. In claim 1, a message is provided with means for specifying a broadcast mode in which the message is transferred to all processors, and when the broadcast mode is specified, the message transfer path is passed through. An inter-processor data transfer method for parallel processors characterized by manipulating information indicating whether or not a message has been sent to a transfer destination processor multiple times. 3. A parallel processor according to claim 1, characterized in that each message transfer path has means for replacing a message transfer path output address in a corresponding message with a message transfer path input address. data transfer method. 4. In claim 1, n = n element processors constituting a parallel processor.
Factorize into n_1×n_2×...×n_n, arrange element processors on an n-dimensional lattice space where each of these factors is the number of lattice points on one side, connect each side with a crossbar switch, and transfer messages. An inter-processor data transfer method for parallel processors, characterized in that a route is configured and information indicating whether or not the message transfer route has been passed is added corresponding to a crossbar switch of each dimension. 5. In claim 4, a message is provided with means for specifying a broadcast mode in which the message is transferred to all processors, and when the broadcast mode is specified, the message transfer path is passed through. Based on the information indicating whether or not it has been broadcast, the crossbar switches in k directions that have not yet been broadcast are determined, and for those crossbar switches, as shown below, ▲ mathematical formulas, chemical formulas, tables, etc. ▼ ▲ There are mathematical formulas, chemical formulas, tables, etc. ▼ By rewriting the information indicating whether or not the message has passed through the message transfer path and sending the message, it is possible to prevent the message from reaching the transfer destination processor multiple times. A data transfer method between processors of parallel processors. 6. A parallel processor according to claim 4, characterized in that each message transfer path has means for replacing a message transfer path output address in a corresponding message with a message transfer path input address. data transfer method.