JPH01258447A - Laminated thick film substrate for hybrid integrated circuit - Google Patents
Laminated thick film substrate for hybrid integrated circuitInfo
- Publication number
- JPH01258447A JPH01258447A JP63086527A JP8652788A JPH01258447A JP H01258447 A JPH01258447 A JP H01258447A JP 63086527 A JP63086527 A JP 63086527A JP 8652788 A JP8652788 A JP 8652788A JP H01258447 A JPH01258447 A JP H01258447A
- Authority
- JP
- Japan
- Prior art keywords
- stitch
- lands
- adjacent
- chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000007665 sagging Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、裸の半導体チップを搭載し、このチップの電
極と配線パターンのステッチランドとをボンディングワ
イヤで接続して混成集積回路を形成するのに用いる積層
厚膜基板に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is a hybrid integrated circuit in which a bare semiconductor chip is mounted and electrodes of the chip are connected to stitch lands of a wiring pattern using bonding wires. The present invention relates to a laminated thick film substrate used for.
従来の混成集積回路の積層厚膜基板は、第２図（ａ）の
部分平面図、および同図（ａ）のＡ−Ａ断面図の同図（
ｂ）に示すように、印刷された基板の数枚を重ね合せ一
括焼成し、最上層に半導体チップの搭載ランドおよび、
ステッチランド３が設けられているものであった。そし
て、搭載ランド上に裸の半導体チップ（ペアチップ）２
を搭載し、このチップ上の電極と、ステッチランド３と
の間を金のボンディングワイヤ４で接続して混成集積回
路を形成しておった。The laminated thick film substrate of the conventional hybrid integrated circuit is shown in the partial plan view of FIG. 2(a) and the AA cross-sectional view of FIG.
As shown in b), several printed substrates are stacked and fired at once, and the top layer has a land for mounting a semiconductor chip and
It was equipped with three stitch lands. Then, two bare semiconductor chips (pair chips) are placed on the mounting land.
was mounted, and the electrodes on this chip and the stitch lands 3 were connected with gold bonding wires 4 to form a hybrid integrated circuit.
上述した従来の積層厚膜基板では、最上層に搭載ランド
があり、また、ペアチップとの間のボンディングワイヤ
接続用ステッチランドも最上層に設けである。ところが
、端子数の多いペアチップのワイヤポンディングでは、
隣接するステッチランド間に、絶縁に必要な距離をとる
ためには、ステッチランドをペアチップから離れた位置
に設けてステッチランドどうしの間隔を広げるか、スチ
ッチランド自体の幅をせまくするかにより対策をたてて
きたが、前者のペアチップからの距離を長くとると、第
２図（ｂ）のようにボンディングワイヤ４のだれにより
他ワイヤとの接触およびペアチップとの接触などの不良
及び不良予備軍を発生させる原因となり、また、後者の
ステッチランドの幅をせまくすると、自動ワイヤポンデ
ィングにおいて、ステッチランドからはずれてポンディ
ング離れ、あるいはポンディングのルーズコンタクトの
可能性が生じ、やはり、不良あるいは不良予備軍の発生
の元となっていた。In the conventional laminated thick film substrate described above, there is a mounting land on the top layer, and a stitch land for connecting a bonding wire to a paired chip is also provided on the top layer. However, in wire bonding of paired chips with a large number of terminals,
In order to maintain the distance required for insulation between adjacent stitch lands, measures can be taken by placing the stitch lands at a position away from the paired chips to increase the distance between the stitch lands, or by narrowing the width of the stitch lands themselves. However, if the distance from the former paired chip is increased, as shown in Figure 2(b), the sagging of the bonding wire 4 may cause defects and potential defects such as contact with other wires and contact with the paired chip. In addition, if the width of the latter stitch land is narrowed, there is a possibility that the bonding will come off from the stitch land in automatic wire bonding, or a loose contact of the bonding may occur. This was the origin of the military.
本発明の積層厚膜基板は、隣接するステッチランドを積
層基板の異なる層の基板上に設けることにより、従来必
要であったステッチランド間の平面距離を零にすること
ができ、よって、ボンディングワイヤによる接続相手の
半導体チップの方にそれぞれのステッチランドを近付け
ることができ、短いボンディングワイヤでの接続が可能
となって、従来の長いボンディングワイヤのために生じ
た数々の欠点をなくすことができる。In the laminated thick film substrate of the present invention, by providing adjacent stitch lands on substrates of different layers of the laminated substrate, the plane distance between the stitch lands, which was conventionally required, can be reduced to zero, and therefore bonding wires can be reduced. This allows each stitch land to be brought closer to the semiconductor chip to which it is connected, making it possible to connect with short bonding wires, thereby eliminating many of the drawbacks caused by conventional long bonding wires.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第１図（ａ）は本発明の一実施例に半導体チップを搭載
した状態の部分平面図、同図（ｂ）は同図（ａ）のＡ−
Ａ断面図である。第１図（ａ）、 （ｂ）において、上
面に配線パターンが印刷された厚膜基板の５枚が重ね合
わされ一括焼成されて積層厚膜基板が形成されている。FIG. 1(a) is a partial plan view of a state in which a semiconductor chip is mounted on an embodiment of the present invention, and FIG. 1(b) is a partial plan view of A-
It is an A sectional view. In FIGS. 1(a) and 1(b), five thick film substrates each having a wiring pattern printed on the upper surface are stacked and fired at once to form a laminated thick film substrate.
この積層基板の上面の搭載ランドに半導体チップ２がマ
ウントされ、チップ２の電極と基板上のステッチランド
の間はボンディングワイヤ４により接続されている。し
かして、半導体チップ２を囲むようにして形成されてい
る多数のステッチランドは、隣り合うどうしが積層基板
の異なる層に設けられている。すなわち、上層ステッチ
ランド３ａは隣り合う一つ置きに最上層の基板上に設け
られており、ステッチランド８ａに隣接する次層ステッ
チランド８ｂは、最上層基板にあけられている溝穴の底
部に上面を露出した上から２番目の層の基板上の前記露
出部に設けられている。したがって、隣り合うどうしの
ステ、チランド３ａ、３ｂは、ステッチランド間の平面
間隔が不要となり、半導体チップに近付けることができ
るので、ボンディングワイヤも短くて済み、ボンディン
グワイヤの垂れによる接触事故、断線、あるいは寄生イ
ンダクタンスによる性能低下などがなくなる。A semiconductor chip 2 is mounted on a mounting land on the upper surface of this multilayer substrate, and bonding wires 4 connect electrodes of the chip 2 and stitch lands on the substrate. Therefore, adjacent stitch lands are formed so as to surround the semiconductor chip 2, and adjacent stitch lands are provided on different layers of the laminated substrate. That is, the upper layer stitch lands 3a are provided on the uppermost layer substrate every other adjacent stitch land, and the next layer stitch lands 8b adjacent to the stitch lands 8a are provided on the bottom of the groove hole drilled in the uppermost layer substrate. It is provided in the exposed portion on the substrate of the second layer from the top with its upper surface exposed. Therefore, adjacent stitch lands 3a and 3b do not require a planar spacing between the stitch lands and can be brought close to the semiconductor chip, so that the bonding wires can be shortened. Alternatively, performance degradation due to parasitic inductance is eliminated.
以上説明したように本発明は、隣接するステ。 As explained above, the present invention is applicable to adjacent stations.
チランドがたがいちがいに少なくとも２層以上に分かれ
ていることにより全ステッチランドの横の幅の総計が格
段に縮小でき、ボンディングワイヤの長さを短かくする
ことができ、不良発生の要因を根絶し、更にペアチップ
による専有面積を極端に小さくすることができるという
効果がある。Since each stitch land is divided into at least two layers, the total horizontal width of all stitch lands can be significantly reduced, the length of the bonding wire can be shortened, and the cause of defects can be eliminated. Furthermore, there is an effect that the area occupied by the paired chips can be extremely reduced.
第１図（ａ）は本発明の一実施例に半導体チップを搭載
した部分平面図、同図（ｂ）は同図（ａ）のＡ−Ａ断面
図、第２図（ａ）、 （ｂ）はそれぞれ第１図の（ａ）
、 （ｂ）に対応する従来例の平面図と断面図である。
１・・・・・・積層基板、２・・・・・・半導体チップ
、３・・・・・・ステッチランド、３ａ・・・・・・上
層ステッチランド、３ｂ・・・・・・次層ステッチラン
ド、４・・・・・・ボンディングワイヤ。
代理人 弁理士 内 原 音FIG. 1(a) is a partial plan view of a semiconductor chip mounted on an embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. 2(a), FIG. ) are respectively (a) in Figure 1.
, FIG. 7(b) is a plan view and a cross-sectional view of a conventional example corresponding to FIG. 1...Laminated substrate, 2...Semiconductor chip, 3...Stitch land, 3a...Upper layer stitch land, 3b...Next layer Stitch land, 4... Bonding wire. Agent Patent Attorney Oto Uchihara
Claims (1)
ンドおよび前記チップの電極に一端を接続したボンディ
ングワイヤの他端を接続するステッチランドとが設けら
れている積層厚膜基板において、前記ステッチランドは
、隣り合うどうしが段差をもった異なる層の基板に分け
て設けられていることを特徴とする混成集積回路の積層
厚膜基板。In a laminated thick film substrate, the upper exposed surface is provided with a chip mounting land for fixing a semiconductor chip and a stitch land for connecting the other end of a bonding wire whose one end is connected to an electrode of the chip, the stitch land is: A laminated thick film substrate for a hybrid integrated circuit, characterized in that adjacent substrates are separated into different layers with steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63086527A JPH01258447A (en) | 1988-04-08 | 1988-04-08 | Laminated thick film substrate for hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63086527A JPH01258447A (en) | 1988-04-08 | 1988-04-08 | Laminated thick film substrate for hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01258447A true JPH01258447A (en) | 1989-10-16 |
Family
ID=13889462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63086527A Pending JPH01258447A (en) | 1988-04-08 | 1988-04-08 | Laminated thick film substrate for hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01258447A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465882B1 (en) * | 2000-07-21 | 2002-10-15 | Agere Systems Guardian Corp. | Integrated circuit package having partially exposed conductive layer |
-
1988
- 1988-04-08 JP JP63086527A patent/JPH01258447A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465882B1 (en) * | 2000-07-21 | 2002-10-15 | Agere Systems Guardian Corp. | Integrated circuit package having partially exposed conductive layer |
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