JPH01258168A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To evade mismatching of cache memories by transferring lower bits of a virtual address to the other caches to determine an entry where data should be rewritten. CONSTITUTION:A multiprocessor system using caches 2-1-2-N of the write-in system is provided with a means 51 which sends at least lower bits of a virtual address VA, which determines an entry of each of caches 2-1-2-N, to a system bus. Consequently, though data in a certain processor system is rewritten, entries in caches 2-1-2-N of the other processor systems which correspond to said data are determined. Thus, cache mismatching is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiprocessor system, and particularly to a multiprocessor system suitable for avoiding inconsistencies in data in caches connected to each processor. It is something.

(Prior Art) As is well known, in a processor system, data retrieved from memory is first stored in a cache, and data is exchanged between the cache and a processor to process the data. Configured to increase speed.

By the way, MIMD (
Multiple In5truct1 on Mu
In a multiprocessor system using the ltipleData) method, when data at the same address is read from memory by multiple processor systems and the data is registered in the cache of each processor system, the When at least one of the caches rewrites the data, a problem arises in that the data differs in content even though the data has the same address as the data in the other caches (so-called cache inconsistency problem).

Therefore, in this case, it is necessary to rewrite the data in the other cache.

Direct map type or set associative type caches are easy to configure and inexpensive, but because such caches do not solve the cache inconsistency problem, conventional multiprocessor systems do not use content addressable memory devices. C A M (con
tent-addressablemes+ory) is used.

The reasons for this will be explained step by step below.

Caches are classified into two types, real cache and virtual cache, depending on how they are accessed. In other words, accesses by the processor are performed using virtual addresses, whereas accesses to memory are performed using real addresses. Therefore, either the cache is accessed after converting the virtual address to a real address, or the cache is accessed before the conversion. They are classified into two methods depending on how they are accessed.

A real cache is configured so that it can be accessed using a real address after converting a virtual address into a real address, and a virtual cache is configured so that it can be accessed using a virtual address as is. has been done.

In systems using virtual cache, the cache can be accessed while converting virtual addresses to real addresses.
Data can be written to and read from the cache quickly.

On the other hand, caches are classified into two types, write-through type and write-in type, depending on the method of writing to memory.

In a write-through type cache, when data recorded in the cache is rewritten, the data in the memory is also rewritten each time the data recorded in the cache is rewritten.

On the other hand, in write-in cache,
Rewriting data in memory is not permitted, especially when required (
For example, this is performed only when recording data at different addresses within the same entry, when the address space changes, when terminating the processor system, etc.).

In normal processor systems, a write-through cache is often used, but in a MIMD multiprocessor system, when a write-through cache is used, each processor writes to memory more frequently. Therefore, the utilization rate of the bus may increase and the transfer capacity of the bus may decrease.

- In other words, there is no point in configuring a multiprocessor system.

Therefore, in a multiprocessor system, a write-in cache is used.

Here, the configuration of the write-in virtual cache will be briefly explained.

FIG. 5 is a schematic diagram showing an example of the structure of a direct map type cache, which is the simplest type of write-in type virtual caches. In this type of cache, the entry is determined by the lower bits of the virtual address.

In the figure, the storage areas of the cache 20 basically include an area (tag) 21 for storing the upper bits of the virtual address VA, an area 22 for storing data corresponding to the virtual address VA, and an area 22 for storing data corresponding to the virtual address VA. Area 2 for storing dirty bits indicating whether or not
It is composed of 3.

In the cache having the above configuration, when the processor needs data, first, the upper bits of the virtual address VA are output to the comparator 25, and the lower bits of the virtual address VA are used to select the cache entry. is determined, the upper bits of the virtual address VA are read from the area 21 within the entry, and are output to the comparator 25.

When the comparator 25 determines that the upper bits are equal, the data stored in the entry area 22 is read out.

If it is determined that the upper bits are not equal (that is, if the data that the processor desires to read is not stored in the cache 20), the memory is accessed and the corresponding data is read, and at the same time the data and The upper bits of the virtual address VA are stored in the entry determined by the lower bits of the virtual address VA.

When data in the cache is rewritten, a dirty bit is set in the area 23 of that entry. Then, when data of a different virtual address VA is to be stored in that entry, and only the data for which a dirty bit is set is transferred to the memory and rewritten.

By the way, in order to avoid the cache inconsistency problem in a multiprocessor system, when a processor rewrites data in the cache, if data at the same address exists in another cache, it is possible to rewrite the data. is necessary. In this case, each cache is interconnected via the system bus, so in order to check whether the same data as the rewritten data exists in other caches, it is necessary to check the real address. must be done.

Here, if this cache is a virtual cache, each entry stores a real address RA corresponding to the virtual address VA of the data stored in the entry, as shown by the broken line in FIG. It is possible to keep it.

That is, the real address RA converted when accessing the memory can be stored in the area 24.

However, even if the real address RA is stored in advance in this way and the real address RA corresponding to the rewritten data is transferred to another cache, it is not possible to compare it with the real address RA of which entry in that cache. cannot be determined.

In other words, in order to transfer the virtual address VA used for data rewriting to the other cache via the system bus 3, the real address RA must go through a map mechanism (not shown). Although transferred to the other cache, the real address RA must be retranslated into a virtual address VA in order to determine the entry in the cache.

However, since the map mechanism is constituted by a mere table within the shell, even if it can convert a virtual address VA to a real address RA, it cannot convert the reverse.

Therefore, this direct map type cache cannot be applied to a multiprocessor system. The same applies to set-associative caches.

In contrast, in a CAM that stores entries in the order in which they are accessed, regardless of the size of the virtual address VA, a comparator is provided for each entry, so only the real address RA is stored in other caches ( CAM), it can be determined whether the data corresponding to the address RA is stored in the cache.

(Problems to be Solved by the Invention) The above-described conventional technology had the following problems.

That is, as described above, in conventional multiprocessor systems, CAM is used as a cache, but CAM requires a comparator for each entry, so its configuration is extremely complicated.

To be more specific, caches such as the direct map method and the set associative method can be easily configured using, for example, RAM, but CAM requires a complex configuration at least at the LSI level, and if this is When constructed using circuit elements, an extremely large dedicated volume is required.

As a result, the configuration of the multiprocessor system becomes complicated and expensive.

The present invention has been made to solve the above-mentioned problems.

(Means and Effects for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a multiprocessor system using a write-in type cache.
The feature is that at least the lower bits of the data are sent to the system bus.

As a result, even when data in a certain processor system is rewritten, it is possible to determine an entry in another cache corresponding to the data.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a schematic configuration diagram of a multiprocessor system to which the present invention is applied.

In FIG. 2, a plurality of processors 1-1 to 1-N are
Cache (local cache: L) 2-1~
Equipped with 2-N.

In the following description, the processor 1-1 and the cache 2-1, the processor 1-2 and the cache L
2-2, . . . , - processors and caches managed by the processors are referred to as processor systems (processor systems 100-1 to 100-N).

Each of the processor systems 100-1 to 100-N includes:
Each is connected to a memory 4 via a system bus 3.

FIG. 1 is a block diagram of a cache applied to an embodiment of the present invention and its vicinity. In FIG. 1, the same reference numerals as in FIG. 2.5 represent the same or equivalent parts.

This cache is a direct map type and write-in type cache.

In FIG. 1, this cache 2-1 (or 2-2
, ..., 2-N) is basically an area (tag) that stores the upper bits of the virtual address VA.
21, an area 22 for storing data corresponding to the virtual address VA, an area 23 for storing a dirty bit indicating whether the data has been rewritten, and a real address RA corresponding to the virtual address VA.
It is made up of an area 24 for storing.

The virtual address register 51 of the processor 1-1 connected to the cache 2-1 has its predetermined lower bit output line connected to the entry determination signal line of the cache 2-1. Processor 1-1 can use this output line to determine the entry in cache 2-1.

The output line of a predetermined upper bit of the virtual address register 51 and the output line of the area 21 of the cache 2-1 are connected to a comparator 25. The output line of the comparator 25 is connected to the processor 1-1.

The lower bit output line of the virtual address register 51 is also connected to the system bus 3 of the multiprocessor system as a first signal line.

Further, in order to transfer the lower bits of the virtual address VA sent from the first signal line from the system bus 3 to the cache 2-1, a second signal line is connected between the system bus 3 and the cache 2-1. The signal line is connected. In this example, a virtual address register 52 for latching is arranged between the system bus 3 and the carriage L2 1, but it does not need to be provided.

The cache 2-1 also uses the lower bits of the virtual address VA transferred from this second signal line.
The entry is configured such that it can be determined.

In other words, the cache 2-1 is
Entries can be determined at different timings or at the same timing, and data can be read by both the lower bits of the virtual address VA output from the system bus 3 and the lower bits of the virtual address VA transferred from the system bus 3. It is composed of two boats.

The output line of the entry area 24 determined using the second signal line drawn out from the system bus 3 and the output signal line of the real address RA output from the system bus 3 are connected to the comparator 26. There is. The output line of the comparator 26 is connected to the processor 1-1 that manages the cache 2-1.

In the multiprocessor system having the above configuration, when data is to be stored in the cache 2-1, the cache entry is first determined by the lower bits of the virtual address VA output from the virtual address register 51 of the processor. Then, the data (upper bits of the virtual address VA) stored in the area 21 is read from the entry, and compared in the comparator 25 with the upper bits of the virtual address VA output from the virtual address register 51.

If both data are equal, area 2 of the entry
The data in 2 is read out to the processor.

If they are not equal, the virtual address VA is
It is converted into a real address RA by a map mechanism (not shown) and transferred to the memory. Then, data corresponding to the real address RA is read from the memory,
It is stored in the area 22 of the cache in the entry determined by the lower bits of the virtual address VA.

When data in a predetermined entry in cache 2-1 is rewritten to other data as data at the same address,
A dirty bit is written in area 23.

When data in a predetermined entry in the cache 2-1 is rewritten as data at a different address, the data in the entry is output to the memory 4 only if the dirty bit is set in that entry, and the data in the entry is output to the memory 4. The corresponding data in the memory 4 is rewritten. When rewriting data to the memory 4, the virtual address register 51
The lower bits of the virtual address VA are then output to the system bus 3, and at the same time or thereafter, the real address RA corresponding to the virtual address VA is converted by the map mechanism and output to the system bus 3.

Here, when the virtual address VA consists of a virtual page number and a page offset, and the real address RA consists of a real page number and a page offset, the virtual address register 51 outputs the virtual address to the cache for entry determination. Although the lower bits of the address VA must include a page offset signal, the data output to the system bus 3 via the first signal line may not include a page offset signal.

The processors of processor systems other than the processor system in question have a virtual address VA on the system bus 3.
It detects that the lower bit of is output, and after this bit is once taken into the virtual address register 52 and latched, it is output to the cache connected to the processor. The entry of this cache is determined by the lower bits of the virtual address VA, and the real address RA stored in the entry is output to the comparator 26.

The comparator 26 compares the real address RA with the real address RA transferred via the system bus 3.

If the addresses match, the data is retrieved from the cache where the data has been rewritten, and the data is rewritten.

In this way, each processor always monitors whether the lower bits of the virtual address VA are sent to the system bus 3, and the processor that rewrites data in the cache uses the virtual address VA at the time of rewriting.
The lower bits of the data are sent to the system bus 3.

The operation of each processor that monitors whether the lower bits of the virtual address VA are sent to the system bus 3 and rewrites data to avoid cache inconsistency will be further explained with reference to FIG. .

FIG. 3 is a flowchart showing the operation of each processor to monitor the transmission of the lower bits of the virtual address VA and avoid cache mismatch.

In FIG. 3, first in step S1, it is determined whether the lower bits of the virtual address VA are output from the second signal line.

If the lower bits of the virtual address VA are detected, in step S2, the cache entry managed by the processor is determined by the lower bits, and the real address RA is read from the area 24 of the entry.

In step S3, it is determined whether the read real address RA and the real address RA output from the system bus 3 match.

If they do not match, the process ends as is.

If they match, the data is fetched from the cache where the data has been rewritten, and the data in the predetermined entry in the cache managed by the processor is rewritten. After that, the process ends.

FIG. 4 is a functional block diagram of an embodiment of the present invention. In FIG. 4, the same reference numerals as in FIG. 1 represent the same or equivalent parts. Also, in this figure, the functions of only one processor system (processor system 100-1) among the plurality of processor systems are shown.

In FIG. 4, first data rewriting means 61 is means for rewriting data using a virtual address VA output from the processor.

The second data rewriting means 62 is a means for rewriting data using the lower bits of the virtual address VA transferred from the system bus 3 and the real address RA in order to avoid cache mismatch.

By the first data rewriting means 61, the cache 2
After rewriting the data in the predetermined entry of -1, the virtual address lower bit sending means 63 sends the lower bits of the virtual address VA used for the rewriting to the system bus 3. Furthermore, during the rewriting, the map mechanism 64 changes the virtual address VA to a real address RA and sends it to the system bus 3.

The virtual address lower bit detection means 65 detects the lower bits of the virtual address VA sent into the system bus 3 and outputs the bits to the real address reading means 66.

The real address reading means 66 reads the real address RA from the entry of the cache 2-1 determined by the lower bits and outputs it to the comparator 26.

The comparator 26 receives the read real address R.
The real address RA sent to the AN and system bus 3 is compared, and the result is sent to the second data rewriting means 62.
Output to.

If the compared real addresses RA are the same, the second data rewriting means 62 takes in the data from the rewritten cache via the system bus 3 and stores it in the cache 2-1. rewrite the data of the predetermined entry.

If the compared real addresses RA are not the same, data is not rewritten.

The configuration of the present invention is basically characterized in that when the processor rewrites data in the cache, the lower bits of the virtual address VA that determine the cache entry are sent to the system bus 3. be.

With this configuration, when data in the cache of a certain processor system is rewritten,
Virtual address VA used to rewrite the data
Even if the real address RA corresponding to the real address RA is transferred to another cache, it is possible to determine the entry in the other cache with which the real address RA should be compared, thereby avoiding cache inconsistency. can.

Note that the processing operation (so-called snob operation) performed by each processor constituting the multiprocessor system to avoid cache mismatch, as shown in FIG. 3, can be performed in various ways by those skilled in the art using known techniques. It goes without saying that the configuration is not limited to only that shown in the figure.

Furthermore, in the above description, only the lower bits of the virtual address VA that determine the cache entry are sent to the system bus 3 via the first signal line, and only the lower bits are sent to the system bus 3 via the second signal line. Although it has been described that the real address RA is transferred to the cache via the system bus 3, the present invention is not limited to this.
Of course, it is also possible to incorporate more data into the cache.

Further, although the above embodiment is an example in which the present invention is applied to a direct map type cache, the present invention is not limited to this, and may be applied to a set associative type cache. Of course.

Since the configuration in this case can be easily created by those skilled in the art, its explanation will be omitted.

(Effects of the Invention) As is clear from the above description, according to the present invention, the following effects are achieved.

When data in the cache is rewritten, the lower bits of the virtual address VA corresponding to the data can be transferred to another cache, so it is possible to determine the entry in the cache where the data should be rewritten.

As a result, cache inconsistency can be avoided even if a write-in type cache is used in a multiprocessor system and a direct map type or set associative type cache is used. In other words, a multiprocessor system can be constructed using a cache that is easy to configure, such as a direct map method or a set associative method.

Therefore, the multiprocessor system can be easily configured.

Moreover, as a result, the multiprocessor system can be manufactured in a small size and at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cache applied to an embodiment of the present invention and its vicinity. FIG. 2 is a schematic configuration diagram of a multiprocessor system to which the present invention is applied. FIG. 3 is a flowchart showing the operation of each processor to monitor the transmission of the lower bits of the virtual address VA and avoid cache mismatch. FIG. 4 is a functional block diagram of an embodiment of the present invention. FIG. 5 is a schematic diagram showing an example of the structure of a write-in type virtual cache and a direct map type virtual cache. 1-1 to 1-N...processor, 2-1.2-N...
- Cache, 3... System bus, 4... Memory, 25.26... Comparator, 61... First data rewriting means, 62... Second data rewriting means, 63.
...Virtual address lower bit sending means, 64...
- Map mechanism, 65... Virtual address lower bit detection means, 66... Real address reading means, 1
00-1 to 100-N... Processor system agent Michito Hiraki and 1 other person Figure 2 Figure 3

Claims (3)

[Claims] (1) A MIMD multiprocessor system comprising a plurality of processor systems each comprising a processor and a write-in cache, a memory, and a system bus connecting each of the processor systems and the memory, wherein each of the processors A multiprocessor system characterized in that the system sends at least the lower bits of the virtual address VA to the system bus for determining the entry of each cache. (2) A MIMD multiprocessor system comprising a plurality of processor systems each comprising a processor and a write-in cache, a memory, and a system bus connecting each of the processor systems and the memory, wherein each of the processors The system includes: a first signal line for sending at least the lower bits of the virtual address VA to the system bus for determining the entry of each cache; and at least the lower bits of the virtual address VA sent to the system bus; A multiprocessor system comprising a second signal line for transferring data to each cache. (3) A MIMD multiprocessor system comprising a plurality of processor systems each comprising a processor and a write-in cache, a memory, and a system bus connecting each of the processor systems and the memory, wherein each of the processors The system includes a first data rewriting unit that rewrites data in the cache using a virtual address VA, and a virtual controller that sends at least the lower bits of the virtual address VA to the system bus when the first data rewriting unit rewrites the data. When data is rewritten by the address lower bit sending means and the first data rewriting means,
means for converting the virtual address VA into a real address RA and sending it to the system bus; virtual address lower bit detection for detecting at least the lower bits of the virtual address VA sent to the system bus from another processor system; real address reading means for reading a real address RA from a cache entry determined by at least the lower bits of the virtual address VA detected by the virtual address lower bit detection means; a comparator that compares a real address RAN and a real address RA sent to the system bus; and a comparator that reads data rewritten by the other processor system if the real addresses RA match each other according to the comparator; , and second data rewriting means for rewriting the data in the cache.