JPH01252090A - Signal detecting circuit - Google Patents

Abstract

PURPOSE:To attain the detection of the presence and absence of a chrominance signal with only one synchronizing detecting circuit by comparing a synchronizing detecting output with two types of a reference voltage, generating a pulse to show that the chrominance signal and the reference signal are in the prescribed synchronizing condition and a phase difference exceeds 90 deg. and controlling a counter. CONSTITUTION:For a detecting output by an ID synchronizing detecting circuit 21, a comparator 23, in which the reference voltage is added to a normal rotation terminal, is processed, and when a chrominance signal and a reference signal are in the prescribed synchronizing condition in accordance with the compared result, a positive burst ID pulse is outputted from an R-S type FF25. In the same way, a negative burst ID pulse to show that the phase difference between the chrominance signal and the reference signal exceeds 90 deg. from an R-S type FF29 is outputted, by the compared result through a comparator 27 in which the reference voltage is added to an inverting terminal. By these ID pulses, counters 30 and 33 are controlled, the pattern of a positive burst ID pulse existence and the mixing of this and the negative burst ID pulse is detected and an ID synchronizing detecting circuit becomes only one IC circuit for detecting the presence and absence of the chrominance signal having a small number of pins.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention is applicable to, for example, a video tape recorder (hereinafter referred to as V
The present invention relates to a signal detection circuit suitable for detecting whether or not a video signal is included in a video signal.

(Prior Art) For example, in a VTR, an ACC circuit is provided so that color signals are kept at a constant level for recording and reproduction.

However, if the television broadcast is black and white, this A
The color noise signal is amplified by the CC circuit, causing color noise interference in the monochrome image. For this reason, in VTR,
A color signal detection circuit and a color killer circuit are provided, and the color signal detection circuit detects whether or not a color signal is included in the video signal, and if the color signal is not included, the ACC circuit cuts the color signal output. It has become.

FIG. 5 shows the configuration of a conventional color signal detection circuit.

In FIG. 5, an ACK (automatic color killer) synchronous detection circuit 11 has a color signal and a 3.58 M'Hz signal synchronized with this color signal by an automatic phase control loop (hereinafter referred to as APC loop). A reference signal is supplied. This reference signal is output from, for example, a crystal oscillator (not shown). The ACK synchronous detection circuit 11 synchronously detects the color burst signal included in the color signal and the reference signal in accordance with the burst gate pulse BG. This synchronous detection output is held at a hold ratio of 12. This held voltage is compared with a reference voltage (1) in a comparator circuit 13.

Normally, since the color burst signal and the reference signal are synchronized, the voltage held by the capacitor 12 is high level < 1-
() becomes. Since this voltage is higher than the reference voltage v1, the output of the comparator circuit 13 becomes high level (H).

On the other hand, if the color signal is very small or the reference signal is not synchronized with this color signal, the synchronous detection output becomes low level (L). As a result, the output of the comparison circuit 13 also becomes low level (L). At this time, a color killer circuit (not shown) operates to cut the color signal output. This prevents color noise interference on a black and white screen.

Note that when the output of the comparator circuit 13 becomes low level (L), by slightly raising the level of the reference voltage V1,
The color signal cut operation may have hysteresis characteristics to enhance the effect of preventing malfunction.

The reference signal is synchronized to the chrominance signal using the APC loop, as described above. In order to speed up the response of this APC loop, an ID synchronous detection circuit 14, a capacitor 15, a comparison circuit 16, an AND circuit 17, and an SR flip-flop circuit 18 are used to increase the phase difference between the color signal and the reference signal by 90°. When it exceeds , the phase of the reference signal is inverted.

The fDIii 1st period detection circuit 14 is an ACK synchronous detection circuit 1.
1, the input signal and the reference signal are synchronously detected at the burst gate period. However, in this case, ID synchronous detection circuit 1
A smoothing capacitor 15, not a hold capacitor, is connected to the output terminal of 4.

Normally, the smoothed output of capacitor 15 is a positive signal. Therefore, in this case, by setting the reference voltage (2) of the comparison circuit 16 lower than the bias level of the smoothed output, the output of the comparison circuit 13 is as follows.

It becomes low level (L).

On the other hand, if the APC operation is disturbed and the phase difference between the input signal and the reference signal exceeds 90', the smoothed output becomes a negative polarity signal. As a result, the smoothed output of the capacitor 15 becomes the reference voltage v
2, and the comparator circuit 16 outputs a high level ()-1.
) pulse is increased by 1η.

This pulse is shaped into a waveform using an AND circuit 17 and an SR flip-flop circuit 18, resulting in a so-called burst ID.
Used as a pulse. That is, this burst ID
When the pulse is output, the phase of the reference signal is reversed,
This speeds up the phase pull-in operation.

Note that the AND circuit 17 and the SR flip-flop circuit 18
The reason why the output pulse of the comparison circuit 16 is waveform-shaped is to prevent chattering from occurring in the burst 10 pulses.

That is, as shown in FIG. 6, the output pulse of the comparator circuit 16 passes through an AND circuit whose gate is opened by the burst gate pulse 8G, and sets the SR flip-flop circuit 18 in a set state.

This SR flip-flop circuit 18 is reset at the timing of the fall of the burst gate BG. Therefore, even if there is chattering C in the output pulse of the comparison circuit 16 as shown in FIG. 6, this chattering C does not appear in the burst Ib pulse.

(Problems to be Solved by the Invention) The configuration of the conventional color signal detection circuit has been described above. In the case of this color signal detection circuit, two synchronous detection circuits, the ACK synchronous detection circuit 11 and the ID synchronous detection circuit 14, are used. When converting this into an integrated circuit (hereinafter referred to as IC),
It is necessary to attach two capacitors 12.15 externally,
There was a problem with external attachments when there were too many bottles.

Therefore, an object of the present invention is to provide a signal detection circuit that can reduce the number of bins for externally attaching capacitors [Arrangement 1 of the Invention (Means for Solving the Problems) To achieve this, the present invention provides a synchronous detection means for gated and synchronously detects an input signal and a first reference signal synchronized with the input signal using an automatic phase control loop at a predetermined period, and this synchronous detection means. The detection output of
or a third reference signal, and
A first pulse indicating that the input signal and the first reference signal are in a predetermined synchronization state, or a pulse indicating that the phase difference between the input signal and the first reference signal exceeds 90°. a comparison means for generating the second pulse, and a state in which the first pulse is continuously generated a predetermined number of times;
and means for determining the presence or absence of the input signal by determining whether the input signal exists a predetermined number of times in a period longer than the gate period of the synchronous detection means.

(Function) According to the above configuration, when an input signal is present, the second pulse is hardly outputted and the first pulse is outputted more often, so that the first pulse is continuously outputted at a predetermined level. The condition that the state that is output a number of times occurs a predetermined number of times in a period longer than the gate period is satisfied.

On the other hand, if there is no input signal, a large number of the second pulses are output, so the above condition cannot be met.

Therefore, from the synchronous detection output, the above-mentioned first. If you create a second pulse and judge its output status according to the above conditions,
It is possible to determine the presence or absence of the input signal.

According to such a configuration, since only one synchronous detection means is required, only one detection capacitor is required, and the number of capacitor connection bins can be reduced when integrated into an IC.

(Example) Hereinafter, an actual example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In this FIG. 1, an ID detection circuit 21, a capacitor 2
2. The comparison circuit 23, AND circuit 24, and SR flip-flop circuit 25, like the ID detection circuit 14, capacitor 15, comparison circuit 16, AND circuit 17, and SR flip-flop circuit 18 shown in FIG. When the phase difference with the reference signal exceeds 90°, a burst ID pulse is output to invert the phase of the reference signal. That is, the ID
The detection circuit 21 is supplied with a color signal and a 3.58 MHz reference signal. This ID detection circuit 21 further includes a burst gate pulse BG indicating a color burst signal period.
is supplied. The ID detection circuit 21 generates ID synchronized waves of the color burst signal and the reference signal included in the color signal according to the burst gate pulse BG. Comparison circuit 23
compares the levels of this synchronous detection output and the reference voltage v2, and outputs a pulse that remains at a high level (H) for a period in which the synchronous detection output is smaller than the reference voltage v2 (hereinafter, this pulse is referred to as a negative pulse). This state corresponds to when the phase difference between the input signal and the reference signal exceeds 90'. The negative pulse output from the comparison circuit 23 is supplied to the set terminal of the SR flip-flop circuit 25 through an AND circuit 24 whose gate is opened by the burst gate pulse BG. The SR flip-flop circuit 25 is turned on at the rising timing of the negative pulse, and the inverter 35
It is reset at the rising timing of the burst gate pulse BG which has been inverted at . As a result, a burst ID pulse that rises at the rising timing (start timing) of the negative pulse and falls at the falling timing (end timing) of the phase-inverted burst gate pulse BG is obtained from the Q output terminal of the SR flip-flop circuit. It will be done. Hereinafter, this burst ID pulse will be referred to as a negative burst ID pulse. This negative burst ID pulse is used as a burst ID pulse to invert the phase of the reference signal, as described above.

The synchronous detection output of the ID synchronous detection circuit 21 is further supplied to the positive phase input terminal of the comparison circuit 27 and compared with the reference voltage v1. As a result, the comparator circuit 27 outputs a high level (
H) is obtained (hereinafter, this pulse will be referred to as a positive pulse). This state corresponds to a case where the color signal and the reference signal are in a predetermined synchronous state. The positive pulse output from the comparison circuit 27 is shaped into a waveform by an AND circuit 28 and an SR flip-flop circuit 29 using the burst gate pulse BG, and output as a burst ID pulse. Hereinafter, this ID pulse will be referred to as a positive burst ID pulse.

The output patterns of the synchronous detection output of the ID detection circuit 21 are the following patterns (1) and (2).

(3) and (4) are possible.

(1) As shown in Figure 2(b), a pattern in which positive pulses appear almost continuously.This pattern occurs when the synchronization between the color signal and the reference signal is normal, for example, during normal playback. You can get it if you do.

(2) As shown in Figure 2 (C), a pattern in which there are more positive pulses than negative pulses, but a considerable proportion of negative pulses are also included. This pattern is obtained when performing special playback, etc. .

(3) As shown in Figure 2 (d), a pattern in which positive pulses and negative pulses are mixed together This pattern is useful when an asynchronous signal that causes a beat with the reference signal is mixed instead of the color signal. It will be done.

(4) As shown in FIG. 2(e), a pattern in which neither positive pulses nor negative pulses are generated.In this case, there is also no noise signal. This is because the noise signal is passed to the ground side by the capacitor 22.

The circuit in Figure 1 discriminates the above four patterns, and (1)
, (2), a detection output indicating that there is a color signal is obtained, and in the case of patterns <3> and (4), a detection output indicating that there is no color signal is obtained.

Here, if we pay attention to patterns (2) and (3), (2)
) During special playback to obtain a pattern, negative pulses may appear in areas corresponding to noise bars, but positive pulses continue in other areas. The continuous period is
Even if you consider up to 20 times speed playback, there is 12H (IH is one horizontal scanning period).

When the pattern (3) is asynchronous, the target frequency may be 800 Hz or more, assuming that the APC pull-in range is 800 Hz. In this case, the positive pulse lasts no more than 9 days. Therefore, if it is detected that a positive pulse continues for 10 hours between negative pulses and that this occurs several times in one vertical scanning period (1 Tvl), it is possible to distinguish between pattern (2) and pattern (3).

Below are the patterns (1) and (2) above, and (3).

A configuration for determining the pattern (4) will be explained.

The positive burst ID pulse obtained from the Q output terminal of the SR flip-flop 29 is counted by a counter 30. This counter 30 generates a pulse when the count value reaches a predetermined value, and is reset by the negative burst ID pulse or the reference pulse RP of 60H7 applied via the OR circuit 31. This reference pulse RP is converted by 1q by differentiating and full-wave rectifying the head switching pulse SWP in a differentiating/rectifying circuit 32. Here, the head switching pulse SWP is 2
This pulse has a frequency of 130 Hz and is synchronized with the rotational phase of the two rotating heads. This head switching pulse SWP is shown in FIG. 2(a).

The output pulses of counter 30 are counted by counter 33. This counter 33 uses the reference pulse R
It is reset by P. The count output of this counter 33 is held in a hold circuit 34 in accordance with the reference pulse RP just before its reset. When this hold value is greater than or equal to a predetermined value, the hold circuit 34 outputs a detection result that a color signal is present, and when it is less than a predetermined value, a detection result that a color signal is absent is output.

The specific configuration of the counters 30, 33 and the hold circuit 34 will be explained in FIG.

The configuration and operation of FIG. 3 will be explained below with reference to the timing chart of FIG. 4.

First, the counter 33 includes four D flip-flop circuits 301, 302, 303, 304 and an AND circuit 30.
4, the counter 33 is configured by an inverter 33
1, D flip-flop circuits 332, 333, 334 and an AND circuit 335. The hold circuit 34 includes an AND circuit 341, an SR flip-flop circuit 342, and a D flip-flop circuit 343.

First, the counters 30, 33 and the SR flip-flop circuit 342 of the hold circuit 34 are reset by the reference pulse RP shown in FIG. 4('a). After this, the counter 30 starts counting the positive burst ID pulses shown in FIG. 4(b).

When this positive ID pulse was counted 10 @, Fig. 4 (
As shown in e), a pulse is output from the AND circuit 305. This becomes a count input to the counter 33 at the next stage, and the count value of this counter 33 advances. After this, the counter 30 continues counting the positive burst ID pulses, but is reset when a negative burst ID pulse appears, as shown in FIG. 4(C). Figure 4 (
CI) shows how the D flip-flop circuit 302 is reset.

On the other hand, if a negative burst ID pulse does not appear, the counter 30 divides the frequency of the positive burst ID pulse by 1/16.

Therefore, the next pulse output from the AND circuit 305 is when the counter 30 outputs the 16th positive pulse l-I.
This is when D pulses are counted.

When the counter 33 counts seven output pulses from the counter 30, the output from the AND circuit 335 is calculated as shown in FIG.
As shown in FIG. 4(C>), the level becomes high (H), and the SR flip 70 tube circuit 342 is placed in the set state as shown in FIG. 4(C>).

After the next reference pulse RP is 1 Tv, the counter 30.3
3 and hold circuit 34, and at the same time, S
The data immediately before the reset of the R flip-flop circuit 342 is held in the D flip-flop circuit 343, as shown in FIG. 4(h).

According to the above configuration, among the patterns of synchronous detection output, (
For patterns 3) and (4), no pulse is output from the AND circuit 305 of the counter 3o, so the counter 33 does not count. Even if some pulses are output, if the number is less than 7, the SR flip-flop circuit 342 of the hold circuit 34 will not be set, so the Q output of the D flip-flop circuit 343 will remain at a low level. be.

On the other hand, in pattern (2), the setting of the SR flip-flop circuit 342 is delayed the most when 25 positive burst ID pulses appear and then a negative burst ID pulse comes. This is the 182nd (=26×7)Hth. Even this is sufficiently shorter than 1 Tv (=262.58). (
For pattern 1), 106 (=10+16x
6) The SR flip-flop circuit 342 is set at the Hth time. Therefore, for the pattern (1>, (2)), the Q output of the D flip-flop circuit 343 becomes high level.

From the above, it can be determined from the Q output of the D flip flow circuit 343 whether or not there is a color signal.

As described above, in this embodiment, by comparing the levels of the synchronous detection output and the reference voltages v1 and V2, a positive pulse indicating that the chrominance signal and the reference signal are in a predetermined synchronization state, and a chrominance signal and the reference voltage Create a negative pulse that indicates that the phase difference with the signal exceeds 90°, and if a color signal is present, make sure that the positive pulse continues at a considerable rate, and then make the positive pulse 10 times in a row. The presence or absence of a color signal is determined by determining whether the above output state exists seven or more times during the ITv period.

According to such a configuration, only one of the ten synchronous detection circuits 21 is required as a synchronous detection circuit, and one of the capacitors 22 is required as a detection capacitor. can be reduced.

Note that the present invention is of course applicable to signal detection circuits other than color signal detection circuits.

[Effects of the Invention] As described above, according to the present invention, a color signal can be detected with one synchronous detection circuit, so when integrated into an IC, the number of bins for connecting detection capacitors can be reduced. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a timing chart for explaining the operation of Fig. 1, Fig. 3 is a circuit diagram showing an example of a specific configuration of a part of Fig. 1, and Fig. 4 is a timing chart for explaining the operation of Fig. 3. FIG. 5 is a circuit diagram showing the configuration of a conventional color signal detection circuit, and FIG. 6 is a timing chart for explaining the operation of FIG. 5. 21... ID detection circuit, 22... Capacitor, 23
゜27... Comparison circuit, 24.28... AND circuit,
25°29...SR flip-flop circuit, 30.3
3... Counter, 32... Differential circuit, 34... Hold circuit, 301.302, 303, 304, 332
゜333.334.343...D flip flow circuit, 305,335,341...AND circuit, 331
...Inverter. Applicant's agent Patent attorney Takehiko Suzue
words

Claims (1)

[Scope of Claims] A synchronous detection means for synchronously detecting an input signal and a first reference signal synchronized with the input signal using an automatic phase control loop by gating the input signal at a predetermined period, and this synchronous detection means. a first comparison means that compares the level of the detection output of the input signal and a second reference signal, and outputs a pulse when the input signal and the first reference signal are in a predetermined synchronized state; and the synchronous detection means The detection output of the input signal and the third reference signal are compared in level, and when the phase difference between the input signal and the first reference signal exceeds 90°, the phase of the first reference signal is inverted. a second comparing means that outputs a pulse; and a first comparing means that counts the output pulses of the first comparing means and generates a pulse when the count value reaches a predetermined value.
a second counting means for counting output pulses of the first counting means; and a second counting means for setting the first counting means to an initial state according to the output pulses of the second comparing means. and a second initial state setting for setting the first counting means and the second counting means to an initial state using a fourth reference signal having a period longer than the gate period of the synchronous detection means. and determining whether the input signal is present by determining whether or not the count value of the second counting means immediately before being set to the initial state by the second initial state setting means has reached a predetermined value. A signal detection circuit characterized in that it comprises a determination means for determining whether or not the signal is detected.