JP3318631B2 - Color killer signal forming device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color for digitally processing a digital color signal in accordance with the presence or absence of a burst signal in a digital color signal obtained by digitizing a color signal component contained in a composite video signal. The present invention relates to a color killer signal forming device that forms a color killer signal supplied to a signal processing unit.

[0002]

2. Description of the Related Art A composite video signal including a luminance signal component, a chrominance signal component having a predetermined carrier frequency, a synchronization signal component, and the like is digitized, and various processes for the composite video signal are digitalized. Accordingly, it has been proposed to improve processing of a composite video signal. The digitization of the composite video signal in such a case is performed, for example, under the condition that the sampling frequency for the composite video signal is 4f _SC corresponding to four times the carrier frequency f _SC of the color signal component. It is assumed that a digital composite video signal having a bit configuration is formed. Then, a digital luminance signal obtained based on a luminance signal component in the composite video signal and a digital color signal obtained based on a color signal component in the composite video signal are separated from the digital composite video signal, and the digital luminance signal is separated into a digital luminance signal. Various digital processing and various digital processing for the digital chrominance signal are performed in the luminance signal processing unit and the color signal processing unit, respectively.

In performing various digital processes on a digital color signal in a color signal processing section, a digital burst signal obtained by digitizing a color burst signal included in a color signal component is variously processed. Used in various ways. The color burst signal in the color signal component has a frequency of f _SC and has a predetermined phase relationship with respect to the RY axis and the BY axis, which are the modulation axes of the color signal component. Thus, when digitized, for example, as shown in FIG. 5, the sampling of the frequency with respect to the color burst signal SBT with the frequency as f _SC and 4f _SC in each cycle of the color burst signal SBT - (R-Y) The phase component, the-(BY) phase component , the ( RY) phase component, and the (BY) phase component are sequentially extracted, and based on each extracted component,
- (R-Y) phase component data - (R-Y) D, - (B-
Y) phase component data - (B-Y) D, (R-Y) phase component data (R-Y) D and (B-Y) phase component data (
BY) D is arranged and the digital burst signal D
BT is formed.

In this way, the composite video signal is supplied, and various digital processes for the digital luminance signal and the digital chrominance signal separated from the digital composite video signal based on the composite video signal are performed in the luminance signal processing unit and the color signal processing unit, respectively. For equipment that is to be performed,
Usually, even when a video signal including a luminance signal component and a synchronizing signal component is supplied without including a color signal component instead of a composite video signal, a digital luminance signal formed by digitizing the luminance signal component Is obtained, and various digital processes on the digital luminance signal are properly performed in the luminance signal processing unit. At this time, a digital signal component obtained based on a component having a frequency falling within the color signal component frequency band in the luminance signal component is treated as if it were a digital color signal in the color signal processing unit, and thereby the color signal is processed. The color noise component is output from the signal processing unit, and the color noise component adversely affects the digital luminance signal or a reproduced image obtained by the image reproducing unit based on the digital luminance signal.

[0005] Therefore, both the composite video signal and the video signal containing no color signal component are selectively supplied, and the digital processing based on the digital luminance signal and the digital chrominance signal, or only the digital luminance signal, is performed. Is performed, when a video signal containing no color signal component is supplied and digital processing is performed on only the digital luminance signal, at least a part of the function of the color signal processing unit is stopped. An assumed color killer operation is performed, thereby preventing a color noise component from being output from the color signal processing unit. In such a color killer operation, when a video signal containing no color signal component is supplied, it is detected that a normal digital color signal does not exist, and a color killer signal for performing the color killer operation is accordingly generated. The color killer signal thus formed is supplied to, for example, a band amplification unit for amplifying a digital color signal in the color signal processing unit, whereby the operation of the band amplification unit is stopped. The detection of the absence of the normal digital color signal at this time is performed by detecting the absence of the digital burst signal.

[0006]

As described above, when the absence of a digital burst signal is detected and a color killer signal is formed, various types of digital processing on a digital color signal, that is, an automatic demodulation axis, have conventionally been used. Phase control (APC) processing, automatic color signal level control (AC
C) A color killer signal including a circuit for determining the presence or absence of a digital burst signal and a circuit for forming a color killer signal in accordance with the determination result of the presence or absence of a digital burst signal in a color signal processing unit for performing processing and the like. And a dedicated circuit unit for obtaining the same. Therefore, the color signal processing section, which originally has a relatively complicated configuration by performing APC processing, ACC processing, and the like on the digital color signal, is further provided with a dedicated signal for obtaining a color killer signal. The provision of the circuit unit is accompanied by the inconvenience of further increasing complexity and increasing the scale.

In view of the above, the present invention provides a color signal processing unit for performing various digital processes on a digital color signal obtained by digitizing a color signal component included in a composite video signal. In detecting the absence of a burst signal, and obtaining a color killer signal in accordance with the detection result, the color signal processing unit does not need a dedicated circuit unit for detecting the presence or absence of the burst signal. An object of the present invention is to provide a color killer signal forming device capable of properly and reliably transmitting a color killer signal, including a process that can be shared with digital processing.

[0008]

In order to achieve the above object, a color killer signal forming apparatus according to the present invention comprises a burst signal in a digital color signal obtained by digitizing a color signal component in a composite video signal. In which a portion of data containing a burst signal is stored with a write cycle corresponding to the horizontal cycle of the composite video signal, and reading out data of a portion containing a burst signal stored in the memory portion for each write cycle A control unit, a maximum amplitude value detecting unit for detecting a maximum amplitude value of a burst signal represented by the data based on data read from the memory unit for each writing cycle, and a burst detected by the maximum amplitude value detecting unit; The state in which the maximum amplitude value of the signal is equal to or larger than the first reference value is over a predetermined number of data read from the memory unit for each writing cycle. In the following, based on amplitude color killer data generating means for transmitting amplitude color killer data having a specific state, and data read out from the memory unit for each writing cycle, each cycle of a burst signal represented by the data is performed. A phase component amplitude value detecting means for detecting an amplitude value of the specific phase component, and an amplitude value of the specific phase component detected by the phase component amplitude value detecting means,
A specific burst period counting means for determining a period of the burst signal which is equal to or more than the reference value as a specific burst period and counting the number for each data read from the memory unit for each writing period; When the state in which the number of the specific burst periods detected by the means is equal to or more than the predetermined number continues over the predetermined number of data read from the memory unit for each writing period, the phase in which the specific state is obtained. A phase color killer data generating means for transmitting color killer data, and a color killer data having a specific state when the amplitude color killer data has a specific state or when the phase color killer data has a specific state. And a color killer data generator for sending out as a killer signal.

[0009]

In the color killer signal forming apparatus according to the present invention as described above, the main part thereof is, for example, a microcomputer which constitutes a color signal processing section for performing various digital processes on digital color signals. Can be substantially configured by setting the above program. Then, while eliminating the need for a dedicated circuit unit for detecting the presence or absence of a burst signal, the color signal processing unit performs a process that is shared with, for example, the APC process. A color killer signal can be appropriately and reliably formed without causing complexity and an increase in scale.

[0010]

FIG. 1 shows an example of a color killer signal forming apparatus according to the present invention, together with a digital video signal processing apparatus including a color signal processing section to which the color killer signal forming apparatus is applied.

In the digital video signal processing apparatus shown in FIG. 1 and including a color signal processing section to which an example of the color killer signal forming apparatus according to the present invention is applied, the luminance signal component and the carrier frequency are set to f _SC ( For example, f _SC = 3.58 MHz)
Or a composite video signal including a color signal component, a synchronization signal component, and the like, or an analog video including a luminance signal component, a synchronization signal component, and the like, and a video signal configured without a color signal component The signal SV is applied to the signal input terminal 1
1 through an analog / digital (A / D) converter 12
Supplied to

When the analog video signal SV is a composite video signal, the analog video signal SV, that is, the composite video signal, includes a color burst signal SBT as shown in FIG. The color burst signal SBT has a frequency of f _SC , a RY axis that is a modulation axis of a color signal component, and a color burst signal SBT.
It has a phase relationship of-(BY) phase with respect to the -Y axis, and is continuous for eight periods.

In the A / D converter 12, the analog video signal SV is digitized under the condition that the sampling frequency is sampled at 4f _SC corresponding to four times the carrier frequency (f _SC ) of the color signal component. And, for example, 1
A digital video signal DV having a 0-bit configuration is formed and supplied to a luminance signal / color signal separation unit (Y / C separation unit) 13. In the Y / C separation unit 13, a digital luminance signal DY obtained by digitizing a luminance signal component and a digital color signal DC obtained by digitizing a chrominance signal component are mutually separated from the digital video signal DV. It is taken out. The digital luminance signal DY is
The digital signal is supplied to the luminance signal processing unit 14, undergoes various types of digital processing in the luminance signal processing unit 14, is converted into a digital luminance signal DYY for image display, and is supplied from the luminance signal processing unit 14 to the matrix processing unit 15.

[0014] On the other hand, the digital color signal DC obtained from the Y / C separation unit 13 is assumed to sampling to 4f _SC of frequency for the carrier with the frequency as f _SC is Moto digitized performed By doing so, B in FIG.
In as shown in, - (R-Y) phase component data - (R
−Y) D, − (BY) phase component data − (BY)
D, (R-Y) phase component data (R-Y) D and (B-
Y) A digital burst signal DBT obtained by repeating the arrangement of the phase component data (BY) D and digitizing the color burst signal SBT as shown in FIG. It is assumed to be included with a period that does. Digital burst signal DBT, corresponding to each cycle of the color burst signal SBT, - (R-
Y) phase component data - (R-Y) D, - (B-Y) phase component data - (B-Y) D, (R-Y) phase component data
( RY) D and (BY) phase component data (BY)
D is formed in an array.

The digital chrominance signal DC is amplified by the band amplification unit 16 in the chrominance signal processing unit 20 and supplied to the chrominance signal demodulation unit 17. Color signal demodulation unit 17
Is also supplied with a reference clock pulse signal CPB sent from a color synchronizing unit 18 described later and having a frequency of f _SC and synchronized with the digital burst signal DBT. In the color signal demodulation unit 17, a digital (RY) demodulation axis signal and a digital (BY) demodulation axis signal are formed based on the reference clock pulse signal CPB, and the digital (R) −
Y) Demodulation using the demodulated axis signal is performed to obtain a digital red color difference signal DC (RY).
Digital (BY) for digital color signal DC
Demodulation using the demodulation axis signal is performed to obtain a digital blue color difference signal DC (BY), and these digital red color difference signal DC (RY) and digital blue color difference signal DC (BY). Are supplied from the color signal demodulation unit 17 to the matrix processing unit 15.

In the matrix processing unit 15, the image display digital luminance signal D from the luminance signal processing unit 14 is output.
The digital red color difference signal DC (RY) and the digital blue color difference signal DC (B-
Y), the digital red primary color signal DR, the digital green primary color signal DG, and the digital blue primary color signal D
B is formed. Then, the digital red primary color signal DR, the digital green primary color signal DG, and the digital blue primary color signal DB are transmitted from the matrix processing section 15 as video signals for image display.

In the color signal processing section 20, Y /
The digital color signal DC obtained from the C separation unit 13 is D
-It is also supplied to the input (D) of the flip-flop (DFF) 21. DF. F. A clock end of a clock pulse signal C having a frequency of 4f _SC as shown in FIG.
PA is supplied and DF. F. At 21, the digital color signal DC supplied to the input terminal (D) is latched at each rising edge of the clock pulse signal CPA. Thereby, DF. F. The digital burst signal DB latched at each rising edge of the clock pulse signal CPA as shown in FIG.
A digital chrominance signal DCR containing TR is obtained and supplied to the input of a random access memory (RAM) 22. A color synchronizing unit 18 is provided at the clock end of the RAM 22.
The inverted clock pulse signal -CPA obtained by inverting the polarity of the clock pulse signal CPA transmitted from the inverter 23 by the inverter 23 is supplied.

The clock pulse signal CPA having a frequency of 4 f _SC from the color synchronizing unit 18 is supplied to the address counter 24.
Is also supplied to the clock end of Further, as shown in FIG. 2E, a portion of the digital burst signal DBT, which appears with a cycle corresponding to the horizontal cycle, and portions before and after the digital burst signal DBT, that is, A burst gate signal BGP which takes a high level corresponding to a portion including the digital burst signal DBT which appears with a cycle corresponding to the cycle is supplied, and the burst gate signal BGP from the burst gate signal input terminal 25 is DF. F. 26 input terminals (D)
Supplied to DF. F. A reference clock pulse signal CPB having a frequency of f _SC from the color synchronizing unit 18 obtained through the phase shift unit 27 at the clock end of
_{As the SC} , a clock pulse signal CPB ′ having a phase different from that of the reference clock pulse signal CPB as shown in FIG. 2F is supplied. And DF. F. At 26, the burst gate signal BGP from the burst gate signal input terminal 25 supplied to the input terminal (D) is the clock pulse signal C with the frequency f _SC from the phase shift unit 27.
Latched at each rising edge of PB '. Thereby, D
-F. F. 26, DF.26 as shown in FIG. F. Obtained control signal CCR taking high level in response to the portion including the digital burst signal DBTR in the digital color signal DCR obtained from the output of 21 (Q), through which the NAND gate 28, the address counter 24 To the control end.

DF. F. The inverted output terminal (-Q) 26 has a level relationship different from that of the control signal CCR. When the control signal CCR rises from a low level to a high level, it falls from a high level to a low level, and the control signal CCR
When R falls from the high level to the low level, an inversion control signal -CCR that rises from the low level to the high level is obtained. F. 29 (D). DF. F. At the clock end of 29, the clock pal
A signal CPA is supplied. And DF. F. 29
, The inversion control signal supplied to the input terminal (D)
CCR is latched at each rising of clock pulse signal CPA . Thereby, DF. F. 29, a control signal CC as shown in FIG.
A control signal CCQ having a period in which R takes a high level after the period in which R takes a high level is obtained, and is supplied to the control terminal of the address counter 24 through the NAND gate section 28.

The address counter 24 includes a color synchronizing unit 18
Pulse signal CPA with a frequency of 4f _SC from
Is counted, and the counted value is DF. F. 26 at the time TWR due to the rise of the control signal CCR from the low level to the high level which is obtained from the output terminal (Q) of the control signal CCR and supplied to the control terminal through the NAND gate unit 28. F. 29 output (Q), NA
The control signal CCQ supplied to the control terminal through the ND gate unit 28 is reset to “0” at the time TRR by the rising of the control signal CCQ from the low level to the high level. Thereby, in the address counter 24, the count value is reset to "0" by the rise of the control signal CCR from the low level to the high level, and thereafter, the count value becomes "0" every time the clock pulse signal CPA rises. And the count value thereof is reset to "0" by the rise of the control signal CCQ from the low level to the high level, and then the clock pulse signal CP
A state in which the value A gradually increases from “0” each time the rising edge of A arrives is selectively taken.

The address counter 24 corresponds to the count value "1" to "56", which is the count value during the period when the control signal CCR is at the high level, and counts during the period when the control signal CCQ is at the high level. Numerical values are assumed to correspond to "1" to "56".
The address data DAD as shown in FIG. 2H is generated every time the clock pulse signal CPA rises, and is supplied to an address terminal in the RAM 22. Further, the address counter 24 takes a high level while the control signal CCR takes a high level during a period in which the count value is from "1" to "56", and the control signal CCR takes a high level.
The signal CX which is assumed to be at a high level even during the period when the count value is from "1" to "56" while the CQ is at a high level is generated, and the signal CX is sent to the memory control unit 31.
To supply. The period in which the count value of the address counter 24 is from "1" to "56" is a period that is 14 times the cycle of the color burst signal SBT.

In the memory control unit 31, the address
Control signal CCR in signal CX from counter 24
2 takes a high level in response to a portion which takes a high level under a high level, and as shown in FIG. 2I, a write command signal PW is formed, and a signal CX from an address counter 24 is generated. In FIG. 2, a read command signal PR is formed as shown in FIG. 2K, which takes a high level in accordance with a portion which takes a high level under the control signal CCQ taking a high level, and these write command signals PW And a read command signal PR are supplied to a write control terminal and a read control terminal of the RAM 22, respectively.

In the RAM 22, a memory control unit 31
During a period in which the write command signal PW supplied from the DF takes a high level, DF. F. 21
Output from the (Q) of - (R-Y) phase component data - (
R−Y) D, − (B−Y) phase component data− (B−Y)
D, (R-Y) phase component data (R-Y) D and (B-
Y) The phase component data (BY) D is written and stored at the address specified by the address data DAD at each rising edge of the inverted clock pulse signal -CPA. As a result, the digital color signal DC is stored in the RAM 22 with a write cycle corresponding to the horizontal cycle.
R, the portion corresponding to the period during which the burst gate signal BGP takes a high level, and therefore the digital color signal DCR
Forming a portion including the digital burst signal DBTR in - (R-Y) phase component data - (R-Y) D, - (
B-Y) phase component data - (B-Y) D, is (R-Y) phase component data (R-Y) D and (B-Y) phase component data (B-Y) D, the inverted clock pulses The data is sequentially stored at the address specified by the address data DAD with a cycle equal to the cycle of the signal -CPA.

In the RAM 22, while the read command signal PR supplied from the memory control unit 31 is at a high level, as described above, writing is performed immediately before the write command signal PW is at a high level. the form a moiety containing a digital burst signal DBTR in the digital color signal DCR - (R-Y) phase component data - (R-Y) D, - (B-Y) phase component data -
(B-Y) D, ( R-Y) phase component data (R-Y) D
And the repetition of the (BY) phase component data (BY) D is read from the address specified by the address data DAD at each rising edge of the inverted clock pulse signal -CPA. Thereby, the RAM 22
From the digital color signal D as shown in FIG.
Forming a portion including the digital burst signal DBTR in CR - (R-Y) phase component data - (R-Y) D,
-(BY) phase component data-(BY) D , ( RY)
) Phase component data (R-Y) D and (B-Y) phase component data (B-Y) D repetition of, will be read out by each write cycle minutes.

On the other hand, the analog video signal SV is
If the video signal does not include a color signal component, the analog video signal SV is supplied to the A / D converter 12 to which the analog video signal SV is supplied at a sampling frequency of 4f.
The digital video signal DV is digitized while being sampled as _SC, and is, for example, a 10-bit digital video signal DV.
Is formed and supplied to the Y / C separation unit 13. In such a case, only the digital luminance signal DY obtained by digitizing the luminance signal component of the digital video signal DV is obtained from the Y / C separation unit 13, and the digital color signal DC is not obtained. And the digital luminance signal DY
Is supplied to the luminance signal processing unit 14, and the luminance signal processing unit 1
4 undergoes various kinds of digital processing, and is converted into a digital luminance signal DYY for image display.
Is supplied to the matrix processing unit 15 from the.

Under these circumstances, since the digital color signal DC cannot be obtained from the Y / C separation unit 13, the RAM 22
- (RY) phase component data forming a portion including a digital burst signal in a digital color signal,-(B
-Y) phase component data , ( RY) phase component data and
(B-Y) operation repeated phase component data are stored is not performed, also along with it, from the RAM 22, to form a portion including the digital burst signal in the digital color signal written to it - (R- The operation of reading out the repetition of the Y) phase component data, the- ( BY) phase component data , the ( RY) phase component data, and the (BY) phase component data is not performed. Then, the image display digital luminance signal DYY is transmitted from the matrix processing unit 15 as it is.

As described above, the analog video signal SV
There data forming a portion including read by the write cycle minutes from RAM22 when a composite video signal, a digital burst signal DBTR in digital chrominance signal DCR, i.e., - (R-Y) phase component data - ( RY)
D,-(BY) phase component data-(BY) D , ( R
-Y) phase component data (R-Y) D and (B-Y) phase component data (repetition of B-Y) D are sequentially supplied to the burst processing unit 32. Burst processing unit 3
2, data forming a portion including the digital burst signal DBTR in the digital color signal DCR read out from the RAM 22 for each writing cycle is sequentially taken in, and based on the data, a digital burst corresponding to eight cycles is obtained. The maximum value (maximum amplitude value) BLmax of the amplitude in each one cycle of the signal DBTR is detected, and the detected maximum amplitude value BLmax is set to a reference value BR set in advance so as to eliminate noise components. Compared to
It is determined whether or not the value is equal to or greater than the reference value BR. And RAM2
2. Whenever the data forming the portion including the digital burst signal DBTR in the digital color signal DCR is read from 2, the maximum amplitude value BLmax obtained based on the read data is set to be greater than or equal to the reference value BR. When the count value CA of the counter TA is increased by "1" and the maximum amplitude value BLmax obtained based on the read data is smaller than the reference value BR, the count value CA of the internal counter TA becomes "1". 1 ". As a result, when the count value CA of the built-in counter TA is “0”, the amplitude color killer data DKA is transmitted as representing “1”, and thereafter, the count value CA of the built-in counter TA becomes a predetermined value, for example, When it becomes “31”, the Y / C separation unit 13 outputs the appropriate digital color signal DC.
Is obtained, and the amplitude color killer data DKA is transmitted as representing "0".
Further, when the count value CA of the built-in counter TA becomes "0" again, it is recognized that a proper digital color signal DC cannot be obtained from the Y / C separation unit 13, and the amplitude color killer data DKA is sent as representing "1".

In the burst processing unit 32, the digital color signal DC read from the RAM 22 is read.
Data forming a portion including the digital burst signal DBTR in R, i.e., - (R-Y) phase component data - (
R−Y) D, − (B−Y) phase component data− (B−Y)
D, (R-Y) phase component data (R-Y) D and (B-
Y) Of the repetition of the phase component data (BY) D,
-(BY) phase component data-(BY) D each (since the entire period is 14 times the period of the color burst signal SBT,-(BY) phase component data-( B-
Y) D) There are a total of 14) L [− (B
−Y) D] is detected, and the detected amplitude value L [− (B
−Y) D] is compared with a reference value LR set in advance so that a noise component can be eliminated, and it is determined whether or not the reference value LR or more. When the amplitude value L [− (B−Y) D] is equal to or larger than the reference value LR, the count value C1 of the built-in counter T1 is increased by “1”, and the amplitude value L [− (B−
Y) D] is smaller than the reference value LR, the count value C1 of the built-in counter T1 is decreased by "1".

In this way, a total of 14-(BY)
When the detection of the amplitude value L [-(BY) D] for all of the phase component data- (BY) D is completed, the final value of the count value C1 of the built-in counter T1 is set to a predetermined value. Is compared with the reference value CR to determine whether it is equal to or more than the reference value CR. Then, the digital color signal D is read from the RAM 22.
Every time data forming a portion including the digital burst signal DBTR in the CR is read, when the final value of the count value C1 of the built-in counter T1 based on the read data is equal to or more than the reference value CR, When the count value C2 of the other built-in counter T2 is increased by "1" and the final value of the count value C1 of the built-in counter T1 based on the read data is smaller than the reference value CR, The count value C2 of the other internal counter T2 is decreased by "1". As a result, when the count value C2 of the built-in counter T2 is "0", the phase color killer data D
KP is sent out as representing "1" and then
The count value C2 of the built-in counter T2 is a predetermined value, for example,
When the value becomes "31", it is recognized that a proper digital color signal DC is obtained from the Y / C separation unit 13, and the phase color killer data DKP is transmitted as representing "0". Thereafter, when the count value C2 of the internal counter T2 becomes "0" again, Y /
It is recognized that a proper digital color signal DC cannot be obtained from the C separation unit 13, and the phase color killer data DKP is transmitted as representing "1".

The amplitude color killer data DKA and the phase color killer data DKP sent from the burst processing unit 32 are respectively supplied to a pair of input terminals of the OR gate unit 33, and the amplitude color killer data DKA is supplied to the output terminal of the OR gate unit 33. And phase color killer data D
When both KPs represent "0", they represent "0",
Color killer data DK representing "1" at other times
L is obtained. Thus, the color killer data DKL obtained from the OR gate unit 33 is supplied to the band amplification unit 16 as a color killer signal. The band amplification unit 16 to which the color killer data DKL is supplied from the OR gate unit 33 performs appropriate amplification processing on the digital color signal DC obtained from the Y / C separation unit 13 when the color killer data DKL represents “0”. And the color killer data DKL is "1"
, The amplification process for the digital color signal DC obtained from the Y / C separation unit 13 is stopped, and the color killer operation for preventing the digital color signal DC from being supplied from the output terminal thereof to the color signal demodulation unit 17 is performed. It is set to be performed.

When the analog video signal SV is a video signal containing no color signal component, data forming a portion including a digital burst signal in the digital color signal is not read out from the RAM 22. Both the amplitude color killer data DKA and the phase color killer data DKP sent from the unit 32 always indicate "1". As a result, the color killer data DKL obtained from the OR gate 33 is maintained as indicating "1". You.

As described above, the amplitude color killer data DKA and the phase color killer data DKP are sent from the burst processing unit 32, and the amplitude color killer data DK is transmitted.
The color killer data DKL is formed by supplying the amplitude color killer data DKA and the phase color killer data DKP to the OR gate unit 33, instead of the A or phase color killer data DKP being directly converted into a color killer signal. , Its color killer data DKL
Is made to be a color killer signal,
A malfunction caused by the noise component being treated like a burst signal can be avoided.

In the burst processing unit 32, the digital color signal DC is read from the RAM 22 as described above.
Each time data forming a portion including the digital burst signal DBTR in R is read, the maximum amplitude value BLmax obtained based on the read data is used, and the ACC that changes in accordance with the change in the maximum amplitude value BLmax is used. An operation for forming the processing control data DCC is also performed. The obtained ACC processing control data DCC is supplied from the burst processing unit 32 to the band amplification unit 16, and the band amplification unit 16 performs ACC on the digital color signal DC obtained from the Y / C separation unit 13. ACC processing based on the processing control data DCC is performed.

Further, in the burst processing unit 32,
For example, when the digital color signal DCR
Data forming a portion including the digital burst signal DBTR.
Based on the digital bar
APC processing control data according to the phase of the strike signal DBT
An operation for forming a DPP is performed. And got
The control data DPP for APC processing is transmitted to the burst processing unit.
The color synchronizing unit 18 supplies the color synchronizing unit 18 with
APC processing is performed, and the
F_SCThe reference clock pulse signal CPB and
And frequency 4f _SCHusband of clock pulse signal CPA
The phase synchronized with the digital burst signal DBT
It is assumed to have.

Under the circumstances, the portion including the RAM 22, the memory control unit 31, the burst processing unit 32, and the OR gate unit 33 constitutes an example of the color killer signal forming apparatus according to the present invention. The burst processing unit 32 is formed using, for example, a microcomputer. An example of a control program executed by the microcomputer in forming a color killer signal in such a case is described in the flowcharts shown in FIGS. It is described as follows with reference to.

The control program shown in FIG. 3 is executed by the microcomputer forming the burst processing unit 32 when transmitting the amplitude color killer data DKA. After the start, the digital color signal DCR read from the RAM 22 at step 41 is read. Data forming a portion including the digital burst signal DBTR therein,
That, - (R-Y) phase component data - (R-Y) D, -
(BY) phase component data-(BY) D , ( RY)
Based on the phase component data (R-Y) D and (B-Y) phase component data (B-Y) repeatedly and D, for detecting the maximum amplitude value BLmax for digital burst signal DBTR corresponding to 8 cycles . Subsequently, in step 42, it is determined whether or not the maximum amplitude value BLmax detected in step 41 is equal to or larger than a preset reference value BR. As a result, if the maximum amplitude value BLmax is equal to or larger than the reference value BR, it is determined in step 43 whether the count value CA of the built-in counter TA is "31" which is a predetermined value set in advance. I do.

If the result of determination in step 43 is that the count value CA of the built-in counter TA is not "31", in step 44, the count value CA of the built-in counter TA is increased by "1". Return. If the result of determination in step 43 is that the count value CA of the built-in counter TA is “31”, it is determined in step 45 whether or not the amplitude color killer data DKA indicates “0”. to decide. If the amplitude color killer data DKA does not indicate "0", the amplitude color killer data DKA is transmitted in step 46 as indicating "0", and then the process returns to step 41. If the amplitude color killer data DKA represents “0”, the process directly returns from step 45 to step 41.

If it is determined in step 42 that the maximum amplitude value BLmax detected in step 41 is smaller than the preset reference value BR, the count value CA of the built-in counter TA is set to "0" in step 47. Is determined, and if the count value CA of the built-in counter TA is not “0”, the count value CA of the built-in counter TA is reduced by “1” in step 48, and thereafter, the process returns to step 41. If the result of determination in step 47 is that the count value CA of the built-in counter TA is “0”, step 4
In step 9, it is determined whether or not the amplitude color killer data DKA represents "1". And
If the amplitude color killer data DKA does not indicate "1", in step 50, the amplitude color killer data DKA is transmitted as indicating "1", and thereafter, the process returns to step 41. If the killer data DKA indicates “1”, the process directly returns from step 49 to step 41.

The control program shown in FIG. 4 is executed by the microcomputer forming the burst processing unit 32 when transmitting the phase color killer data DKP. After the start, in step 51, the count value C1 of the built-in counter T1 is set to " 0 ". In the next step 52, the digital burst signal DB in the digital color signal DCR read from the RAM 22 is set.
Data forming a part including TR, that is, − (RY)
Phase component data - (R-Y) D, - (B-Y) phase component data - (B-Y) D, (R-Y) phase component data (R
− (B−Y) phase component data− (B) in the repetition of (Y) D and (BY) phase component data (BY) D
−Y) D represents an amplitude value L [− (B−Y) D].
Is detected.

Next, in step 53, step 5
It is determined whether or not the amplitude value L [− (B−Y) D] detected in step 2 is equal to or larger than a preset reference value LR. as a result,
If the amplitude value L [− (B−Y) D] is less than the reference value LR, in step 54, the count value C1 of the built-in counter T1 is decreased by “1”, and the process proceeds to step 56. If the amplitude value L [− (B−Y) D] is equal to or larger than the reference value LR, in step 55, the count value C1 of the built-in counter T1 is increased by “1”, and the process proceeds to step 56. In step 56, the number counter T
It is determined whether or not the count value CN of N is “14”, and if the count value CN of the number counter TN is not “14”,
In step 57, the count value CN of the number counter TN
Is increased by “1”, and the process returns to step 52.
If the count value CN of the number counter TN is “14”, the count value CN of the number counter TN is reset to “0” in step 58, and the process proceeds to step 59.

In step 59, the built-in counter T
It is determined whether or not the count value C1 is equal to or greater than a preset reference value CR. As a result, the count value C of the built-in counter T1
If 1 is equal to or greater than the reference value CR, it is determined in step 60 whether the count value C2 of the built-in counter T2 is "31" which is a predetermined value set in advance. If the result of the determination in step 60 is that the count value C2 of the built-in counter T2 is not "31", the count value C2 of the built-in counter T2 is increased by "1" in step 61, and thereafter, the process returns to step 51. Also, as a result of the determination in step 60, the count value C2 of the built-in counter T2 becomes "3".
If "1", it is determined in step 62 whether or not the phase color killer data DKP indicates "0". If the phase color killer data DKP is not set to represent "0", then in step 63, the phase color killer data
KP is transmitted as representing "0", and thereafter, the process returns to step 51, where the phase color killer data DKP
Represents "0", the process directly returns from step 62 to step 51.

At step 59, the built-in counter T
If the count value C1 of the internal counter T2 is less than the reference value CR, it is determined in step 64 whether the count value C2 of the internal counter T2 is "0". In step 65, the count value C2 of the built-in counter T2 is decreased by "1", and the process returns to step 51. Also, as a result of the determination in step 64, the count value C2 of the built-in counter T2 becomes "0".
In step 66, it is determined whether or not the phase color killer data DKP indicates "1". And the phase color killer data D
If KP does not represent "1",
In step 67, the phase color killer data DKP
Is transmitted as representing "1", and thereafter, the flow returns to step 51. If the phase color killer data DKP is represented as "1", the flow directly returns from step 66 to step 51.

[0043]

As is clear from the above description, the main part of the color killer signal forming apparatus according to the present invention is, for example, a micro signal forming section for performing various digital processes on digital color signals. It can be constructed substantially by setting a predetermined program in a computer, and furthermore, it does not require a dedicated circuit unit for detecting the presence or absence of a burst signal. Performed, for example, APC
According to the color killer signal forming apparatus according to the present invention, the color killer signal is properly and reliably processed without complicating and enlarging the color signal processing unit. Can be formed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a color killer signal forming apparatus according to the present invention together with a digital video signal processing apparatus including a color signal processing unit to which the color killer signal forming apparatus is applied.

FIG. 2 is a waveform chart used for describing the operation of the digital video signal processing device shown in FIG.

FIG. 3 is a flowchart illustrating an example of a control program executed by a microcomputer used in an example of a color killer signal forming apparatus according to the present invention when transmitting amplitude color killer data.

FIG. 4 is a flowchart illustrating an example of a control program executed by a microcomputer used in an example of a color killer signal forming apparatus according to the present invention when transmitting phase color killer data.

FIG. 5 is a waveform chart for explaining digitization of a color burst signal.

[Explanation of symbols]

 Reference Signs List 11 signal input terminal 12 A / D conversion unit 13 Y / C separation unit 14 luminance signal processing unit 15 matrix processing unit 16 band amplification unit 17 color signal demodulation unit 18 color synchronization unit 20 color signal processing unit 21, 26, 29 D- F. F. 22 RAM 24 Address counter 31 Memory control unit 32 Burst processing unit 33 OR gate unit

Claims (2)

(57) [Claims] 1. A digital color signal obtained by digitizing a color signal component of a composite video signal, the data of a portion including a burst signal is stored with a write cycle corresponding to the horizontal cycle of the composite video signal. A read control unit that reads, from the memory unit, data of a portion including the burst signal stored with the write cycle for each write cycle, and reads from the memory unit for each write cycle. A maximum amplitude value detector for detecting a maximum amplitude value of a burst signal represented by the data based on the data; and a maximum amplitude value of the burst signal detected by the maximum amplitude value detector being equal to or greater than a first reference value. An amplitude color killer that takes a specific state when a state occurs over a predetermined number of data read from the memory unit for each write cycle. And an amplitude color killer data generating means for transmitting data, and detecting an amplitude value of a specific phase component in each cycle of a burst signal represented by the data based on data read for each writing cycle from the memory unit. Phase component amplitude value detection means, and a cycle of the burst signal in which the amplitude value of the specific phase component detected by the phase component amplitude value detection means is equal to or greater than a second reference value is determined as a specific burst cycle. A specific burst cycle number counting means for counting the number for each data read from the memory unit for each writing cycle; and the number of the specific burst cycles detected by the specific burst cycle number counting means is a predetermined number or more. A phase color that assumes a particular state when the state occurs over a predetermined number of data read from the memory unit for each write cycle. A phase color killer data generating means for transmitting the error data, when the amplitude color killer data takes a particular state,
A color killer data generator configured to transmit, as the color killer signal, the color killer data having the specific state when the phase color killer data has a specific state. 2. A digital chrominance signal whose carrier frequency is f _SC
Specific phase component in each period of the color signal component is that obtained by digitizing at Moto in which the sampling frequency is 4f _SC, a burst signal amplitude is detected by the phase component amplitude value detecting means Is-(B
2. The color killer signal forming apparatus according to claim 1, wherein the color killer signal is a phase component.