JPH01251660A - Hetero junction bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a hetero junction bipolar transistor wherein the miniaturization of an intrinsic transistor region and the reduction of a parasitic capacitance are easily enabled, by forming an emitter layer composed of a first conductor layer and a second semiconductor Iayer whose impurity concentration is higher than the first semiconductor layer, and forming a collector layer so as to include the second semiconductor layer. CONSTITUTION:On a semiinsulative GaAs substrate 2, the following are grown in order by MBE method; a high concentration collector layer 3 composed of an N<+> GaAs layer, an undoped collector layer 4u composed of an I-GaAs layer, and a first base layer 51 composed of P<+> GaAs layer. After that, in a part 12 to be turned into the intrinsic part of a transistor, the first base layer 51 is etched and eliminated, and silicon being N-type dopant is ion- implanted in the part where the collector layer 4u is exposed, thereby forming an active ion implanted region 4i. Then a second base layer 52, an emitter layer 6 and a high concentration emitter layer 7 are selectively grown in a specified pattern. Thereby the intrinsic transistor region 12 can be made fine, without using annealing art which is difficult to be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a heterojunction bipolar transistor and a method for manufacturing the same.

(US technology) - Terojunction bipolar transistors (hereinafter referred to as 7-HBT) are expected to be applied as next-generation ultra-high speed and ultra-high frequency devices. The performance of HBT is limited by the time taken for minority carriers to pass through the base layer and the collector nitride layer, and the charging time of parasitic capacitance that is increased by the device structure. Therefore, in order to improve the crystal performance, K is determined by the size of the entire device. It is necessary to reduce the parasitic capacitance and parasitic resistance by eliminating all unnecessary structures.

Conventional Yoterojunction bipolar transistors have a mesa-type transistor structure in which the main layers of emitter, base, and collector are all multilayered epitaxial layers, but each epitaxial layer is doped with impurities. However, parasitic capacitance depending on the device structure inevitably occurs.

FIG. 6 is a cross-sectional view showing the structure of a conventional heterojunction bipolar transistor.

In this conventional example, a semi-insulating Ga A, s substrate 2 is used.
A highly concentrated collector consisting of an n+-CfaAs layer with a thickness of 5000 J: m3.A base layer consisting of an n-C1aAs layer of 500 OA and a base layer of 5.300 OA n-kl 63G
A high concentration emitter layer 7 consisting of an n-UaAs layer of 100 OA is successively grown, and then a predetermined pattern is formed by the insulating region 1 formed by ion implantation of high concentration protons. Highly emitter layer in the area partitioned into 7. Electrodes ge, 8b, and g are formed on the base layer 5 and high-intensity collector layer 3 exposed by etching, respectively.
It has a structure with c. In this conventional example, low concentration protons are ion-implanted particularly into the collector layer 4 in the external transistor region 13.
By forming h, the parasitic collector capacitance in the external transistor region 13 is reduced.

FIG. 7 is a cross-sectional view of another conventional example, in which the emitter layer structure is grown before the collector layer structure.
The structure of a top heterojunction bipolar transistor is shown. This conventional heterojunction bipolar transistor is manufactured in the same manner as shown in FIG. 6, except that oxygen ions and magnesium ions are implanted into the external transistor region 13 instead of protons. The advantage of the collector-top structure is that no parasitic collector capacitance occurs due to its structure, but electron injection from the emitter that does not contribute to transistor operation occurs in the external transistor region 13, so it has the disadvantage that the circulation gain is reduced. be.

The oxygen ion resident region 110 is for inactivating the emitter layer 6, and the magnesium ion region 11m is for restoring the base layer 5 damaged by oxygen ion implantation. This suppresses electron injection from the emitter in the external transistor region 13,
The drawbacks of the collector-top type heterojunction bipolar transistor have been overcome.

(Problems to be Solved by the Invention) However, in the conventional a-structure HBT manufactured by mesa etching, the size of the intrinsic region of the transistor is determined by the mesa size, so it is difficult to effectively miniaturize the transistor. To achieve this, a fine mesa processing technology is required, but in addition to this, advanced conductor dry etching technology is required, and even if the mesa can be made finer, the contact resistance of the electrode will increase due to the finer electrode size. A problem arises.

Regarding the t1 collector top type HBT, there are specific problems related to ion implantation. In other words, after implanting impurity ions such as magnesium into the base layer of the external transistor region 13, annealing is performed at a high temperature to fully activate the implanted impurity. There is a risk that the base impurity in the transistor region 12 will diffuse.Furthermore, in order to increase the total height resistance of the external emitter region, the implanted impurities such as oxygen ions are activated at the same time during activation annealing of the external base layer, resulting in high resistance. There is a problem that the effect of resistivity is easily lost, and it is difficult to control the annealing conditions!ff1J.

The purpose of the present invention is to easily realize miniaturization of the intrinsic transistor region and reduction of parasitic capacitance without relying on advanced semiconductor dry etching technology or annealing technology - Terojunction single polar transistor and its manufacture The purpose is to provide a method.

(Defined means for deciding issues) The heterojunction bipolar transistor of the present invention is:

In a heterojunction bipolar transistor having a layered structure in which an emitter N (collector layer), a base layer, and a collector layer (emitter 1~) are sequentially formed on a semiconductor substrate, the emitter layer (collector layer) is a first semiconductor layer. A collector layer (emitter layer) which is sandwiched between the first semi-integrated layer, is composed of a second semiconductor layer having a higher impurity concentration than the first semi-integrated layer, and is located above the second semi-integrated layer. The second semiconductor layer is formed to entirely encompass the second semiconductor layer.

The first method of manufacturing a heterojunction bipolar transistor of the present invention includes the steps of sequentially forming an emitter layer (collector layer) and a first base layer and forming a first isolated F$ film on a conductive substrate. , a step of forming an opening for forming a collector layer (emitter layer) in the first insulating film, a step of forming a side wall made of a second insulating film on the 1H11 surface of the opening, and forming a 1FJil wall. a step of converting the emitter l1lj (collector layer) immediately below the opening into an emitter NI (collector layer) with a high impurity concentration;
After removing the No. 11 wall, the second base layer and the collector layer (emitter layer) are selectively formed in the opening above the upper surface of the emitter layer (collector layer) having a high impurity concentration.

The second uninvented method for manufacturing a heterojunction bipolar transistor includes sequentially forming an emitter layer (collector layer) and a first base layer, forming an insulating film on top of a conductor, and then forming an insulating film on the insulating film. Step 7: forming an opening, and once the opening is formed, the entire insulating film is used as a mask to remove the 10 base layer by etching, and then ion implantation of impurities is performed to form an ion-implanted region in the emitter layer (collector layer). forming or etching away the first base layer after forming the entire ion-implanted region;
The method includes the steps of widening the opening of the insulating film on the base layer by side etching, and then selectively forming a second base layer and a collector layer (emitter layer) entirely within the opening.

(Function) Due to the structure of the heterojunction bipolar transistor of the present invention, the size of the intrinsic transistor region 12 is the same as that of the region that is doped with a relatively high degree of sieving in the instep of the collector layer (emitter layer in the case of collector-top type). Although it is determined by the size, this high α degree doped region can be easily miniaturized by the manufacturing method of the present invention, so it can be used as a substantial intrinsic transistor region regardless of the size 14 of the emitter mesa (collector mesa in the case of collector top type). 12 miniaturization becomes possible.

Furthermore, in order to miniaturize the intrinsic transistor region 12 without sacrificing the entire electrode contact area of the emitter (collector) layer, electrode formation is facilitated by making the emitter (collector) mesa size 14 optically larger. It is OT to completely prevent the increase in electrode contact resistance due to miniaturization of the sib vise.
become capable.

(Embodiment) Next, an embodiment of the present invention will be described with reference to all the drawings.

FIG. 1 is a sectional view of a heterojunction bipolar transistor according to a first embodiment of the invention.

The first embodiment in FIG.
+ A high concentration collector layer 3 made of an n-GaAs layer with a thickness of 5000 A on the As substrate 2, an undoped collector layer 4u made of a 1-GaAs layer with a thickness of 5000 A, and ioo.

After the first base layer 51 made of a p-GaAs layer of 0 + A is grown by the sequential MBE method, the first base layer 51 is grown in a portion 12 which is to become the intrinsic region of the transistor.
'r etching is removed and silicon, which is an n-type dopant, is ion-implanted into the exposed portion of the collector layer 4u to form an active ion-implanted region 41. Second base M 52 , h, 2500A emitter layer made of -41.3GaO, 7As; 6. High a degree emitter #7 made of n-GaAs of 10000+A is selectively grown in a predetermined pattern. The result is nine heterojunction bipolar transistors.

Each transistor 1 is partitioned by a disconnection region 1 of a desired pattern, and includes a fully exposed portion of the collector layer and a first
N poles 8c, 8b, and 8e are provided in the base layer 51 and high concentration emitter layer 7, respectively. In addition, the collector
A top type heterojunction bipolar transistor can be manufactured in exactly the same manner.

FIG. 2 shows a heterojunction bipolar transistor according to a second embodiment of the present invention! It is an ar view.

In the heterojunction bipolar transistor of this second embodiment, the first base layer 51a, whose base is in direct contact with the pole 8b, consists of p U a 5bxA s l-x. In general, p-type Garb has a characteristic of low contact resistance with the electrode, and in non-examples, the first
The base layer 51a is a compositionally graded layer in which the Sb composition increases with growth.

FIG. 3 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a method of manufacturing a collector-top type heterojunction bipolar transistor according to a third embodiment of the present invention.

First, as shown in Figure 3 ta+, semi-insulating Oa A
After a high concentration emitter layer 7, an undoped emitter layer 6u, and a first base layer 51 are sequentially grown on the s-substrate 2, a first insulating film 91 made of Si3N4 is formed. Next, an opening 20 to become a collector mesa is formed in the first insulator a91 by dry etching. 5 in the dark
A second insulating film 92 made of i02 is formed over the entire surface including the entire opening s20.

Next, as shown in FIG. 3 tb+, the second insulating film 92 is etched by an anisotropic etching method to form the open Q portion 2C.
1) A side wall 92A is formed on the side surface. First insulating film 9
1 and side wall 92A' as a mask.

After only the first base layer 51 made of p-GaAs is completely etched away, an ion-implanted region 61 is formed in the undoped emitter layer 6u by ion-implanting Si, which is an n-type dopant.

Next, as shown in FIG. 3, the side wall 92A made of SiO2 is etched away using buffered hydrofluoric acid while leaving the first insulating film 91. Next, opening 2
A second base layer 52 made of p-GaAs, collector layer 4 made of n-GaAs, + collector layer 4 made of n-GaAs, selectively made by the molecular beam epitaxial (MBE) method in By sequentially crystal-growing the concentrated collector layer 3, only the intrinsic transistor region 12 of the emitter layer is doped with impurities, completing a collector-top type heterojunction bipolar transistor with almost no parasitic injection from the emitter to the base.

FIG. 4 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a fourth embodiment of the invention.

First, as shown in FIG.
+ undoped emitter layer 5u, first base layer 51°, first insulating film 91 and II;I+ wall 92 in opening 20 are formed.

Next, as shown in FIG. 4+DI, after forming a trench that completely penetrates the seven-band single-band emitter layer 6u from the surface of the first base layer 51 by dry etching, the emitter region in this trench is filled with fiJ containing dopant TF. o, 3 (jaO, 7
A buried growth region 6g of As is entirely formed.

Formation of grooves! Although side etching is suppressed by using a dry etching method since the depth of the 'iI groove is deep, etching may be performed by combining wet etching and dry etching.

Next, as shown in Figure 4 (C1), the opening 20A VCMB
Selectively by method E, the second base pigeon 52. Collector J
fk4. The high collector layer 3 is lengthened to allow the completion of a heterojunction bipolar transistor.

FIG. 5 is a sectional view of a semi-integrated chip for explaining the manufacturing method of a collector-top type heterojunction bipolar transistor according to a fifth example of the invention.

First, as shown in Figure 5, a high concentration emitter layer 5u is formed on the GaAs substrate 2.

First base layer 51'? In order? : is grown, and then an insulating layer M'l made of 5i02 with a thickness of 200 OA is formed on the entire surface. Subsequently, a 7-inch photoresist film 10t was formed and patterned to form an opening 21. After that, this photoresist film 10' (as an i-mask, the entire insulating film 9 was opened by dry etching, leaving only the photoresist film 10. Si, which is a dopant for nfjl, is ion-implanted into the undoped emitter j1F*6u to form an ion-implanted region 61.

Next, as shown in FIG.
An insulating film 9 is formed using Budsfurd hydrofluoric acid as a mask.
After side etching is performed to widen the opening area of the e-ray film 9, the photoresist 1JI110't- is removed.

Below, as shown in FIG.
゜Collector layer 4 and high concentration collector layer 3 are sequentially grown with gold to complete the Peter junction bipolar transistor.

In the third and fourth embodiments shown in FIGS. 3 and 4, collector-top type heterojunction bipolar transistors have been explained as examples, but heterojunction bipolar transistors with a normal structure can be similarly applied. In this case, the external collector region contains impurities! Therefore, it is possible to create a structure with extremely small parasitic base-collector capacitance.

(Effects of the Invention) As explained above, according to the present invention, it is possible to miniaturize the substantial intrinsic transistor region 12 without using advanced semiconductor dry etching technology or difficult-to-control annealing technology, and still reduce the mesa area. Since it can be made larger than the all-intrinsic transistor region, electrical contact between the upper part of the mesa and the electrode can be facilitated. Therefore, as devices are miniaturized, the parasitic capacitance is reduced, but the electrode contact resistance increases. This has the effect of significantly improving the high-speed and high-frequency characteristics of Peter junction bipolar transistors.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of the first and second embodiments of the present invention, and FIGS. 3 to 5 are semiconductor chips for explaining the third to fifth embodiments of the present invention. , WJ6, and FIG. 7 are cross-sectional views of an example of a conventional heterojunction bipolar transistor. DESCRIPTION OF SYMBOLS 1... Insulating region, 2... Ga As substrate, 3...
...High concentration collector layer, 4...Collector layer, 41...
- Active ion implantation region, 4u... Undoped collector layer, 5... Base layer, 6... Emitter layer, 61...
・Ion implantation region, 6g... Buried growth region, 7.
...High concentration emitter layer, 8b...Base t1M, 8c
...Collector electrode, 8e...Emitter electrode, 9...
・Insulating film, 10... Photoresist layer, llh...
Proton implantation region, l1m... Magnesium ion implantation region, 110... Oxygen ion implantation region, 12...
Intrinsic transistor region, 13... External transistor region, 20.21... Opening, 51151a... First
base layer, 52... second base layer, 91... first insulating film, 92... second insulating film, 92A... side wall. Agent Patent attorney Shin Uchihara Reiju area 7 Life Enic Co. 2:
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Claims (3)

[Claims] (1) In a heterojunction bipolar transistor having a layer structure in which an emitter layer (collector layer), a base layer, and a collector layer (emitter layer) are sequentially formed on a semiconductor substrate,
The emitter layer (collector layer) is composed of a first semiconductor layer and a second semiconductor layer sandwiched between the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; A heterojunction bipolar transistor characterized in that an upper collector layer (emitter layer) is formed to include the second semiconductor layer. (2) forming a first insulating film on a semiconductor substrate on which an emitter layer (collector layer) and a first base layer are sequentially formed, and forming a collector layer (emitter layer) on the first insulating film;
a step of forming an opening for formation, a step of forming a sidewall made of a second insulating film on the side surface of the opening, and a step of forming an emitter layer (collector layer) directly under the opening where the sidewall is formed with an impurity concentration. After removing the sidewall in the opening, forming a second emitter layer (collector layer) in the opening including the upper surface of the emitter layer (collector layer) with a high impurity concentration.
1. A method for manufacturing a heterojunction bipolar transistor, comprising the step of selectively forming a base layer and a collector layer (emitter layer). (3) forming an insulating film on the semiconductor substrate on which the emitter layer (collector layer) and the first base layer are sequentially formed, and then forming an opening in the insulating film; and the step of forming an opening in the insulating film, and After removing the first base layer by etching using the film as a mask, impurity ions are implanted to form the emitter layer (
collector layer) or etching away the first base layer after forming the ion implantation region, and forming an opening in the insulating film on the etched first base layer. A method for manufacturing a heterojunction bipolar transistor, comprising the step of widening the opening by side etching, and then selectively forming a second base layer and a collector layer (emitter layer) within the opening.