JPH01251142A - Program trace system - Google Patents

Abstract

PURPOSE:To omit the rewriting of an address instruction and to reduce an OS load by setting all addresses showing the trace points at an address matching means and at the same time deciding the conditions via firmware based on a trace condition list. CONSTITUTION:An address matching register means 11 is provided for setting some addresses showing the trace points. Then a trace condition list is provided for setting the trace conditions for each address set at the means 11. An instruction address to be executed is compared with those addresses set at the means 11 for detection of the arrival at a trace pointer. In this case, the corresponding trace conditions are taken out of the trace condition list via the firmware processing. Then the conditions are decided. Based on the result of this decision, a trace interruption is produced to the OS.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) This invention Concerning a program tracing method suitable for tracing.

(Prior art) When trying to dynamically trace the behavior of a program,
Conventionally, the instruction (original instruction) at the address to be set as a trace point in the relevant program is first replaced with a special instruction, and the original instruction is saved in a predetermined area.In this state, the special instruction is replaced at the trace point. Generates an interrupt when executing the operating system (O8)
After collecting trace information within the program, the original instruction that had been saved was executed to return to the interrupt source.

Further, all determinations of various conditions for whether or not to trace are performed within the O8 (by software processing) after an interrupt occurs.

This program tracing method has the following problems.

■There are restrictions on the address (command word) that can be used as a trace point, and it is not possible to set a trace point at an arbitrary location. For example, the address where an indirect instruction instruction word is placed cannot be used as a trace point.

■When a special instruction newly set at the address set as a trace point is executed, an interrupt to O8 occurs, and even if tracing becomes unnecessary as a result, various trace condition judgments are always performed at the interrupt destination O8. This increases processing overhead.

(2) Inserting trace processing in place of a special instruction may result in a timing shift, making it impossible to achieve the purpose of tracing.

■In order to execute the original instruction at the trace point, a special procedure is required to execute the instruction in a single step.

(Problems to be Solved by the Invention) As mentioned above, in the conventional program trace method, there are restrictions on where trace points can be set, and when a trace point is reached, an interrupt is unconditionally inserted into O8. There was a problem that program tracing could not be performed efficiently.

Therefore, this invention solves the problem of making it possible to set trace points without any restrictions and without rewriting instructions, and to reduce O3 (operating system) overhead associated with trace processing. This is an issue that should be addressed.

[Configuration of the Invention (Means for Solving the Problems) This invention provides address match register means for setting a number of addresses indicating trace points,
By providing a trace condition list in which trace conditions are set for each address set in this address match register means, and comparing the instruction address to be executed next with several addresses set in the address match means. The arrival at a trace point is detected, and when this arrival is detected, the corresponding trace condition is extracted from the trace condition list by firmware processing, the condition is judged, and a trace interrupt is generated in O8 according to the result of this judgment. Features.

(Function) According to the above configuration, in order to set a trace point, it is only necessary to set all the addresses to be set as trace points in the address matching means, and there is no need to rewrite the instruction at the corresponding address. . Furthermore, when a trace point is reached, a condition determination according to the trace condition list is performed by firmware processing, and a trace interrupt to O8 is generated only when the condition is satisfied, so that the burden on O8 is reduced.

(Embodiment) FIG. 1 is a block tR diagram showing an embodiment of a computer system to which the present invention is applied. In the figure, 11 is an address match register unit (hereinafter referred to as AMR) having a group of registers for setting several addresses to be used as trace points, and 12 is a program status word (hereinafter referred to as AMR) indicating the status of the program being executed. (referred to as PSW).

A trace instruction bit TRC is assigned to the PSW 12 to indicate whether the program being executed is a program to be traced. 13 is a next location counter (hereinafter referred to as
(referred to as NLOC), 14 indicates a trace point by comparing the instruction address indicated by NLOC13 and some addresses set in AMR11 when the trace instruction bit TRC in PSW12 is a true value. This is a comparison circuit for determining whether or not the target point has been reached.

15 is a trace condition list (hereinafter referred to as TCL) that is prepared corresponding to each register of AMR11 and has an information area used for setting (information indicating) trace conditions of trace points set in the corresponding registers. ), 1B is a trace condition list pointer (hereinafter referred to as TCLP) for indicating the starting position of T CL 15.

T CL P 15 and T CL P 1B are placed, for example, on the main memory, and in particular, T CL P 1G is placed at a predetermined position on the main memory.

17 is an O3 (operating system), and 18 is an O3 (operating system) which, when it is determined by the comparison circuit 14 that a trace point has been reached, determines the trace condition by referring to the TCL 15, and according to the result of this determination, a trace interrupt is issued to the OS 17. It is a microprocessor that generates

Next, the operation of the configuration shown in FIG. 1 will be explained. First, when a program to be traced is executed, several addresses to be used as trace points are set in registers in the AMR 11. In addition, the trace conditions (trace interrupt conditions) for each trace point set in the register in AMR11 are set in the TCL corresponding to that register number.
15 internal information area, and its first address is TCL.
Set to Pl[i. The above setting operation is performed on a task-by-task basis according to instructions from the software, and is performed together with the PSW information setting operation when disbatching a task, for example.

Now, when the above setting operation is performed, the trace instruction bit TRC of the PSW 12 is set to the true value (here, "1") at the start of execution of the program to be traced. This trace instruction bit TRc is a comparison circuit.
4.

The comparison circuit 14 detects the trace instruction bit TR of the PSW12.
During the period when C is the true value (“1”), that is, the period when the trace target program is in the execution state, the address of the next instruction to be executed indicated by NLOC13 and some addresses set in AMR11 are Compare each. Then, the comparison circuit 14 compares the instruction address of N L OC13 with the instruction address indicated by N
It determines that the instruction address indicated by LOC 13 is a trace point and generates an interrupt to microprocessor 18. At the time of this interrupt, the comparator circuit 14 reads AMR1, which had been set to an address that matches the instruction address.
The register number of register 1 in microprocessor 18
give to

When an interrupt from the comparison circuit 14 occurs, the microprocessor 18 executes the instruction at the corresponding address, and then executes the TCLP.
TCL 15 where the start address is specified by l6
Out of the information areas within, the trace conditions (trace condition information) set in the information area corresponding to the register number given by the OS 17 are retrieved and checked to determine whether the trace conditions are met. . This determination is made, for example, by comparing the contents of the main memory, various registers, etc. (not shown) in addition to the PSW 12.

When the microprocessor 18 checks the trace condition and determines that the condition is met, it generates a trace interrupt to the OS 17. As a result, 0817 recognizes that the trace condition is met and collects trace information. On the other hand, if it is determined that the trace condition is not satisfied, the microprocessor 18 refrains from generating a trace interrupt for 0S17 and continues the instruction processing.

[Effects of the Invention] As detailed above, according to the present invention, the following effects can be achieved.

■To set a trace point, all you need to do is set all the addresses you want to use as trace points in the address matching means, and there are no equivalence restrictions on the setting locations.
There is no need to rewrite the instruction at the relevant point.

■Trace condition determination is performed by firmware processing independently from O5 (operating system), and a trace interrupt to O8 occurs only when the condition is met, reducing unnecessary trace processing in O8 and reducing O8 overhead. .

- Unlike the conventional method, trace processing is not inserted by rewriting a special instruction, so timing deviations caused by trace processing can be prevented as much as possible.

■No special operations are required to execute the original instruction at the trace point.

(2) If a trace instruction bit is provided in the program status word (psw) to indicate whether the program being executed is a program to be traced, a trace point can be set for each task.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. 11...Address match register section (AMR), 12
...Program status word (PSW), 13.
...Next location counter (NLOC),
14... Comparison circuit, 15... Trace condition list
゛(TCL), 17...Operating system (
OS), 18...Microprocessor, TRC...
Trace indication bit. Applicant's agent Patent attorney Takehiko Suzue]1;1 F]p

Claims (2)

[Claims] (1) Address match register means for setting several addresses indicating trace points, a trace condition list in which trace conditions are set for each address set in this address match register means, and a trace condition list to be executed next. a comparison means for comparing the instruction address with each address set in the address match register means in order to determine whether the instruction address is the trace point; and a comparison between the comparison means to reach the trace point. firmware means for extracting a corresponding trace condition from the trace condition list and making a condition determination, and generating a trace interrupt to the operating system according to the determination result; A program tracing method characterized in that trace information is collected in response to a trace interrupt. (2) A trace instruction bit is provided in the program status word to indicate whether the program being executed is a program to be traced, and the comparison result of the comparison means is valid only when the trace instruction bit is a true value. A program tracing method according to claim 1, characterized in that: