JPH0124934Y2 - - Google Patents
Info
- Publication number
- JPH0124934Y2 JPH0124934Y2 JP18984083U JP18984083U JPH0124934Y2 JP H0124934 Y2 JPH0124934 Y2 JP H0124934Y2 JP 18984083 U JP18984083 U JP 18984083U JP 18984083 U JP18984083 U JP 18984083U JP H0124934 Y2 JPH0124934 Y2 JP H0124934Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- plating jig
- plating
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007747 plating Methods 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Description
【考案の詳細な説明】
本考案は、半導体集積回路基板を鍍金加工する
際に使用する鍍金治具に関するものである。[Detailed Description of the Invention] The present invention relates to a plating jig used when plating a semiconductor integrated circuit board.
従来、第1図に斜視図で示すような半導体集積
回路基板1を鍍金加工する場合、第2図及び第3
図にそれぞれ正面図及び側面図で示すように、導
電性支持棒2の両側面に長手方向に導電性フラツ
トバー3,3を並設し、先端をSの字形状に折り
曲げ加工した0.3〜1.5mmφの金具4,4……4の
基端部を該フラツトバー3,3の外向主面3a,
3aに長手方向等間隔に半田付け又は熔接してな
るものが鍍金治具として使用されていた。鍍金治
具の金具4,4……4の先端Sの字形とは内方湾
曲部4a,4a……4aと基端側でこれに連なる
外方湾曲部4bとが形成されるようにフラツトバ
ー3,3の外向主面3a,3aに対して直角に折
り曲げ加工してなる形状を称する。そして支持棒
2及びフラツトバー3,3を介して対向配置され
ている前記金具4,4……4の間に半導体集積回
路基板1,1……1を該半導体集積回路基板1,
1……1の側面金属化部1a,1a……1aと前
記金具4,4……4の内方湾曲部4a,4a……
4aの頂点とが導電接触するように弾性的に嵌合
し、図示しない直流電源より同じく図示しない陽
極体にプラスの電圧をフラツトバー3,3及び金
具4,4……4を順次介して陰極となるべき側面
金属化部1a,1a……1aにマイナスの電圧を
印加することによつて半導体集積回路基板1,1
……1は側面金属化部1a,1a……1a上及び
主面金属化部1b,1b……1b上に鍍金され
る。 Conventionally, when plating a semiconductor integrated circuit board 1 as shown in a perspective view in FIG.
As shown in the front view and side view, respectively, conductive flat bars 3, 3 are arranged in parallel in the longitudinal direction on both sides of the conductive support rod 2, and the tips are bent into an S-shape with a diameter of 0.3 to 1.5 mm. The base ends of the metal fittings 4, 4...4 are connected to the outward main surfaces 3a, 3 of the flat bars 3, 3,
3a, soldered or welded at equal intervals in the longitudinal direction, was used as a plating jig. The S-shape at the tip of the metal fittings 4, 4...4 of the plating jig means that the flat bar 3 is shaped so that the inner curved portions 4a, 4a...4a and the outer curved portion 4b connected thereto at the base end are formed. , 3 is bent at right angles to the outward main surfaces 3a, 3a. The semiconductor integrated circuit boards 1, 1, . . . 1 are placed between the metal fittings 4, 4, .
1...1 side metallized portions 1a, 1a...1a and the inwardly curved portions 4a, 4a... of the metal fittings 4, 4...4...
4a are elastically fitted so as to make conductive contact with the apex of 4a, and a positive voltage is applied to the anode body (also not shown) from a DC power source (not shown) sequentially through the flat bars 3, 3 and metal fittings 4, 4...4 to the cathode and By applying a negative voltage to the side metallized portions 1a, 1a...1a, the semiconductor integrated circuit substrates 1, 1
...1 is plated on the side metallized parts 1a, 1a...1a and on the main surface metallized parts 1b, 1b...1b.
しかしながら、上記鍍金治具は、第一に金具
4,4……4の内方湾曲部4a,4a……4aの
それぞれの曲率を一致させるのが困難であること
から、半導体集積回路基板1,1……1の側面金
属化部1a,1a……1aとの接触面積が基板に
よつて異なり、ひいては鍍金厚みの均一化を妨げ
る傾向にあつた。第二にフラツトバー3,3と金
具4,4……4との固着方法が半田付け又は熔接
であるため、金具4,4……4が正確に等間隔に
配置されていないことから、半導体集積回路基板
1,1……1を金具4,4……4に嵌合する工程
を手作業で行わざるを得ず、コスト低減化を妨げ
ていた。第三に半田付けの場合は鍍金液に半田が
溶出し、半導体集積回路基板1,1……1を汚染
することがあつた。 However, with the above plating jig, firstly, it is difficult to match the respective curvatures of the inwardly curved portions 4a, 4a...4a of the metal fittings 4, 4...4. The contact area with the side metallized portions 1a, 1a, . Second, since the flat bars 3, 3 and the metal fittings 4, 4...4 are fixed by soldering or welding, the metal fittings 4, 4...4 are not arranged at exactly equal intervals, which makes it difficult to integrate semiconductors. The process of fitting the circuit boards 1, 1...1 into the metal fittings 4, 4...4 had to be performed manually, which hindered cost reduction. Third, in the case of soldering, the solder sometimes eluted into the plating solution and contaminated the semiconductor integrated circuit boards 1, 1, . . . 1.
本考案は、叙上の欠点を克服するためになされ
たもので、以下図面の実施例を参照し乍ら本考案
を説明する。 The present invention has been made to overcome the above-mentioned drawbacks, and will be described below with reference to embodiments shown in the drawings.
第4図及び第5図は本考案に係る鍍金治具の一
実施例を示し、それぞれ該鍍治具で半導体集積回
路基板を挾持したところの正面図及び側面図であ
る。 FIGS. 4 and 5 show an embodiment of a plating jig according to the present invention, and are a front view and a side view, respectively, of a semiconductor integrated circuit board being held between the plating jig.
5は鍍金治具を示し、胴体5aと基端部が該胴
体5aの長辺に連なり該胴体を介して両側に等間
隔に対向並設されている複数の尖端脚5b,5b
……5bとからなる。該鍍金治具5は厚さ0.3〜
1.5mmの不銹鋼又は鉄を主成分とするフ−プ材を
金型によつて第6図に示す如く両長辺に複数の尖
端脚を有する両櫛歯形状に打ち抜いた後、各尖端
脚の尖端が内向して正面が凹字形状となるように
該尖端脚の基端部付近望ましくは前記胴体5aの
長辺より内側で折り曲げ加工することによつて製
造される。 6は支持棒を示し、前記鍍金治具5
をボルト7により機械的に支持すると共に図示し
ない直流電源より該鍍金治具5に導電する。 Reference numeral 5 denotes a plating jig, which includes a body 5a and a plurality of pointed legs 5b, 5b whose proximal ends are connected to the long side of the body 5a and are arranged opposite to each other at equal intervals on both sides through the body.
...consists of 5b. The plating jig 5 has a thickness of 0.3~
After punching a 1.5 mm hoop material mainly composed of stainless steel or iron into a double comb shape with a plurality of pointed legs on both long sides as shown in Fig. 6, each pointed leg is It is manufactured by bending the proximal end portion of the pointed leg, preferably inside the long side of the body 5a, so that the pointed end faces inward and the front side has a concave shape. 6 indicates a support rod, and the plating jig 5
is mechanically supported by bolts 7, and electrically conductive to the plating jig 5 from a DC power source (not shown).
本考案鍍金治具を用いて半導体集積回路基板
1,1……1を鍍金加工するには、該半導体集積
回路基板1,1……1の側面金属化部1a,1a
……1aと鍍金治具5尖端脚5b,5b……5b
の尖端とが導電接触するように該半導体集積回路
基板1,1……1を尖端脚5b,5b……5bの
間に弾性的に嵌合し、図示しない直流電源より電
圧が印加される。 In order to plate the semiconductor integrated circuit boards 1, 1...1 using the plating jig of the present invention, the side metallized portions 1a, 1a of the semiconductor integrated circuit boards 1, 1...1
...1a and plating jig 5 pointed legs 5b, 5b...5b
The semiconductor integrated circuit boards 1, 1, . . . 1 are elastically fitted between the pointed legs 5b, 5b, .
本考案鍍金治具は前述のようにその製造工程が
すべて機械加工であるため、加工寸法精度が良
く、尖端脚5b,5b……5bを正確に等間隔に
並設することができる。また、尖端脚5b,5b
……5bの先端が尖つているので、半導体集積回
路基板1,1……1の側面金属化部1a,1a…
…1aとの接触面積が基板によつて大きく異なる
ことがない。更にまた、本考案鍍金治具は機械加
工で製造されることから、半田等により鍍金液を
汚染するおそれがない。 Since the manufacturing process of the plating jig of the present invention is entirely machined as described above, the machining dimension accuracy is high, and the pointed legs 5b, 5b, . . . 5b can be arranged side by side at equal intervals with accuracy. In addition, the pointed legs 5b, 5b
. . . 5b has a sharp tip, so that the side metallized portions 1 a, 1 a . . . of the semiconductor integrated circuit substrates 1, 1 .
...The contact area with 1a does not vary greatly depending on the substrate. Furthermore, since the plating jig of the present invention is manufactured by machining, there is no risk of contaminating the plating solution with solder or the like.
以上のように本考案は半導体集積回路基板を鍍
金加工するのに好適な鍍金治具である。 As described above, the present invention is a plating jig suitable for plating a semiconductor integrated circuit board.
第1図は半導体集積回路基板の斜視図、第2図
は第1図の半導体集積回路基板を従来の鍍金治具
で挾持したところを示す正面図、第3図は同じく
側面図、第4図は第1図の半導体集積回路基板を
本考案の一施例に係る鍍金治具で挾持したところ
を示す正面図、第5図は同じく側面図、第6図は
本考案の一実施例に係る上記鍍金治具の製造工程
を示す斜視図である。
1……半導体集積回路基板、5……鍍金治具、
5b……尖端脚。
Fig. 1 is a perspective view of a semiconductor integrated circuit board, Fig. 2 is a front view showing the semiconductor integrated circuit board of Fig. 1 held between conventional plating jigs, Fig. 3 is a side view, and Fig. 4 1 is a front view showing the semiconductor integrated circuit board shown in FIG. 1 being held between plating jigs according to an embodiment of the present invention, FIG. 5 is a side view of the same, and FIG. 6 is a diagram showing an embodiment of the present invention. It is a perspective view showing the manufacturing process of the above-mentioned plating jig. 1...Semiconductor integrated circuit board, 5...Plating jig,
5b... Apical foot.
Claims (1)
長辺に複数の尖端脚を並置して基端部で連ねた両
櫛歯形金属板を、各尖端が内向するように該尖端
脚の基端部付近より凹字形状に折り曲げ加工して
なる半導体集積回路基板の鍍金治具。 In a device for holding a semiconductor integrated circuit board, a plurality of pointed legs are arranged side by side on both long sides, and both comb-shaped metal plates are connected at the base end. A plating jig for semiconductor integrated circuit boards bent into a concave shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18984083U JPS6096840U (en) | 1983-12-07 | 1983-12-07 | Plating jig for semiconductor integrated circuit boards |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18984083U JPS6096840U (en) | 1983-12-07 | 1983-12-07 | Plating jig for semiconductor integrated circuit boards |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6096840U JPS6096840U (en) | 1985-07-02 |
JPH0124934Y2 true JPH0124934Y2 (en) | 1989-07-27 |
Family
ID=30409198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18984083U Granted JPS6096840U (en) | 1983-12-07 | 1983-12-07 | Plating jig for semiconductor integrated circuit boards |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6096840U (en) |
-
1983
- 1983-12-07 JP JP18984083U patent/JPS6096840U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6096840U (en) | 1985-07-02 |
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