JPH01248671A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve erasing characteristics and write characteristics, by increas ing impurity concentration in a third semiconductor region constituting a drain region of a memory transistor, lowering the breakdown voltage of the third semiconductor region, and elevating the breakdown voltage of a first semiconduc tor region organizing a source region. CONSTITUTION:A memory transistor Q1 is constructed by respectively using first and third semiconductor regions as a source region 5 and a drain region 6, and a selective transistor Q2 is constituted by separately employing third and second semiconductor regions as the source region 5 and the drain region 6. In the memory transistor Q1, impurity concentration in the third semiconduc tor region is increased and breakdown voltage thereof is lowered, thus easily generating hot electrons. The hot electrons are injected into a floating gate electrode FG, thus improving erasing characteristics. On the other hand, break down voltage on the first semiconductor region side is elevated, thus enhancing write characteristics. Accordingly, erasing characteristics and writing characteristics can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and in particular to an E
E P ROM (Electrically Er
asable and programmable Re
It is most suitable for application to ad ONLY MEMORY).

[Summary of the invention]

In the nonvolatile semiconductor memory device of the present invention, a control gate electrode is formed on the floating gate electrode and the semiconductor substrate, spanning one side of the floating gate electrode formed on the semiconductor substrate of the first conductivity type, the other side of the floating gate electrode; the side of the control gate electrode opposite to the other side of the floating gate electrode with respect to the one side of the floating gate electrode; First, second, and third semiconductor regions of a second conductivity type are formed in the semiconductor substrate at portions corresponding to the one side portion, respectively. Thereby, it is possible to improve the erasing characteristics and writing characteristics.

[Conventional technology]

Conventionally, a batch erase type EEPROM as shown in Fig. 4 has been used.
(so-called F1a5h EEPROM) is known (for example, JEERJOURNAL OF 5QLIO
-5TATECIRCUITS, VOL, 5C-2
2, pp. 676-682. NO,5,0CTOB
OR1987), as shown in Figure 4, 20E EF
In a ROM, a gate insulating film 22 is formed on the surface of a semiconductor substrate 21 such as a p-type silicon (Si) substrate, and a floating gate electrode (FC) is formed on this gate insulating film 22. There is. An insulating film 23 is formed on the surface of this floating gate electrode FC. Symbol CG indicates a control gate electrode, and this control gate electrode CG is formed astride the floating gate electrode FC. In addition, the semiconductor substrate 2
1, an n-type source region 24 and a drain region 25 are formed in portions corresponding to one side of the control gate electrode CG and one side of the floating gate electrode FC, respectively.

In this conventional EEFROM, data erasing and writing are performed as follows. That is, at the time of erasing, first, a positive voltage V of about 16 V is applied to the drain region 25, a positive voltage VFP' of about 17 V is applied to the control gate electrode CG, and a positive voltage VFP' of about 17 V is applied to the source region 24 and the semiconductor substrate 2.
Ov is applied to each of the transistors 1 and 2, and hot-electrons generated near the pinch-off point near the drain region 25 are injected into the floating gate electrode FC. On the other hand, during writing, the drain region 25
For example, a positive voltage VPP'' of about 21 V is applied to the control gate electrode CG1 source region 24 and the semiconductor substrate IIJi21'', and a Fowler-Nord voltage is applied at the overlapped portion of the drain region 25 and the floating gate electrode FG.
Electrons are extracted from the floating gate electrode FC by the tunnel current of heim.

[Problem to be solved by the invention]

In order to improve the erase characteristics of the conventional EEFROM described above, it is necessary to lower the drain breakdown voltage to facilitate generation of hot electrons.

On the other hand, in order to improve the write characteristics, it is necessary to increase the source-drain breakdown voltage BVos to prevent breakdown even when a higher VPF' is applied to the drain region [25], and to increase the drain breakdown voltage to It is necessary to make it difficult to generate electrons. However, these requirements contradict each other, so conventional EEFRO
The reality is that M is designed based on a compromise between erasing and writing characteristics, and both erasing and writing characteristics have to be sacrificed to some extent. For this reason, conventionally it has been difficult to improve the erasing characteristics and writing characteristics.

Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can improve erase characteristics and write characteristics.

[Means to solve the problem]

The present inventor focused on the fact that in the conventional EEPROM described above, both erasing and writing are performed on the drain region 25 side, which is the reason why it is difficult to improve the erasing characteristics and writing characteristics, The present invention has been devised.

That is, in the present invention, the control gate electrode (CG) straddles one side of the floating gate electrode (FC) formed on the semiconductor substrate (1) of the first conductivity type.
) and formed on the semiconductor substrate (1), on the other side of the floating gate electrode (FC) and opposite to the other side of the floating gate electrode (FG) with respect to one side of the floating gate electrode (FC). First and second electrodes of a second conductivity type are formed in the semiconductor substrate (1) at portions corresponding to the side portions of the control gate electrode (CG) on the side and one side portion of the floating gate electrode (FG), respectively.
This is a nonvolatile semiconductor memory device in which a third semiconductor region (5, 6, 7) is formed.

[Effect]

According to the above means, the memory transistor is configured using the first and third semiconductor regions as the source region and the drain region, respectively, and the third and second semiconductor regions are used as the source region and the drain region, respectively. A transistor is configured. In this memory transistor, hot electrons can be easily generated by increasing the impurity concentration of the third semiconductor region (and lowering its withstand voltage). By injecting these hot electrons into the floating gate electrode, Erasing can be performed efficiently, and therefore the erasing characteristics can be improved.On the other hand, by increasing the withstand voltage on the first semiconductor region side, it is possible to apply a higher voltage to this first semiconductor region. Therefore, the writing characteristics can be improved.Thereby, the erasing characteristics and the writing characteristics can be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment uses the present invention as a bulk erase type EEFRO.
This is an example applied to M.

FIG. 1A shows a planar structure of essential parts of an EEPROM according to an embodiment of the present invention, and FIG. 1B shows a cross section taken along the line X--X in FIG.

As shown in FIGS. 1A and 1B, E
In an EPROM, a field insulating film 2 such as a SiOg film is selectively formed on the surface of a semiconductor substrate 1 such as a p-type Si substrate, thereby providing isolation between elements. A gate insulating film 3 having a thickness of, for example, about 150 layers is formed on the surface of the active region surrounded by the field insulating film 2, and a floating gate electrode FG is formed on this gate insulating film 3. The gate insulator 1193 is made of, for example, a 5iOz film, and the floating gate electrode FG is made of a conductive film such as a polycrystalline Si film doped with impurities. For example, the surface of the floating gate electrode FG has a film thickness of 2
The insulating film 4 of about 0.00 is formed. This insulating film 4
For example, the film is composed of three layers: 5i02 film/Si3N film and film/SiO□ film. Further, reference numeral CG indicates a control gate electrode, and this control gate electrode CG is formed on the floating gate electrode FC and the semiconductor substrate 1 so as to straddle one side of the floating gate electrode FC. This control gate electrode C
G is, for example, a polycide film (polycrystalline S doped with impurities)
It consists of a conductive film such as a layered film (layered film in which a high-melting point metal silicide film is layered on an i-film).

On the other hand, in the semiconductor substrate 1, the floating gate electrode F
and a control gate electrode C on the opposite side to the other side with respect to one side of the floating gate electrode FC.
For example, an n' type source region 5 and drain region 6 are formed in portions corresponding to the side portions of G, respectively. That is, in the EEPROM according to this embodiment, unlike the conventional EEFROM shown in FIG. 4, the floating gate electrode FC is formed on the source region 5 side. These source regions 5 and drain regions 6 have, for example, n-type low impurity concentration regions 5a and 6a, and therefore, in these source regions 5 and drain regions 6, high impurity concentration regions are surrounded by low impurity concentration regions. It has a double structure. These low impurity concentration portions 5a and 6a can relieve the electric field near these source regions 5 and drain regions 6.

Furthermore, in addition to the source region 5 and drain region 6 described above, in the semiconductor substrate 1, for example, an n-type semiconductor region 7 is provided in a portion corresponding to one side of the floating gate electrode FC.
is formed.

In this embodiment, a memory transistor Q is constituted by a floating gate electrode FC, a gate insulating film 3, a source region 5, and a semiconductor region 6.

Further, a selection transistor Q is constituted by the control gate electrode CG, the gate insulating film 3, the semiconductor region 7, and the drain region 6. The memory transistor Q1 and the selection transistor Q connected in series constitute a memory cell. An equivalent circuit of this memory cell is shown in FIG.

Next, the EEPR according to this embodiment configured as described above will be described.
How to use OM will be explained.

First, during erasing, the drain region 6 is applied with a positive voltage VPP of, for example, about 16 V, the control gate electrode CG is applied with a positive voltage VPP' (for example, about 17 V), which is larger than VPP, and the source region 5 and the semiconductor substrate 1 are applied with a positive voltage VPP' (e.g., about 17 V). Apply O■ respectively. In this case, the potential of the semiconductor region 7 is V□-(V
(+ΔV) (where, ■ is the threshold voltage of the selection transistor Q, and ΔVth is the amount of change in the threshold voltage Vth due to the substrate effect.) During this erasing, the drain region of the memory transistor Q1 is Ho-node electrons generated near the pinch-off point near the semiconductor region 7 are injected into the floating gate electrode FG.

Furthermore, during writing, the source region 5 is supplied with a voltage of, for example, 21V.
A positive voltage of about v,, I- is applied to the drain region 6, the control gate electrode CG, and the semiconductor substrate l, respectively, and a Fowler-Nordheim tunnel current is generated at the overlapped portion of the source region 5 and the floating gate electrode FG. electrons are extracted from the floating gate electrode FC.

Note that during reading, a positive voltage VC is applied to the drain region 6.
A positive voltage VCC' is applied to the C1 control gate electrode CG, and Ov is applied to the source region 5 and semiconductor substrate 1, respectively.

Next, the EEPR according to this embodiment configured as described above will be described.
An example of a method for manufacturing OM will be described.

As shown in FIG. 3A and FIG. 1A, first, the semiconductor substrate l
After a field insulating film 2 is formed by selectively thermally oxidizing the surface of the field insulating film 2, a gate insulating film 3 is formed on the entire surface of the active region surrounded by the field insulating film 2 by, for example, thermal oxidation. Next, a conductive film 8 such as a polycrystalline Si film doped with impurities is formed over the entire surface. Next, after forming an insulating film 9 made of a two-layer film, for example, a 5LOx film/5i3Na film, on this conductor film 8, these insulating films 9 are
Then, the conductive film 8 and the gate insulating film 3 are patterned into a predetermined shape by etching to form the shape shown in FIG. Using this resist 10, the conductor film 8, etc. as a mask, n-type impurities such as arsenic (As) are ion-implanted into the semiconductor substrate 1 at a high concentration, thereby covering the semiconductor region 7 with the conductor film 8. Formed in a self-consistent manner. After this, the resist IO is removed.

Next, a 5ift film is formed on the surface of the 5isNa film constituting the insulating film 9, the side surface of the conductive film 8, and the surface of the semiconductor substrate 1 by, for example, thermal oxidation. 5i (h film/Si3Nm film/sto
, while forming an insulating film 4 consisting of three layers of films,
A gate insulating film 3 is formed over the entire surface of the active region. Next, a polycrystalline Si film doped with impurities and a high melting point metal silicide film are sequentially formed on the entire surface to form a conductor film 11 made of a polycide film. After that, a resist 12 having a predetermined shape, for example, is formed on the conductor film 11. Next, using this resist 12 as a mask, the conductor film 11, the insulating film 4,
The conductor film 8 and gate insulating film 3 are sequentially patterned by etching to form a floating gate electrode FG and a control gate electrode CG as shown in FIGS. 1A and 1B. Thereafter, using these floating gate electrodes FC and control gate electrodes CG as masks, ions of, for example, phosphorus (P) are first implanted into the semiconductor substrate 1 at a low concentration, and then ions of, for example, A
After ion implantation of s at a high concentration, annealing is performed to electrically activate these implanted impurities. by this,
A source region 5 and a drain region 6 having low impurity concentration portions 5a and 6a are formed in self-alignment with the floating gate electrode FC and the control gate electrode CG. In this way, as shown in FIGS. 1A and 1B, the target EE
FROM is completed.

According to this embodiment, as described above, erasing is performed by directing hot electrons generated near the semiconductor region 7 to the floating gate electrode F.
On the other hand, writing is performed by injecting electrons in the floating gate electrode FG into the Fowler-No.
This is done by drawing the rdheim tunnel current into the source region 5. That is, in this embodiment, erasing is performed on the semiconductor region 7 side, and writing is performed on the source region 5 side. In this case, since a high electric field exists near the semiconductor region 7 with a high impurity concentration, its withstand voltage is low, and therefore hot electrons are likely to be generated. Therefore, these hot electrons are transferred to the floating gate electrode FG.
Since it can be efficiently injected into the inside, the erasing characteristics can be improved.

Further, by increasing the withstand voltage BVos on the source region 5 side, a higher voltage can be applied to the source region 5 without causing breakdown, so that the write characteristics can be improved. In this embodiment, the electric field 1 near the source region 5 due to the low impurity concentration portion 5a is
B■ due to surface effect. , can be made higher.

As described above, according to this embodiment, erasing characteristics and writing characteristics can be simultaneously improved.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiment, the semiconductor region 7 is formed along the entire length of the active region in the direction along the floating gate electrode FC, but it is not necessary to do so; for example, the semiconductor region 7 is formed only in the center of the active region. It is also possible to form 7.

〔Effect of the invention〕

As described above, according to the present invention, the impurity concentration of the third semiconductor region constituting the drain region of a memory transistor configured using the first and third semiconductor regions is increased to lower its breakdown voltage. By doing so, hot electrons can be easily generated, and by injecting these hot electrons into the floating gate electrode, erasing can be performed efficiently, and therefore, the erasing characteristics can be improved. Furthermore, by increasing the breakdown voltage of the first semiconductor region that constitutes the source region of the memory transistor, it is possible to apply a higher voltage to this first semiconductor region, thereby improving the write characteristics. . Thereby, it is possible to improve the erasing characteristics and writing characteristics.

[Brief explanation of the drawing]

FIG. 1A is a plan view of essential parts of an EEPROM according to an embodiment of the present invention, FIG. 1B is a sectional view taken along the line X-X in FIG. 1, and FIG. EEPRO shown in Figure 1B
3A and 3B are cross-sectional views showing an example of the manufacturing method of the EEPROM shown in FIGS. 1A and 1B in the order of steps, and FIG. 4 is a circuit diagram showing an equivalent circuit of a memory cell of M. 1 is a cross-sectional view showing a conventional batch erasing type EEPROM. Explanation of main symbols in the drawings 1 Two-handed conductor substrate (semiconductor base), 2: Field insulating film, 3: Gate insulating film, 4: Insulating film, 8.11: Conductor film, FG: Floating gate electrode, CG 2 control gate electrode, Ql: memory transistor, Q2: selection transistor. Agent Patent Attorney Tadashi Sugiura TomoEEPROMf > Rebellion 7; Tree 7 (a) EEPROM's servant A is Figure 3B

Claims (1)

[Scope of Claims] A control gate electrode is formed on the floating gate electrode and the semiconductor substrate, spanning one side of the floating gate electrode formed on the semiconductor substrate of a first conductivity type, and the floating gate electrode is formed on the floating gate electrode and the semiconductor substrate. the other side of the control gate electrode opposite to the other side of the floating gate electrode with respect to the one side of the floating gate electrode; and the one side of the floating gate electrode. a first conductivity type of a second conductivity type,
A nonvolatile semiconductor memory device characterized in that second and third semiconductor regions are respectively formed.