JPH01248363A - Clock regeneration circuit - Google Patents

Abstract

PURPOSE:To hold stable phase-locked loop and perform extraction at the optimum point even in fast regeneration where a data rate changes considerably by shifting the phase-locking range of a loop corresponding to the change of the output voltage of a frequency voltage converter based on tape speed and the direction of a tape. CONSTITUTION:The frequency voltage converter 17 to convert a voltage to the one which shifts the central frequency of a voltage controlled oscillator (VCO) 11 by two FG pulses having phase difference of 90 deg. to each other of a timer roller representing the tape speed is provided. Firstly, in ordinary regeneration or the fast regeneration at speed of several (+)/(-) times, the FG frequency of the timer roller is low, therefore, no frequency voltage converter 17 is operated, and a constant voltage is outputted, thereby, the same operation as that of an on-going clock regeneration circuit is performed in the loop. However, in the regeneration at speed of several tens (+)/(-) times, the frequency voltage converter 17 is operated, and the output voltage changes centering a certain voltage based on a frequency value and the direction of the tape. Therefore, the central frequency of the VCO 11 changes, and which becomes the clock frequency of data to be regenerated. In such a way, the loop can always respond stably even in the fast regeneration, and the optimum extraction can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clock recovery circuit suitable for reproduction and high-speed reproduction of digital data.

2. Description of the Related Art A phase synchronization circuit is used as a clock recovery circuit in conventional digital data reproduction, and a block diagram thereof is shown in FIG. 5, 50 is a multiplier that multiplies input digital data, 51 is a voltage controlled oscillator (hereinafter referred to as CO), 52 is a phase comparator (hereinafter referred to as PC), 53 is a charge pump including an LPF, and 54 is a Delay device A555 that delays input digital data is VCo51
Delay device B, 56 that delays the clock from delay device A5
This is a data latch that latches data from 4 using the clock from delay device B55. The operation of the clock recovery circuit configured as described above will be described below. First, when input digital data is input to the multiplier 50, a multiplied pulse of the input data is generated. The multiplied pulse enters the PC 52 together with the output of the VCo 51, a phase comparison is performed, and the phase difference is converted into a voltage in the charge pump 53, which is applied as a control voltage to the VCo 51 to form a loop. Then, the data latch 56 and the delay device A54
The input digital data is latched by the clock from the delay device B55, and the data is extracted.

Problems to be Solved by the Invention However, in the above configuration, the characteristics of the loop are determined by the time constant of L PF in the charge pump 53. Then, in the case of high-speed playback, the input data rate changes significantly, causing the loop to become unable to respond and lose synchronization. Further, even if a response is made, a phase shift occurs and the data latch 56 cannot perform optimal extraction. SUMMARY OF THE INVENTION An object of the present invention is to provide a clock recovery circuit that can perform optimal extraction without causing a loop to respond even when the input data rate changes significantly during high-speed reproduction.

Means for Solving the Problems The present invention provides a multiplier that multiplies input digital data, a voltage controlled oscillator, and a phase comparison that compares the phases of the output of the multiplier and the clock that is the output of the voltage controlled oscillator. a charge pump that converts the phase error output from the phase comparator into a voltage and applies it to the voltage controlled oscillator, a delay device that delays a clock that is an output of the voltage controlled oscillator, and a delay device that delays input digital data. The center frequency of the voltage controlled oscillator is determined from two FG pulses having a phase difference of 90 degrees from each other, from a delay device, a data latch that latches data from the outputs of the two delay devices using a clock, and a timer roller that represents the tape speed. It is equipped with a frequency-voltage converter that converts it into a moving voltage.

Operation The present invention operates as a conventional clock regeneration circuit in normal reproduction and +/- several times higher speed reproduction with the above-described configuration. However, in high-speed playback at +/- several tens of times faster, a voltage that changes +/- around a certain voltage according to the FG frequency of the timer roller that indicates the tape speed is input to the voltage controlled oscillator, and the center frequency changes. , allows the loop response and further performs an optimal extraction.

Example Hereinafter, the present invention will be explained in more detail based on the drawings.

FIG. 1 shows a block diagram of a clock recovery circuit in an embodiment of the present invention. In FIG. 1, 10 is a multiplier that multiplies input digital data, 11 is a VCo, and 12 is a multiplier for multiplying input digital data.
14 is a charge pump that compares the phase of the multiplied signal from the multiplier 10 and the clock from the VCOII.
Delay device A for delaying input digital data, 15
is a delay device B that delays the clock from VCOII,
16 transfers the data from delay device A 14 to delay device B
A data latch 15 latches with a clock, and 17 is a frequency-voltage converter that converts the center frequency of the VCO II into a voltage that moves by two FG pulses having a phase difference of 90 degrees from each other on a timer roller representing the tape speed. The operation of the clock recovery circuit of this embodiment configured as described above will be explained below.

First, during normal playback or high-speed playback at +/- several times the speed, the FG frequency of the timer roller is low, so the frequency-voltage converter does not work and outputs a constant voltage. Then, the inside of the loop operates in the same way as a conventional clock recovery circuit. However, when playing back at a high speed of +/- several tens of times faster, the frequency-voltage converter 17 operates, and the output voltage changes depending on the frequency value and tape direction.
It changes around a certain voltage. Then, the central circular wave number of VCO II changes, and the starting frequency of the reproduced data becomes I92. This is the loop's "Move Itsu range" (
).

As described in 1-1 above, according to this embodiment, when the output voltage of the frequency-voltage converter 17 changes depending on the tape speed and tape direction, the synchronization range of the loop changes accordingly.
Stable synchronization can be maintained even during high-speed playback of +/- several tens of times the speed where I· changes greatly. Historically, data latches can also be extracted at optimal points.

FIG. 2 is a block diagram of a frequency-to-voltage converter showing a second embodiment of the present invention, and FIG. 3 is an operating waveform diagram thereof. In FIG. 2, reference numeral 20 denotes a tape direction detector 21 which generates tape forward and reverse rotation signals from two Q) PC pulses having a phase difference of 90° from each other and representing the tape speed.
is a tape speed detector that produces a signal that activates the tape direction detector 20 when the FG pulse reaches a certain frequency amount I-;
2 is an Ex-or circuit that multiplies the FG pulse; 23.
24 is a monomarna vibrator (M・MA, M−
M13) 25 is a level converter that converts the DC voltage obtained by connecting the outputs of M-MA-B through a resistor matrix to a certain I level. A second device configured as described above.
The operation of the frequency-to-voltage converter ζ according to the embodiment will now be described with reference to FIG.

First, the FG pulse of the timer [7-ra representing the tape speed is input to the tape speed detector 21 by a certain frequency amount -1-
When this happens, it will look like (C) in Figure 3: Nihai I novel. Two FG pulses with a phase difference of 90' rI enter the tape direction detector 20 as shown in FIG. 3(a).
Create a signal like (l). However, the above signal is actually output during the high level period (C), which is the output of the tape speed detector 21. Therefore, the forward/reverse rotation signal of the tape direction detector 20 output during this high level period is E, x-o, which is obtained by multiplying the FG pulse.
5M-MA 2a・M- along with the pulse of r circuit 22
MB2/lζ is input. Therefore, when the tape direction is forward, M-MF324 is used, and when it is reversed, M-MA
23 stop operating, and M-MA 23 outputs a high level and M-MB 24"C outputs a low level. At the same time, the opposite M-M generates a pulse as shown in Figure 23. When a pulse occurs, M
-The output DCC level of Ml decreases, and the output I)C level of M-MB increases. Then two M-M
The I)C voltage obtained by connecting the outputs of the two through a resistor matrix changes around a certain voltage as shown in (I) in FIG. As described above, according to this embodiment, only the two FG pulses of the timer roller, which represent the tape speed and which have a phase difference of 900, can be outputted according to the tape speed and tape direction without changing the signals. Since the voltage can be changed around the center, continuity of voltage change can be maintained. FIG. 4 is a block diagram of a frequency-voltage converter showing a second embodiment of the present invention. In FIG. 4, 21 is a tape speed detector, 23.24 is M/MA, R125
is a level converter, and the above structure is similar to that shown in FIG. The difference from the configuration shown in FIG. 2 is that the tape direction detector is changed to a tape direction detector 40 which generates a forward/reverse rotation signal from a tape direction signal. Other actions and [No! J, similar to the embodiment of FIG.

As described in detail, according to the present invention, the center frequency of the VCO changes in response to changes in the input data rate during high-speed playback, and the loop always responds stably to perform optimum extraction.

Two FG pulses from the timer roller with a phase difference of 90 degrees representing the tape speed, or the capstan servo's playback controller l-D-C pulses and the tape direction signal allow +/- high-speed playback without switching signals. I is proportional to the change in data rate around a voltage that is according to
I) It has a great practical effect because it can generate C voltage and maintain continuity of voltage change.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clock recovery circuit in the embodiment ζ of the present invention, FIG. 2 is a block diagram of a frequency-voltage converter in the second embodiment, and FIG. 3 is a timing waveform diagram in the same embodiment. 4 is a block diagram of a frequency-voltage converter according to the third embodiment, and FIG. 5 is a block diagram of a conventional glue regeneration circuit. IO... Multiplier, 11... V COl 12.
...PC113...Charge pump, 1/l...Delay device A-15...Delay device B, 16...Data latch, 17...Frequency voltage converter, 20...Tape direction detection device, 21...tape speed detector 22...Ex-
or circuit, 23...M-MA, 24...M-MB,
25... Level converter, 40... Tape direction detector, 50... Multiplier, 51... VCO152...
・PCl53...Charge pump, 54...Delay unit A, 55...Delay unit B, 56...Data latch.

Claims (3)

[Claims] (1) A multiplier that multiplies input digital data, a voltage controlled oscillator, a phase comparator that compares the phases of the output of the multiplier and the clock that is the output of the voltage controlled oscillator, and the phase comparator. a charge pump that converts the output phase error into a voltage and applies it to the voltage controlled oscillator; a delay device that delays a clock that is an output of the voltage controlled oscillator; and a delay device that delays input digital data.
A data latch that latches data from the outputs of the two delay devices with a clock, and a timer roller that represents the tape speed. Two FG pulses having a phase difference of 90 degrees from each other are converted into a voltage that moves the center frequency of the voltage controlled oscillator. A clock regeneration circuit characterized in that it has a frequency-voltage converter. (2) A tape direction detector that generates tape forward and reverse rotation signals from two FG pulses with a phase difference of 90 degrees from each other representing the tape speed; and when the FG pulse exceeds a certain frequency, the tape direction detector a tape speed detector that generates an operating signal; an Ex-or circuit that multiplies the FG pulse; and a first pulse that generates a pulse of a certain width from the rising or falling edge of the output pulse of the Ex-or circuit; a second mono-multivibrator; and a second mono-multivibrator;
, a level converter that converts the DC voltage obtained by connecting the output of the second mono multivibrator through a resistance matrix to a certain level, and when the playback speed is several tens of times faster, the tape direction detector is activated and the tape direction detector is activated. Either the first or second mono-multivibrator works by rotating forward or reverse,
2. A clock recovery circuit according to claim 1, further comprising a frequency-to-voltage converter in which the resulting DC voltage varies around a certain potential. (3) It is characterized by having a tape direction detector that generates tape forward/reverse signals based on the tape direction signal, and a frequency-voltage converter that generates a voltage that changes the center frequency of the voltage controlled oscillator based on the capstan servo playback control signal. 2. The clock recovery circuit according to claim 1.