JPH01245703A - Matching circuit for field effect transistor - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the RF characteristic by providing an input side dielectric base having a 1st strip line connecting to a 1st external circuit and an output side dielectric base having a 2nd strip line connecting to a 2nd external circuit so as to eliminate a phase difference in RF signals passing through a FET of a multi-cell structure. CONSTITUTION:A gate electrode 4, an input side strip line 2, a drain electrode 5 and an output side strip line 7 are connected by a metallic line 8. The input side strip line 2 is connected to the input side matching circuit at a point A being at one side of the multi-cell FET 3. The strip line is connected at points A, B located at the cell at the end of the FET to the input/output matching circuit to allow the RF signal passing from the point A to the point B to have no phase difference because the distance is the same even if the RF signal passes any cell of the multi-cell FET. Thus, the deterioration in the RF characteristic due to the phase difference is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a matching circuit for field effect transistors, and more particularly to the shape of a strip line forming the matching circuit.

Conventional technology Conventionally, matching circuits for this type of field effect transistor (hereinafter referred to as FET), especially gallium arsenide field effect transistors, utilize the good characteristics inherent in FETs, and are an important technology as the frequency increases and output increases. It becomes.

Problems to be Solved by the Invention In the conventional matching circuit described above, when considering high output, the FET pellet has a multi-cell structure in which a large number of basic PETs are lined up. is used. The gate electrode 11 of the multiple cell pellet 1° and the strip line 9 on the input side dielectric substrate 8 are connected to the metal wire 15.
Further, the drain electrode 12 and the slip line 14 on the output side dielectric substrate 13 are connected by a metal wire 15.

At this time, in the conventional system, when the RF multiplied signal passes from point A to point B, the distance between passing through the center b cell and passing through the a and c cells at both ends is different, so there is a difference in the phase. arise. In a conventional matching circuit, this phase difference is R
This has the disadvantage of deteriorating the F characteristics.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel matching circuit for field effect transistors, which makes it possible to eliminate the above-mentioned drawbacks inherent in the prior art.

Differences between the invention and the prior art In contrast to the conventional matching circuit described above, the present invention has the following advantages by changing the shape of the strip line forming the matching circuit.
The objective is to eliminate the problematic RF multiplication signal phase difference.

Means for Solving the Problems In order to achieve the above object, the matching circuit according to the present invention increases the distance through which the RF double signal passes through the FET in order to eliminate the phase difference in the RF double signal passing through the FET in other cell structures. It has the characteristic of being the same.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a schematic diagram showing an embodiment of the present invention.

Referring to FIG. 1, reference number 1 is a dielectric substrate for forming an input side matching circuit, 2 is a strip line, 3 is an FET with a multi-cell structure, 4 is a gate electrode, 5 is a drain electrode, and 6 is a Dielectric substrate for forming an output side matching circuit,
Reference numeral 7 indicates a strip line, and reference numeral 8 indicates a metal line for connecting the gate electrode 4 and the input side strip line 2 and the train electrode 5 and the output side strip line 7, respectively.

The input strip line 2 is connected to the input matching circuit from one side (point A) of the multi-cell FET 3. Further, the output side strip line 7 is connected to the output side matching circuit from the other side (point B).

As described in detail, according to the present invention, the RF multiplied signal passing from point A to point B is connected to the input/output matching circuit at point A and point B located in the end cell of the FET. No matter which cell of the cell FET it passes through, the distance is the same and there is no phase difference, eliminating deterioration in RF characteristics due to the phase difference. This provides the effect that the good characteristics of the FET can be fully brought out.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an embodiment of a matching circuit according to the present invention, and FIG. 2 is a configuration diagram of a conventional matching circuit. 1... Dielectric substrate for forming an input side matching circuit,
2... Stripline line, 3... Multi-cell structure FE
T, 4... Gate electrode, 5... Drain electrode, 6.
...Dielectric substrate for forming an output side matching circuit, 7.
...Strip line, 8...Metal connection line, 9...
Dielectric substrate for forming an input side matching circuit, 10...
・Strip line, 11...Multi-cell structure FET =
12...Goo 1~electrode, 13...Drain electrode,
14...Dielectric substrate for forming an output side matching circuit, 15...Strip line, l...Metal connection line Patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai 1.6 : Dielectric material

Claims (1)

[Claims] In a matching circuit using a field effect transistor consisting of many cells and a strip line on a dielectric substrate on the input/output side of this field effect transistor element, a signal is generated from one end cell of the field effect transistor consisting of many cells and the other end is connected to the field effect transistor consisting of many cells. an input-side dielectric substrate having a first strip line connected from a cell to a first external circuit; and an input-side dielectric substrate having a first strip line connecting a cell to a first external circuit; a second circuit connected from the cell to a second external circuit;
and an output-side dielectric substrate having a strip line.