JPH01243530A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01243530A JPH01243530A JP7127488A JP7127488A JPH01243530A JP H01243530 A JPH01243530 A JP H01243530A JP 7127488 A JP7127488 A JP 7127488A JP 7127488 A JP7127488 A JP 7127488A JP H01243530 A JPH01243530 A JP H01243530A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- plasma
- wiring part
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000001257 hydrogen Substances 0.000 abstract description 2
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特にH2ジン
ター技術の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to improvements in H2 ginter technology.
本発明は、半導体装置の製造方法において、全図配線を
形成した後、プラズマ中でH1処理することにより、比
較的低温1こで、全図配線形成時のダメージを大幅に改
善するものである。The present invention is a method for manufacturing a semiconductor device, in which damage caused during the formation of full-figure wiring can be significantly reduced at a relatively low temperature by performing H1 treatment in plasma after forming full-figure wiring. .
従来、全図配線形成後のH,シンターに関しては電気炉
を使用し450℃程度の温度により行なわれていた。Conventionally, H and sintering after the entire wiring has been formed has been carried out using an electric furnace at a temperature of about 450°C.
この14.シンターエ(呈は、トランジスターのソース
、ドレイン領域と全図配線とが良好な接触杢得られる様
にするためと、全図配線形成時のダメージを回復させる
ための2つの目的がある。後者のダメージの回復には、
従来の電気炉では450℃fX [fの温度が必要であ
った。ところが前者のソース、ドレイ/領域と全図配線
の良好な接触を実現するには400℃程度の温度がΔ当
であり、逆に450℃まで温度を上げると、ソース、ド
レイン領域と全図配線接触部に81が析出する事により
接触抵抗が高くなる問題が発生する。年々半導体素子の
微細化が進み、これに併ない、ソース、ドレイン領域と
全図配線とを接触させるためのコンタクトホールの径も
小さくなってきており、Si析出による接触抵抗増加が
重大な問題となっできている。This 14. Sintering has two purposes: to obtain good contact between the source and drain regions of the transistor and the full wiring, and to recover from damage caused during the formation of the full wiring. For the recovery of
Conventional electric furnaces require a temperature of 450°C fX [f]. However, in order to achieve good contact between the source, drain/region and the entire wiring in the former case, a temperature of about 400°C is necessary for Δ, and conversely, if the temperature is raised to 450°C, the contact between the source, drain/region and the wiring in the entire wiring is Δ. A problem arises in that the contact resistance increases due to the precipitation of 81 at the contact portion. Semiconductor devices are getting smaller and smaller every year, and the diameter of the contact hole used to connect the source and drain regions to the entire wiring is also becoming smaller, and increased contact resistance due to Si precipitation has become a serious problem. It is becoming.
本発明は、このような従来の半導体装置の製造方法の問
題点を解決するもので、その目的とするところは、より
高集積化に対応でき、特性の安定した半導体装置の製造
方法を提供するところにある。The present invention solves the problems of the conventional semiconductor device manufacturing method, and aims to provide a semiconductor device manufacturing method that can accommodate higher integration and has stable characteristics. There it is.
本発明の半導体装置の製造方法は、全図配線形成後、4
00℃以下の温度にてH,プラズマ処理することを特徴
とする。In the method for manufacturing a semiconductor device of the present invention, after forming the entire diagram wiring,
It is characterized by H and plasma treatment at a temperature of 00°C or lower.
第1図は、本発明の実施例における半導体装置の概略図
である。FIG. 1 is a schematic diagram of a semiconductor device in an embodiment of the present invention.
全図配線形成後のウェハー3をチャンバ7内の400
’Cに温度コントロールされた下部電極2上にセットす
る。そして排気口6よりチャンバ7内を真空排気し、H
,ガス又はNH,ガス等をガス導入口5より導入し、上
部電極1もしくは下部電極2に高周波4を印加し水素プ
ラズマを発生させ、400℃に温度コントロールされた
ウェハー3に所定のH,プラズマ処理を行なう。The wafer 3 after complete wiring is placed in the chamber 7 at 400°C.
It is set on the lower electrode 2 whose temperature is controlled to 'C. Then, the inside of the chamber 7 is evacuated from the exhaust port 6, and H
, gas or NH, gas, etc. are introduced through the gas inlet 5, and a high frequency wave 4 is applied to the upper electrode 1 or the lower electrode 2 to generate hydrogen plasma. Process.
第2図に全図配線形成時のダメージの回復を、N型トラ
ンジスターのしきい電圧(V t h)をパラメータに
示す。第2図から明らかなように所定のVth (0,
7V)が400″C30分(D H!プラズマ処理にて
得られている。それに対して従来の電気炉の場合は、第
3図に示したように、4゜OoCでは所定のVth (
0,7V) は得うレず、450℃30分処理が必要で
ある。FIG. 2 shows recovery from damage during full wiring formation using the threshold voltage (V th ) of the N-type transistor as a parameter. As is clear from FIG. 2, the predetermined Vth (0,
7V) is obtained by plasma treatment at 400''C for 30 minutes (DH!).On the other hand, in the case of a conventional electric furnace, as shown in Fig. 3, the predetermined Vth (
0.7V) was not obtained and required treatment at 450°C for 30 minutes.
以上述べたように本発明によれば、全図配線形成時のダ
メージ回復を400″C以下のH,プラズマ処理にて行
なうことができるので、ソースー、ドレイ/領域と全図
配線の接触抵抗の最適化がけがられ、半導体装置の歩留
り、特性の安定化、向上が可f1しとなる。As described above, according to the present invention, damage recovery during the formation of full-figure wiring can be performed by H, plasma treatment at 400"C or less, so that the contact resistance between the source, drain/region and full-figure wiring can be reduced. Optimization is improved, and the yield of semiconductor devices and the stabilization and improvement of characteristics become f1 possible.
第1図は、本発明による実施例の半導体装置の概略図で
ある。
第2図は、本発明によるダメージ回復するまでの時間を
N型トランジスターのしきい電圧をパラメーターとした
グラフ。
第3図は、従来の電気炉によるダメージ回復するまでの
時間をN型トランジスダ一のしきい電圧をパラメーター
としたグラフ。
■・・・上部電極 2・・・下部電極3・・・ウェ
ハー 4・・・高周波5・・・ガス導入口 6・
・・排気ロア・・・チャンバ
以 上
出願人 セイコーエプソン株式会社
A1口
第1色
第3目FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a graph using the threshold voltage of an N-type transistor as a parameter for the time taken to recover from damage according to the present invention. Figure 3 is a graph using the threshold voltage of an N-type transistor as a parameter for the time it takes to recover from damage caused by a conventional electric furnace. ■... Upper electrode 2... Lower electrode 3... Wafer 4... High frequency 5... Gas inlet 6.
...Exhaust lower...Chamber and above Applicant: Seiko Epson Corporation A1 Port 1st color 3rd eye
Claims (1)
下の低温にてプラズマ中でH_2ジンターする工程から
なることを特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device, comprising the step of forming full wiring on the surface of a semiconductor substrate and then performing H_2 gintering in plasma at a low temperature of 400° C. or lower.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7127488A JPH01243530A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7127488A JPH01243530A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01243530A true JPH01243530A (en) | 1989-09-28 |
Family
ID=13455970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7127488A Pending JPH01243530A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01243530A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012216737A (en) * | 2010-05-18 | 2012-11-08 | Hitachi High-Technologies Corp | Heat treatment apparatus |
JP2013123028A (en) * | 2011-11-08 | 2013-06-20 | Hitachi High-Technologies Corp | Heat treatment apparatus |
-
1988
- 1988-03-25 JP JP7127488A patent/JPH01243530A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012216737A (en) * | 2010-05-18 | 2012-11-08 | Hitachi High-Technologies Corp | Heat treatment apparatus |
JP2013123028A (en) * | 2011-11-08 | 2013-06-20 | Hitachi High-Technologies Corp | Heat treatment apparatus |
US9490104B2 (en) | 2011-11-08 | 2016-11-08 | Hitachi High-Technologies Corporation | Heat treatment apparatus |
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