JPH01243475A - Semiconductor element - Google Patents

Abstract

PURPOSE:To reduce junction capacitance, and to increase a voltage gain by providing an n<-> type low impurity-concentration region only on an n-type active- region surface layer section between a gate and a drain and making the exten sion of a depletion layer larger than a section between the gate and a source. CONSTITUTION:Junction capacitance CGS between gate-source 3, 4 and, junction capacitance CGD between gate-drain 3, 5 are shaped to an epitaxial growth layer section having constant impurity concentration, but a section between the gate-drain 3, 5 is formed in structure in which a low impurity-concentration region 10 is shaped. Consequently, only junction capacitance CGD between the gate-drain 3, 5 can be reduced by the elongation of a depletion layer 11 in the low impurity-concentration region 10. As a result, junction capacitance CGD between the gate-drain 3, 5 can be made lower than junction capacitance CGS between the gate-source 3, 4, thus improving the ratio of CGS to CGD. Accord ingly, a junction type field-effect transistor having high voltage gains is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, particularly a junction field effect transistor (JFET), such as a JFET for low noise amplification with a large voltage gain.

[Conventional technology]

As the performance of consumer video cameras and broadcast cameras continues to improve, there is a demand for higher performance JFETs used in the first stage amplification thereof.

JFETs have high input impedance and low noise characteristics, and are widely used not only in consumer equipment such as audio amplification, FM, and TV tuners, but also in communications industry equipment. for example,
Published by Kogyo Kenkyukai (Electronic Materials J, February 1979 issue, February 1, 1979, pages 32 to 36) shows an example in which a JFET is combined with a conventional bipolar element.

This document also describes specific application examples for which combination with rJFET is desired, such as various amplifiers with high input impedance and low cross-modulation, low-noise amplifiers for audio, etc., and low-noise amplifiers for cameras, smoke sensors, etc. current input amplifier,
Examples include amplifiers that include various switching functions with low crosstalk that prevent control signals from influencing non-control signals. ” is stated.

The JFET has a structure as shown in FIG. That is, an n-type active region 2 is provided on the main surface of a p+-type semiconductor substrate 1 made of silicon, and a gate (G) made of a p-domain layer is formed on a part of the surface of this n-type active region 2. ef
An f-range 3 is provided.

Also, sandwiching this gate region 3, a source (S) tI region 4 consisting of an n◆decade layer is provided. A drain (D) 6i region 5 is provided. Further, the main surface of the semiconductor substrate 1 is partially covered with an insulating film 6. Then, the game DI area 3. Source area 4. an electrode electrically connected to the drain region 5;
In other words, the gate electrode (not clearly shown in the figure).
, a source electrode 7, and a drain electrode 8 are provided. The gate electrode is used while being electrically connected to the semiconductor substrate 1.

Note that the n-type active region 2 is electrically independent in a p-type isolation region 9. Further, the n-type active region 2 is formed by epitaxial growth or ion implantation, and has a uniform impurity concentration.

Therefore, the source-gate junction capacitance and the gate-drain junction capacitance in the active region are expressed as a certain ratio.

[Problem to be solved by the invention]

The voltage gain (Gv) to the downstream stage of a JFET for a video camera preamplifier is determined by the capacitance of the image element (C1) and the source-to-gate capacity of the JFET! (ccs) and the gate-drain capacitance (CG11) of the JFET, that is, (1
) is shown by the formula.

In the conventional technology, when changing the JFET device parameters to lower the junction capacitance, both CG S and rCGD decrease, and there is little benefit in improving voltage gain.
An object of the present invention is to provide a semiconductor device having a high voltage gain junction field effect transistor.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the JFET of the present invention has p÷ made of silicon.
A gate consisting of a shaped semiconductor substrate, an n-type active region provided electrically independently on the main surface of the semiconductor substrate, and a p◆-type region provided in the surface layer of the n-type active region. an n◆-type source region and a drain region provided on the surface layer of the n-type active region 2 so as to sandwich this game HJI region; and an n◆-type source region and a drain region between the gate region and the drain region.
The structure has an n-type low impurity concentration region provided in the surface layer of the active region.

[Effect]

According to the above means, the JFET of the present invention has a gate
Since the n-type low impurity concentration region is provided only in the surface layer of the n-type active region between the drains, during FET operation, the n-type low impurity concentration region has a higher concentration than between the gate and source. Since the depletion layer extends well, the junction capacitance can be reduced. Therefore, in the JFET of the present invention, the gate-drain capacitance can be reduced without changing the gate-source capacitance, and the voltage gain can be improved.

【Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, an example in which the present invention is applied to a single junction field effect transistor will be described.

FIG. 1 is a schematic diagram showing the main parts of a JFET according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the main parts of the same JFET.
Figures 3 to 5 are cross-sectional views of a wafer at each step in the manufacture of the same JFET. Figure 3 is a cross-sectional view of a wafer with an n-type low impurity concentration region formed, and Figure 4 is FIG. 5 is a cross-sectional view of a wafer with a gate region formed thereon, and FIG. 5 is a cross-sectional view of a wafer with a source region and a drain region formed thereon.

Junction field effect transistor (JFET) of this example
has a structure as shown in FIG. That is, on the main surface of the p-type (first conductivity type) semiconductor cutting board 1,
(second conductivity type) is provided, and this n
A layer consisting of a p+ type layer on a part of the surface of the active region 2 of the shape)
(G) A tI region 3 is provided. Further, a source (S) 8U region 4 consisting of an n+ type layer is sandwiched between this gate region 3.
A drain CD) SIN region 5 is provided.

The semiconductor substrate l is made of a p-type silicon crystal substrate, and the n-type active region 2 has an impurity concentration N of 2.
It is formed of an epitaxially grown layer having a specific resistance ρ of 0°28Ω. Further, the impurity concentration of the source region 4 and drain region 5 is lX
10"cm-', and the impurity concentration of the gate region 3 is 5×10"cm-3.

On the other hand, the main surface of the semiconductor substrate 1 is partially covered with an insulating film 6. The gate SN region 3, the source region 4. An electrode electrically connected to the drain region 5, ie, a source electrode 7. A drain electrode 8 is provided.

The gate Nl region 3 is used while being electrically connected to the semiconductor substrate 1.

On the other hand, this is a characteristic feature of the present invention, in which the surface layer of the n-type active region 2 between the gate region 3 and the drain region 5 has an n-type (second conductivity type) low-conductivity layer. An impurity concentration region 10 is provided. This low impurity concentration region 10 has an impurity concentration of approximately 5×10” cm −3 .

Such a JFET has a gate region 3 and a drain region 5.
between the n type active region 2 and the impurity concentration lower than the n type active region 2
Since the −-shaped low impurity concentration region 10 is provided, as shown in FIG.
In this region, the depletion layer 11 extends further under the same bias conditions than in the n-type active region 2 portion between the gate region 3 and source region 4, so that the junction capacitance CGD can be reduced.

As a result, even when using an epitaxially grown layer whose entire region has a constant impurity concentration, the gate-drain junction capacitance C0 remains unchanged, without changing the gate-source junction capacitance CCS.
can be reduced. Therefore, as can be seen from the above equation (1), the ratio between 0.3 and CGD is improved, and the voltage gain can be increased.

Next, we will discuss the manufacturing method of such a JFET in the third section.
This will be explained with reference to FIGS.

First, a semiconductor substrate (wafer) 15 is prepared.

This wafer 15 consists of a p-type (first conductivity type) silicon substrate (semiconductor substrate) 1, and has a main surface with
An n-type (second conductivity type) epitaxial growth layer 16 is provided. The epitaxial growth layer 16 has, for example, an impurity concentration N of 2X IO"cm-" and a resistivity of 0. It is 28Ω. The main surface of such a wafer 15 is partially coated with a photoresist film 17.
is provided. This photoresist film 17 is exposed and developed, and only the portion located between the gate and drain of the finished product is removed. Next, using the photoresist film 17 as a mask, a p-type impurity (boron) is implanted by ion implantation to form an n-type low impurity 4-degree head region 10.

Note that after this, a JFET is manufactured according to the normal JFET process specifications, but the low impurity concentration region 1
0 means that the impurity concentration will ultimately be 5X10IScm- even if there is a thermal effect in subsequent annealing or subsequent steps.
The ion dose landscape is determined so that '. In the following steps, as mentioned above, it is important to keep the doped p-type impurity in a predetermined position, so surface oxidation is performed at low temperature and high pressure oxidation, and isolation region formation is performed using ion Dedication is essential.

Next, the photoresist film 17 is removed.

Further, an insulating film made of a SiO□ film or the like is formed on the main surface of the wafer 15, and this insulating film is partially removed by common photolithography. and,
Using this insulating film as a mask, ions such as boron (B) are implanted at a high concentration to form a p+ type isolation region 9 that penetrates the epitaxial growth Jii 16 and reaches the semiconductor substrate 1. Therefore, the region surrounded by this isolation region 9 has an electrically independent n
This becomes the active region 2 of the shape.

Next, on the main surface of the wafer 15, as shown in FIG. 4, an insulating film 18 made of a Sin film or the like is provided. A region of this insulating film 18 corresponding to a gate formation region is removed by photolithography. Thereafter, p'' type gate region 3 is formed by ion implantation.

This gate region 3 has an impurity concentration of 5×10”
It is about cm-3. Further, this gate region 3 is formed so as to be in contact with the low impurity concentration region 10, for example.

Next, on the main surface of the wafer 15, as shown in FIG. 5, an insulating film 19 made of a Sin film or the like is provided. Regions of this insulating film 19 corresponding to source/drain formation regions are removed by photolithography. Thereafter, n+ type source region 4 and drain region 5 are formed by ion implantation. These source region 4 and drain region 5 have an impurity concentration of lXl0''c
It is about m-3. Further, one side of the drain region 5 is formed so as to be in contact with the low impurity concentration region 10 .

Therefore, the surface layer of the n-type active region 2 between the gate HN region 3 and the drain region 5 has an impurity concentration of I
The structure is such that an n-type low impurity concentration region 10 of about 1016 cm-'' is provided.

Next, an insulating film 6 is formed on the main surface of the wafer 15, and this insulating film 6 is partially removed by photolithography, and a source electrode and a drain electrode are formed. Further, a passivation film is formed on the surface of the wafer 15. Thereafter, this wafer 15 is divided vertically and horizontally to form JFET elements (
JFET chips) are manufactured in large numbers.

According to such an embodiment, the following effects can be obtained.

(1) The junction field effect transistor of the present invention has a gate and an epitaxial growth layer with a constant impurity concentration.
A source junction capacitance I CG s and a gate-drain junction capacitance C1 are formed, but since the structure has a low impurity concentration region formed between the gate and drain, the gate-drain junction capacitance C,. An effect can be obtained in that only the depletion layer can be reduced by the extension of the depletion layer in the low impurity concentration region.

(2) According to (1) above, the junction field effect transistor of the present invention can reduce the gate-drain junction capacitance C0, compared to the gate-source junction capacitance C0. As a result of being able to improve the ratio, it is possible to provide a junction field effect transistor with a high voltage gain.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, even if the n-type active region is formed by ion implantation, the same effect as in the embodiment described above can be obtained. Further, in the above embodiment, a p-type semiconductor substrate is used, but an n-type semiconductor substrate may be used.

In the above explanation, the invention made by the present inventor was mainly applied to the manufacturing technology of a single junction field effect transistor, which is the background field of application, but the invention is not limited to this. It can be similarly applied to the production of standardized semiconductor devices.

The present invention can be applied to the manufacture of semiconductor devices having at least junction field effect transistors.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In the junction field effect transistor of the present invention, an n-type low impurity concentration region is provided only in the surface layer of the n-type active region between the gate and drain, and the spread of the depletion layer is made larger than that between the gate and source. Since we are trying to reduce the capacity,
An improvement in voltage gain can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the main parts of a JFET according to an embodiment of the present invention, Fig. 2 is a cross-sectional view showing the main parts of the same JFET, and Fig. 3 is a schematic diagram showing the main parts of the same JFET. Figure 4 is a cross-sectional view of a wafer with a gate region formed thereon, Figure 5 is a cross-sectional view of a wafer with a source and drain region formed thereon, and Figure 6 shows the main parts of a conventional JFET. FIG. ■... Semiconductor substrate, 2... N-type active region, 3...
- Gate region, 4... Source region, 5... Drain region, 6... Insulating film, 7... Source electrode, 8...
Drain electrode, 9... isolation region, lO.
...Low impurity concentration region, 11...Depletion layer, 15...
Wafer, 16...Epitaxial growth layer, 17...
Photoregis No. 1 Fig. 2 Fig. 2-7 L type 117I gong first binding Ei No. 3 Fig. 1θ Fig. 4 Fig. 5 Fig. 6

Claims (1)

[Claims] 1. A source consisting of a first conductivity type semiconductor substrate, a second conductivity type active region provided on the main surface of this semiconductor substrate, and a second conductivity type with high impurity concentration provided in the surface layer of this active region. A semiconductor element having a junction field effect transistor having a gate region of a first conductivity type provided on a main surface of the active region between the source region and the drain region, A semiconductor device comprising: a low impurity concentration region of a second conductivity type provided on the main surface of the active region between a gate region and a drain region.