JPH01243133A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To fix a RAM in a fixed condition at the time of checking by providing a condition setting circuit to switch the control signal of the RAM to a prescribed fixing signal. CONSTITUTION:A condition setting circuit 30 is standardized as a kind of macro cells, incorporated in a RAM 20, and composed of a write address port 23, a read address port 24, and two-input logic gates G23-25 made to intervene in respective bit lines of a write control port 25. Respective logic gates G23-G25 are commonly operated by an external terminal Px provided for a test. Thus, even when the RAM 20 and a logic circuit 10 except for the RAM 20 are not completely separated and reconnected, while both are partially connected in a condition close to a real action condition, the logic circuit 10 can be checked regardless of the condition of the RAM 20.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and furthermore, to an RA'
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device incorporating M (Random Access Memory), for example, a technique that is effective when applied to a gate array with a built-in RAM.

[Prior Art] This type of semiconductor integrated circuit device has operating conditions such as RAM
Because it changes in many different ways depending on the state of memory, it has been extremely difficult to test or diagnose it.

For example, in the case of a gate array with built-in RAM, even if you attempt to test the operation of peripheral logic circuits other than RAM configured using the standard cell method, the operating conditions of the peripheral logic circuits will vary in a complex manner depending on the storage state of the built-in RAM. Therefore, a large number of test operations are required.

Normally, in testing a semiconductor integrated circuit device, a pre-prepared pattern is given from the outside to cause the semiconductor integrated circuit device to perform a simulated operation, and the state that appears externally due to this simulated operation is observed. This is done by evaluating the results (see, for example, "rLSI Handbook" published by Ohm Publishing Co., Ltd.), pages 665-166.

However, in the above-mentioned RAM-embedded semiconductor integrated circuit device, the operating conditions vary greatly depending on the state of the RAM, so it is extremely difficult to create a test pattern for inspection, and the The pattern data size becomes extremely large.

Therefore, in order to streamline the inspection or diagnosis of the above-mentioned semiconductor non-product circuit device, the present inventors divided the RAM and logic circuits other than the RAM at the time of inspection, and reconnected both parts so that they could be accessed directly from the outside. We considered installing a switching circuit.

In this way, the logic circuit can be tested without being affected by the state of the RAM, making it easier to create test patterns for testing.

[Problems to be Solved by the Invention] However, the inventors have found that the two-part technique has the following problems.

In other words, a switching circuit that divides RAM and non-RAM logic circuits during inspection and reconnects both parts so that they can be accessed directly from the outside requires a large number of signal switching circuit sections, which reduces the circuit size. becomes larger,
This results in the layerer occupying a large area within the semiconductor integrated circuit device. As a result, the area of the layerer 1 for forming the circuits required for actual operation is reduced.
This results in a decline in the functionality of the semiconductor integrated circuit device. In particular, in the case of a gate array, since the switching circuit described above is composed of single cells, a problem arises in that the number of cells that can be used to form the circuits necessary for actual operation is greatly reduced.

Further, since the switching circuit described above differs depending on the configuration of the logic circuit, the switching circuit must be newly designed together with the logic circuit. This also causes the problem that the burden on the designer increases.

An object of the present invention is to use a relatively simple additional circuit to remove logic other than RAM built into a semiconductor integrated circuit device without degrading the functions necessary for actual operation or increasing the burden on the designer. The objective is to provide a technology that allows circuit inspection to be performed properly and efficiently.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the RA built in the semiconductor integrated circuit device
A state setting circuit is provided to switch the control signal of M to a predetermined fixed signal, and this state setting circuit allows the above R to be set during inspection.
This is to fix AM in a constant state.

[Operation] According to the above-mentioned means, the RAM and the logic circuit other than the RAM do not have to be completely disconnected and reconnected, but they can be left partially connected in a state close to the actual operating state. Logic circuits can be tested without being affected by the state of RAM.

As a result, logic circuits other than RAM built into semiconductor integrated circuit devices can be tested using relatively simple additional circuits without degrading the functions necessary for actual operation or increasing the burden on designers. The purpose of being able to do this properly and efficiently is achieved.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

In addition, in the figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a schematic configuration of a semiconductor integrated circuit device to which the technology of the present invention is applied.

A semiconductor integrated circuit device 100 shown in the figure is configured as a RAM'M built-in type array, and includes a peripheral logic circuit 10, a RAM 20, and a state setting circuit 3o.

Peripheral logic circuit] O and the state setting circuit 30 are arbitrarily designed using standard cells. In addition, RAM20 is
Cells with certain functions are standardized and prepared as a type of macro cell. Functions necessary for actual operation are constituted by peripheral logic circuit 10 and RAM 20.

The peripheral logic circuit 10 exchanges data and signals with the outside via the terminal Px, and connects the RA as necessary.
By accessing M20, a predetermined function is realized.

The RAM 20 cannot be directly accessed from an external terminal Px, but is accessed via a peripheral logic circuit. This RAM 20 is of a so-called multi-port type, and has write data ports 1 to 21 for inputting write data WD and read data R.
It independently has a read data port 22 for outputting I). In addition to these, write address 1-23 for inputting write address WA, read address RA
It has read address ports 1-24 for inputting , and write control ports 1-25 for inputting a write control signal (write enable) WE. Each port 21-2
5 are connected to the peripheral logic circuit 10, respectively.

The state setting circuit 30 is standardized and incorporated as a kind of macro cell in the RAM 20, and is interposed in each pin 1 to line of the write address port 23, the read address port 24, and the write control port 25, respectively. 2-input logic gate (NOR gate) G23. G24. G
25. Each logic game 1-023. G2
4. G25 is commonly operated by an external terminal Px provided for testing.

Here, when the test external terminal pt is L (low level), each logic game hG23. G24 and G25 are states in which the write address WA, read address RA, and write control signal WE given from the peripheral logic circuit 10 side are transmitted as they are to the ports 1-23, 24, and 25 on the RAM 20 side and inputted. It is in. That is, the state setting circuit 30 at this time is not involved in the state of the RAM 20.

On the other hand, when the external terminal pt for test 1 is set to H (high level) by an external operation, the write address WA and read address RA given from the peripheral logic circuit 10 are fixed addresses (all 0 ), and the write control signal WE is also fixed to the write setting state (H). That is, the addresses WA and RA and the control signal WE input to the RAM 20 via the peripheral logic circuit 10 are fixed at a constant logic state.

As a result, the write data WD inputted from the peripheral logic circuit 10 to the write data port 21 of the RAM 20 is transmitted as is to the read data port 22 of the RAM 20 and returned to the peripheral logic circuit]0. In this state, when the peripheral logic circuit 10 is tested by applying a predetermined pattern from the external terminal Px, the RAM 20 is regarded as just a data path, so it is not affected by the state of the RAM 20. In addition, it is possible to efficiently test only the peripheral logic circuit 10. Furthermore, since the RAM 20 operates as a data path, there is no need to provide a separate path that is used only during inspection.

As described above, even if the RAM 20 and the logic circuit 10 other than the RAM 20 are not completely disconnected and reconnected, the state of the RAM 20 can be changed by keeping them partially connected in a state close to the actual operating state. The logic circuit 10 can be tested without being influenced by the What should be noted here is that the state setting circuit 30 can be configured with only a few logic gates interposed in port 1- of the RAM 20, and that the circuit configuration is similar to that of the peripheral logic circuit 1.
This means that it can be made the same regardless of the configuration of 0. Thereby, the state setting circuit 30 can be standardized together with the RAM 20 as a macro cell, and the designer can design a system without considering the state setting circuit 30.

Therefore, in the semiconductor integrated circuit device 100 described above,
With a relatively simple additional circuit, the RAM built into the semiconductor integrated circuit device 100 can be installed without degrading the functions necessary for actual operation or increasing the burden on the designer.
Logic circuits 10 other than 20 can be tested properly and efficiently.

FIG. 2 shows a schematic configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention.

In the embodiment shown in the figure, the state setting circuit 30 is interposed only in the address ports 23 and 24 of the RAM 20, and the write control ports 1 to 25 are connected to the peripheral logic. It is directly connected to the circuit 10. As a result, the RAM 20 in the test state receives the write control signal WE input from the peripheral logic circuit 10 to the write control boards 1 to 25.
It is designed to operate as a parallel latch circuit using 1 as the rigger clock. In this case as well, the RAM 20 can be inspected as a simple latch circuit, so as in the case described above, a relatively simple additional circuit can be used without degrading the functions necessary for actual operation. , and without increasing the burden on designers]
The logic circuit 10 other than the RAM 20 built into the OO can be properly and efficiently tested.

Hereinafter, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

For example, the RAM 20 has more data ports.
- may be of the type.

In the above explanation, the invention made by the present inventor was mainly applied to a RAM built-in gate array, which is the field of application that formed the background of the invention. It can also be applied to normal semiconductor RAM.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, by using a relatively simple additional circuit, it is possible to improve the R
The effect is that logic circuits other than AM can be properly and efficiently tested.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a block diagram showing an outline of a semiconductor integrated circuit device according to a second embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a built-in RAM, characterized in that the semiconductor integrated circuit device has a built-in state setting circuit for fixing the RAM to a constant state in response to an external command. Device. 2. Claim 1 comprising a RAM, a logic circuit other than the RAM, and a state setting circuit that sets the address and control signal input to the RAM via the logic circuit to a predetermined fixed state. The semiconductor integrated circuit device described in . 3. A RAM having independent write data ports and read data ports, a logic circuit that configures a predetermined logic system using this RAM, and the above-mentioned R from this logic circuit.
A semiconductor integrated circuit according to claim 1 or 2, further comprising a state circuit that sets a state in which a signal input to a write data port of an AM is transmitted as is to a read data port. Device.