JPH01239948A - Test of wafer - Google Patents

Abstract

PURPOSE:To shorten the necessary time by a method wherein each item for a first wafer is tested in accordance with the sequence and manner which have been decided in advance and each item of subsequent wafers is tested after the sequence and manner have been changed on the basis of a result of a preceding test. CONSTITUTION:For individual chips, of a first wafer 3 of a lot, in a region specified by a region-specifying apparatus 2 on the basis of a data in a memory 4, all test items (a)-(d) are tested in the sequence which has been input to a controller 8; the number of the chips which have passed this test is stored in counter parts 6a-6d in a counter 6; the number of the chips which have passed the test of all the items is stored in a memory 9. For a second wafer, the sequence of the test is changed on the basis of an obtained result of the test in such a way that the item which has been rejected in most chips is first tested; when the number of the chips which have passed the test of each item is less than the preset number of good chips and rejected products occur continuously, the test inside a specified region is executed; when the number of the good chips exceeds the preset number of the good chips and the rejected products do not occur continuously, the test of the item for a sampling inspection is not executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a wafer testing method carried out during the manufacture of semiconductor integrated circuits and the like.

(Prior Art) In manufacturing semiconductor elements such as semiconductor integrated circuits, a large number of semiconductor elements are formed on one wafer, and such wafers are manufactured simultaneously in lots of about several dozen pieces. .

After testing each element on the wafer for a number of items using a tester, the wafer is divided into individual elements. In this wafer test, a defective chip in which an abnormal state is detected for any test item is marked and removed from subsequent processing.

In conventional wafer testing, test items, their order of execution, and manner of implementation (e.g., 100% inspection, sampling inspection, etc.) are predetermined, and all wafers are tested using the same items, order, and manner. will be held.

(Problem to be Solved by the Invention) If an abnormal state occurring in a chip is detected by a test item that is performed late in a wafer test, many items may be detected before that test item. The abnormal condition cannot be detected until after the test has been performed. This results in unnecessary repeated tests, which increases the time required to detect the abnormal condition and reduces the efficiency of tester usage. There is a problem that the amount decreases.

A sudden accident during the wafer fabrication stage may cause the same type of abnormal condition to occur in many wafers in the same lot. In such a case, the above-mentioned problem becomes more serious because it takes a long time to detect the abnormal state and is repeated on many wafers.

The present invention was made in view of the current situation, and
The purpose of this is to shorten the time required for wafer testing, and prevent unnecessary repetition of tests even when the same abnormal condition occurs on wafers from the same lot.
An object of the present invention is to provide a wafer testing method that enables efficient operation of a tester.

(Means for Solving the Problems) The wafer testing method of the present invention is a method in which a plurality of wafers each having a plurality of elements formed thereon are sequentially tested for a plurality of items. tests each item in a predetermined order and manner,
For subsequent wafers, each item is tested by changing the order and manner based on the test results of the previous wafer, thereby achieving the above objective.

(Example) Examples of the present invention will be described below.

FIGS. 1A and 1B are flowcharts showing a general flow of an embodiment of the method of the present invention. FIG. 2 is a block diagram showing a schematic configuration of an integrated circuit tester for implementing this embodiment.

The tester shown in FIG. 2 includes a tester main body 1, an area specifying device 2
, first memory 4, test signal generator 5, counter 6,
It includes an n-ary counter 7, a controller 8, a second memory 9, and an alarm generation circuit 10. Reference numeral 3 indicates a wafer to be inspected.

The controller 8 controls the test sequence, and each predetermined test item and its execution order are input. In this example, test item a
, b, c, and d are predetermined to be performed in this order. The first memory 4 stores the names of test items (hereinafter referred to as "sampling target items") that may be used as sampling tests (item d in this embodiment), the set number of non-defective products nx, the number of continuous non-defective products ny, and the number of non-defective products in the wafer. The specified area is stored in advance. The test signal generator 5 sends out signals for performing each test item a to d.

First, a first wafer of a certain lot is set in a tester, and each chip within a region on the wafer 3 specified by the region specifying device 2 is tested based on data in the first memory 4. All test items a to d are performed on all chips on the wafer in the order input to the controller 8. The number of chips that passed each item a to d is stored in counter sections 6 a to 6 d of the counter 6 corresponding to each item. The number of non-defective chips that passed all the items is counted, and the result is stored in the second memory 9.

Further, the test results for each chip within the specified area stored in the first memory 4 are also stored in another storage area of the second memory 9. Once all chips within the designated area have been tested, if no defective products have occurred within the designated area for item d, which is the item to be sampled, item d will be sampled in subsequent tests. Tests in other areas are performed with these settings.

When the test on the first wafer is completed, the controller 8 determines the order of execution of each test item on the second wafer and the Ra of execution based on the obtained test results. Determine. That is, the order of execution is changed and set so that the items with the largest number of defective chips are executed first.

If the number of passing chips for each item is less than the set number of non-defective products nX, or if defects occur continuously within the designated area, it is considered that an abnormality occurred during the wafer manufacturing process. Therefore, only the second and third wafers are tested within the designated area, the results are recorded in the first memory 4, and the alarm generator 10 generates an alarm. Further wafer testing for that lot is canceled.

On the other hand, the number of passing chips for each item is the set number of good chips n
If the number of defects is greater than or equal to x and defects do not occur continuously within the designated area, the second and subsequent wafers of the same lot are tested as follows.

Each item is tested on each chip according to the modified order of implementation as described above. As a result of the test, the n-ary counter 7 is incremented each time one chip passes the test, and when a chip fails, the n-ary counter 7 is reset. When the value of the n-ary counter 7 reaches the number of consecutive good products ny stored in advance in the first memory 4 (i.e.,
(If ny non-defective products are obtained in succession), sampling target item d is not performed in subsequent tests. After that, when a defective product occurs and the n-ary counter 7 is reset, item d is tested again. When the value of the n-ary counter 7 reaches ny again, item d is not tested. Repeat this below.

In the above-mentioned embodiment, regarding the change in the execution order, the execution order of each test item on the second wafer is changed based on the test results on the first wafer, and the changed execution order is applied to subsequent wafers. However, the only change in the implementation aspect is the implementation aspect of the items to be sampled. However, the method of making these changes is not limited to this, and can be changed as appropriate depending on the importance of each test item, the frequency of occurrence of defective products, etc. For example, based on the test results of the previous wafer, , the actual order and its aspects may be changed, or test results of the same lot may be accumulated and changes may be made based on the accumulated test results.

(Effects of the Invention) According to the wafer testing method of the present invention, the order and mode of implementation of test items are changed based on the test results of the previous wafer, so items with a high frequency of failure are placed first. As a result, defective products can be detected quickly without repeating unnecessary tests, and the time required for wafer testing can be shortened. Therefore, wasted time spent on testing even for abnormal lots can be minimized, the tester can be used efficiently, and the throughput of the tester can be improved.

Figures 1A and 1B are flowcharts for explaining an embodiment of the present invention, and Figure 2 is a block diagram showing a schematic configuration of a tester to which the embodiment is applied.

3... Wafer, 4... First memory, 7... N-ary counter, 8... Controller.

that's all

Claims (1)

[Claims] 1. A method in which a plurality of wafers each having a plurality of elements formed thereon are sequentially tested for a plurality of items, the first wafer being tested for each item in a predetermined order and manner. and for subsequent wafers,
A wafer test method in which each item is tested by changing the order and mode based on the test results of the previous wafer.