JPH01235331A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To shorten the heat treatment time and to reduce the occurrence of a hot spot and the concentration of a surface electric field by a method wherein, after an N-type epitaxial growth layer has been formed on one main face of a silicon wafer, an N-type layer is distributed again by a heat treatment and a low-concentration and thick N-type layer is formed. CONSTITUTION:An N-type epitaxial growth layer 12 is formed on an N-type silicon substrate 11. After this N-type epitaxial growth layer 12 has been formed, a pushing diffusion operation is executed. When this pushing diffusion operation is executed, an N-type impurity in the epitaxial growth layer is diffused to the N<-> layer 11 due to a difference in concentration; a concentration gradient on the side of an N-layer near a junction of the N<-> layer and the N-layer becomes gentle. Since the low-concentration and thick N-layer can be formed by epitaxial growth in this manner, the heat treatment time can be shortened sharply.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method of manufacturing semiconductor devices such as thyristors.

B9 Summary of the Invention The present invention performs N-type epitaxial growth on one main surface of a silicon wafer, and then heat-treats it to form a deep, low-concentration N-type diffusion layer, which is required for high forward blocking voltage and silicon risk. At the same time, it is possible to significantly shorten the heat treatment time when forming this N-type diffusion layer, and it is possible to manufacture a semiconductor element with less generation of hot spots and less concentration of surface electric field.

The C0 prior art thyristor is PN-r-'N (P
Emitter 1. It has a four-layer structure: N-base 2, P base 3, and N emitter 4). In this case, as the forward blocking voltage increases, it is necessary to increase the thickness of the N-base layer 2 in order to prevent the space charge layer from penetrating into the P emitter layer. Therefore, a problem arises in that the forward voltage drop becomes large.

Therefore, recently, a relatively high concentration N layer 5 is formed in the N-base 2 as shown in FIG.
It has been proposed to prevent the RI load layer from penetrating into the P emitter layer 1 to obtain a thin N-base layer 2, that is, to obtain a high forward voltage device with a small forward voltage drop. To form the N layer 5, deposit the N layer on the substrate (N-base) 2 as shown in FIG.
One-shot diffusion is performed (Fig. 8(b)).

The thickness of the N layer 5 must be determined not only by the spread of the space charge layer within the N layer 5 but also by the diffusion length of minority carriers from the P emitter layer I.

The diffusion length of minority carriers depends on their lifetime, but when the lifetime of minority carriers is several μsec, the diffusion length is 5KV.
In order to obtain a similar forward blocking breakdown voltage, the N layer 5 needs to have a considerable thickness of about 60 to 100 ltm. Furthermore, considering the influence of the P emitter on the injection efficiency, the peak impurity concentration of the N layer 5 is required to be several orders of magnitude lower than the surface impurity concentration of the P emitter I.

D1 Problems to be Solved by the Invention However, in order to deeply diffuse the N-type impurity at a low concentration, it is necessary to perform heat treatment at a high temperature for a long time.

For example, an appropriate amount of phosphorus is deposited as an N-type impurity on an N-type silicon wafer with a substrate concentration of 1.5 X I 013 cm-', and this is pushed in and diffused (oxidized) to give a peak impurity concentration of I X I 1 cm-3. If the diffusion depth is 100 μm, it will take about 300 hours at 1250°C.

Therefore, another method has been considered in which the N layer 5 shown in FIG. 8(b) is entirely formed by N-type epitaxial growth. Although this method does not require high-temperature and long-term heat treatment like the above-mentioned methods, it has the following major drawbacks.

(2) In thyristors and the like, after forming this N layer, a P base and a P emitter layer are formed by diffusing P type impurities. In this method, as shown in FIG. 9, since all NG is formed by the epitaxial growth layer, the P emitter 1 is formed in a spike shape at the crystal defects that occur during epitaxial growth, and the P emitter 1 is formed in the form of a spike, causing the P base WJ3 and the N - When a reverse voltage is applied to the junction with layer 2, a so-called hot spot occurs in which the leakage current locally increases due to a local punch-through phenomenon in the spike-shaped portion. This hot spot not only deteriorates the forward breakdown voltage characteristics of the device, but also causes permanent destruction of the device. Since the incidence of crystal defects that occur during epitaxial growth increases in proportion to the area, this becomes a problem especially when attempting to increase the area of the device.

■Since the N layer is formed only by epitaxial growth,
As shown in FIG. 10, the concentration gradient on the N layer side near the junction between the N- layer and the N layer becomes quite steep.

In thyristors and the like, after forming this N layer, a surface treatment called bevel is performed to form a P base layer, a P emitter layer, and an N emitter layer to achieve normal breakdown voltage characteristics. The purpose of this bevel is to weaken the surface electric field so that the breakdown voltage at the surface is not too low compared to the theoretical breakdown voltage of the main junction between the P base layer and the N- layer. On the other hand, in a structure in which the N base layer is composed of an N- layer and an N layer, the steeper the concentration gradient on the N layer side near the junction between the N layers, the more the surface electric field is concentrated in that part. It becomes easier to do. Therefore, with this method of forming the N layer using only epitaxial growth, even if the surface electric field is weakened by the bevel, the surface electric field is concentrated in the N layer, so there is a problem that only a breakdown voltage characteristic that is considerably lower than the theoretical breakdown voltage can be achieved. There is.

Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can significantly shorten the heat treatment time when forming a deep N-type diffusion layer with a low a degree, and also reduces the occurrence of hot spots and concentration of surface electric field. purpose.

E Means for solving the problem An N-type epitaxial cell growth layer is formed on the main surface of a silicon wafer (substrate) by epitaxial cell growth, and then this is heat-treated to redistribute the N-type layer to form a low concentration layer. Form a thick N-type layer.

F1 action Most of this N layer is formed by the growth of long-term cells, and the interface between the substrate and the long-term cell growth layer is N-
It is formed by joining the layer and the N layer. Furthermore, the N-type impurity in the extracellular growth layer diffuses into the N- layer due to the concentration difference, and the concentration gradient on the N-layer side near the junction between the N-1 and N layers becomes gentle.

G. Example An embodiment of the present invention will be described below.

First, as shown in FIG. 1(a), an N-type silicon substrate 11
Then, an N-type epitaxial cell growth layer 12 is formed. The concentration distribution at this time was as shown by the dotted line in FIG. After forming this N-type epitaxial growth layer 12, forced diffusion is performed. When forced diffusion is performed, the N-type impurity in the epitaxial growth layer becomes N-F! due to the concentration difference. j11, and the concentration gradient on the N layer side near the junction of the N− layer and the N layer becomes gentler, as shown in practice B in FIG. To explain a more specific example, the substrate concentration is 8×lO cm
-', diameter 10011. Impurity concentration 1°5×I on one side of a 570 μm thick N-type FZ crystal silicon wafer
When N-type epitaxial growth was performed to a thickness of 80 μm and a thickness of 80 μm, and forced diffusion was performed at 1250° C. for 60 hours, a layer with a concentration distribution as shown in FIG. 3 was obtained.

Furthermore, when gallium was diffused into this wafer under heat treatment conditions of 1250 DEG C. for 60 hours, a layer with a single distribution as shown in FIG. 4 was obtained.

This wafer was cut into a disk with a diameter of 88zx, the end face was beveled to weaken the surface electric field, and the end face was further protected with a passivation go, and the withstand voltage of the main junction was measured. As a result, despite the large diameter (large area) element with a diameter of 88 square centimeters, there were no hot spots, and the leakage current was less than 1 mA, and the breakdown voltage was 6000 V, which was almost the same as a single theoretical breakdown voltage. It was done.

1-1. Effects of the Invention By manufacturing the present invention using the above method, the following effects were obtained.

(1) Compared to forming a thick N-layer with a low concentration using only the conventional impurity diffusion method, in the present invention, most of the N-type layer is formed by epitaxial growth, so the heat treatment time is reduced. will be significantly shortened.

(2) Compared to the case where a P base layer and a P emitter layer are formed by diffusing P type impurities after forming an N layer using Cyrisk etc., as shown in FIG. Since this is shifted from the junction between the N− layer and the N layer, hot spots do not occur at crystal defects that occur during epitaxial growth.

(3) Compared to the case where the N layer is formed only by epitaxial growth, the concentration gradient on the N layer side near the junction of the N- layer and the N layer becomes gentler as shown in Figure 2, so it is possible to form a silisk structure with a bevel. When processed, the surface electric field is not concentrated, and a breakdown voltage characteristic that is almost the same as the theoretical breakdown voltage of the main junction can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are structural explanatory diagrams for forming an N-type epitaxial growth layer according to the present invention, FIG. 2 is an explanatory diagram of impurity concentration distribution in the N base portion of the present invention, and FIG. The impurity concentration distribution diagram of the N base part of the invention, FIG.
Figure 5 is an explanatory diagram of the structure of the present invention, Figure 6 is an explanatory diagram of the structure of a general thyristor, and Figure 7 is an impurity concentration distribution diagram of the structural part.
The figure is an explanatory diagram of the structure of a thyristor with high forward blocking voltage, Figure 8 is an explanatory diagram of the N layer forming method of Figure 7, Figure 9 is an explanatory diagram of crystal defects in a conventional thyristor, and Figure 1O is an explanatory diagram of the conventional thyristor. FIG. 3 is an impurity concentration distribution diagram of an N base portion. II...N type silicon substrate, 12.12'...N
type epitaxial growth layer. Figure 1 (a) (b) Figure 2 Impurity concentration (composition scale) A Concentration distribution immediately after epitaxial growth B -11F
Concentration distribution after diffusion including L Figure 3 Impurity 14 lines (cm') Figure 4 [Impurity concentration (cm-3) Figure 5 Figure 6 Figure 7 (a) (b) Impurity concentration (arbitrary scale)

Claims (1)

[Claims] (1) After forming an N-type epitaxial growth layer on one main surface of a silicon wafer by epitaxial growth, heat treatment is performed to redistribute the N-type layer to form a thick, low-concentration N-type layer. A method for manufacturing semiconductor devices.