JPH01234831A - Thin film transistor with signal storage capacitor - Google Patents

Abstract

PURPOSE:To prevent a drain and a source electrode from being broken and to improve throughput by forming two insulating layers of a gate insulating film and a signal charge storage capacitor. CONSTITUTION:Two layers of an SOG film 26 and an insulating film 27 are arranged between a gate electrode 23 and a semiconductor film 29 and the source electrode 31 and drain electrode 32 are arranged on the semiconductor film 29 to form the thin film transistor (TFT) 20. Further, an SOG film 26 and an insulating film 27 are arranged between two electrode ITO 25 and trans parent conductive film 30 to form an image signal storage capacitor. Consequent ly, the throughput is improved and a drain line is never broken at the intersec tion of the TFT 20 of a drain line and the gate line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin film transistor with a signal charge storage capacitor used as a switch element of an active matrix panel.

[Prior art and its problems]

BACKGROUND ART Conventionally, TPT active matrix panels that control screen display using an active matrix method using thin film transistors (hereinafter referred to as TPT) as switch elements have been used in liquid crystal televisions, information terminal displays, and the like.

By the way, in order to improve the image quality of a liquid crystal television or display using this TPT active matrix panel, it is conceivable to improve the aperture ratio of the pixels used in the above panel. However, to achieve this, the above-mentioned panel space is limited and there is a limit to improving the pixel aperture ratio, so the width of each signal line must be narrowed and the TP
It is necessary to miniaturize T. - A partial plan view of a conventional TPT active matrix panel is shown in FIG.

As shown in the figure, there is a gate line 1 parallel to the scanning direction of the screen on the glass substrate 2;
A drain line 12 is formed perpendicularly to the gate electrode 1, and a part of the gate line 11 is formed to protrude in a convex shape at the intersection of the gate line 11 and the drain line 12 formed perpendicularly to each other. It is 5. A semiconductor film 7 is formed above the gate electrode 5 via a gate insulating film, and a portion of the drain line 12 formed above the semiconductor film 7 becomes the drain electrode 9.

Further, a source electrode 8 is formed on the semiconductor film 7 above the gate electrode 5 and electrically connected to the end of the pixel electrode 10 .

Next, FIG. 3 shows a sectional view taken along line AA' in FIG. 4. In the figure, on a transparent glass substrate 2 is an ITO which is one electrode of the signal charge M product capacitor.
(Indium-Tin-Oxide) 3 is patterned. Furthermore, a separation layer 4 made of silicon dioxide (SiO2) is formed on the entire surface of the glass substrate 2, covering the ITO3 as well. A gate electrode 5 is formed on the portion F4JEf'r, and covers the entire surface of the separation layer 4 and gate electrode 5 to cover silicon nitride (silicon nitride).
An insulating layer 6 made of (SiN) is formed, and a semiconductor film 7 made of amorphous silicon is formed above the gate electrode 5.
is formed. Further, on both sides of this semiconductor film 7, a source electrode 8 and a drain electrode 9 are formed facing each other and spaced apart by a predetermined ratio of 8u. Further, a transparent conductive film 10 is formed on the insulating film 6 at a position facing the ITO 3 and connected to the source electrode 8, which also serves as a pixel electrode and the other electrode of the signal charge N product capacitor. , I
A signal charge storage capacitor is constructed by sandwiching an insulating film 6 and a separation layer 4 (SiO2) between two electrodes, rO2 and a transparent conductive film 10.

Next, FIG. 5 shows a sectional view taken along line BB' in FIG. 4.

As shown in the figure, the drain line is formed by covering the level difference caused by the multilayer structure consisting of the D1-line, the gate insulating film 6a, and the semiconductor film 7. Generally, the thickness of the gate electrode 5 is 1000 Å or less, but in order to improve the aperture ratio of the pixel, it is necessary to miniaturize the gate line, and it is also necessary to reduce the wiring width of the gate electrode 5 and the gate line. be. However, when the wiring width of the gate line is reduced, the wiring resistance value increases. In order to suppress this, the thickness of the gate line must be increased.

However, if the gate electrode 5 and the gate line are made thicker, the difference in level of the drain line becomes larger at the point where the gate line intersects with the gate line, increasing the probability that the drain line will be disconnected, resulting in a lower yield.

Further, since the gate insulating film 6a is formed to cover the gate electrode 5, 5iN (silicon nitride) is generally used. However, when SiN is deposited directly on IrO2, which is one electrode of the signal charge storage capacitor, SiN
This results in abnormal growth, leading to poor insulation and peeling. Therefore, when using SiN for the gate insulating film 6a and the insulating film 6 in the conventional TFTl, as shown in FIG. After forming the isolation layer 4, IrO is deposited as the insulating film 6 by depositing SiN.
2 and SiN, which is the insulating film 6, were prevented from coming into direct contact with each other. However, since SiO2, which is the separation layer 4, has poor step coverage, the edge portion 13 of IrO2 shown in FIG. As mentioned above (SiN causes abnormal growth and Si
There was a problem with N peeling off.

As described above, the conventional TPT not only requires a process to form the isolation layer 4, but also has the problem that peeling of the isolation layer 4 causes abnormal growth of SiN, which is the insulating film 6.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a thin film transistor having a signal storage capacitor that prevents disconnection of the drain and source electrodes of T and FT and has a high throughput.

[Key points of the invention]

In order to achieve the above object, the present invention is characterized in that the gate insulating film and the signal charge storage capacitor have two insulating layers.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1(1) is a cross-sectional view of a TFT 20 having a signal charge storage capacitor according to an embodiment of the present invention. Same figure (
1), a gate electrode 23 made of Cr, Hel, Cu, Ti, W, etc. is formed on a transparent glass substrate 21, and an IT
O25 is formed. Furthermore, 5OGflJ26 is formed covering the gate electrode 23 and ITO25. An insulating film 27 made of SiO2 is formed on the SOG film 26, and a semiconductor film 29 made of amorphous silicon is formed on the insulating film 27 above and in the vicinity of the gate electrode 23. Further, a transparent conductive film 30 is formed on the same (insulating film 27) and covers a part of the transparent conductive film 30 and a part of the semiconductor film 29, connected to one end of the semiconductor film 29. and source electrode 3
A drain electrode 32 is formed on one side of the semiconductor film 29 facing the source electrode 31 and spaced apart from the source electrode 31 by a predetermined distance.

In this way, two layers, the SOG film 26 and the insulating film 27, which are insulating films, are provided between the gate electrode 23 and the semiconductor film 29, and the source electrode 31 and the drain electrode 32 are provided on the semiconductor film 29.
A TPT is formed by disposing an insulator S between the two electrodes ITO 25 and the transparent conductive film 30.
An image signal storage capacitor is formed by arranging the OG film 26 and the insulating film 27. The SOC film 26 covering the gate electrode 23 and the ITO 25 is first formed using a spin code method.
After applying the coating so that it is thin on the top and thick on the other glass substrate 21, it is baked in two stages (first at 100°C, then at 40°C).
It is formed by baking the silanol at a temperature of 0° C. to form a SiO2 film. The SOG film coated by the spin code method has excellent step coverage and can make the step difference caused by the gate electrode 23 and ITO 25 extremely flat. Insulation 1* is applied to the surface planarized by the SOG film 26 by ECR plasma CVD.
27 is deposited. ECR plasma CVD
SiO2 formed by this method has better electrical properties than SiN.

In addition, the application of the SOG film 26 by the spin code method and the E
Deposition of 5i02 (insulating film 27) by CR plasma CVD both has a higher throughput than deposition of SiN by plasma CVD, and therefore higher productivity than conventional TPT. Furthermore, no matter how much the thickness of the gate electrode 23 increases, the level difference between the insulating film 27, the semiconductor film 29, and the drain line (not shown) formed in a later process will be small because planarization is performed by the SOG film 26. Therefore, there is almost no possibility that the drain line will be disconnected or that the drain line and the gate line will be short-circuited at the intersection of the drain line with the TFT 20 and the gate line (not shown), unlike in the prior art.

Next, a method for manufacturing a TPT active matrix panel using the above-mentioned TFT 20 as a switch element will be described with reference to FIGS.

First, as shown in FIG. 1(a), chromium (Cr) and aluminum (A) are placed on a transparent glass substrate 21 whose surface has been cleaned.
l), copper (Cu), titanium (Ti), tungsten (
After forming a metal film 22 made of W) or the like to a thickness of approximately 3000 mm by sputtering or vapor deposition, a gate electrode 23 is formed by photolithography as shown in FIG.
Buttering.

Furthermore, as shown in FIG. 1(C), an ITO film 24 is formed on the gate electrode 23 and the glass substrate 21 to a thickness of approximately 1,000 yen by sputtering, and then a photo film 24 is formed as shown in FIG. 1(d). The ITO 25, which will become one electrode of the signal charge storage capacitor, is patterned by lithography. Next, as shown in Fig. 1 (21), the So
A G film 26 is coated on the glass substrate 21 to a thickness of about 3000 nm, covering the gate electrode 23 and the ITO 25. In this coating, the tops of the gate electrode 23 and the ITO 25 are coated thinner than the tops of the glass substrate 21 to reduce the level difference and flatten the surface.

Next, as shown in FIG. 1(f), 6Si was deposited on the two SOG films.
Insulating film 27 made of O2 and amorphous silicon 28
are deposited by ECR plasma CVD and plasma CVD, respectively, both to a thickness of approximately 1000 nm.

Then, as shown in FIG. 1 (gl), the amorphous silicon 28 is etched by photolithography to form a semiconductor film 29.Furthermore, the insulating film 27 and the semiconductor film 29 are covered with ITO by sputtering, for example. After being deposited to a thickness of 1,000 yen, photolithography is performed as shown in FIG.
Pattern 0. Finally, the insulating film 25 and the semiconductor film 29 are formed by sputtering or vapor deposition.
After depositing the transparent conductive film 30 to a thickness of, for example, about 1,000 layers, a source electrode 31 and a drain electrode 32 are formed by photolithography as shown in FIG. 1(1).

FIG. 2 shows a cross-sectional view taken parallel to the drain line when the TFT 20 formed as described above is used as a switch element of an active matrix panel. As shown in the figure, the gate electrode 2 is miniaturized and has an increased thickness.
The difference in level caused by 3 is 5OG1j! Since the drain line 33 has been flattened and relaxed by 26, there is almost no possibility that the drain line 33 will be disconnected. Furthermore, since the SOG film 26 has good stent coverage, short circuits between the gate line and the drain line 33 are unlikely to occur.

In this example, since planarization is performed by the 5OGli 26, SiO2 deposited by the ECR plasma CVD method, which has poor stamp coverage but good electrical properties, can be used for the insulating film 27 in contact with the semiconductor film 29. . Therefore, the electrical characteristics of TFT20 are different from those of conventional TPT.
improved.

In addition, in this embodiment, the SOG film 26 is made thicker so that the ECRSi
Since the insulating film 27 made of O2 is made thinner,! ffi l
! The throughput is higher than conventional TPT using SiN for the film. Furthermore, the gate insulating film is made of SOG film 24 and SiO2.
Since the insulating film 27 has a two-layer structure of different types of films, gate dielectric breakdown due to pinholes can be prevented.

〔Effect of the invention〕

As explained above, according to the present invention, the gate insulating film and the insulating layer of the signal charge M product capacitor are made of two layers, so even if the thickness of the gate electrode and gate line increases due to miniaturization, the spin code method can be used. By applying the SOG film, it is possible to flatten the step caused by the gate electrode and the gate line, and even if miniaturization is performed, the drain line will not be disconnected. Furthermore, since SiO2 deposited by ECR's plasma CVD method, which has high electrical properties, can be used as an insulating film in contact with the semiconductor layer, the electrical properties of the TPT are improved. Furthermore, since the gate insulating film is formed of two different layers, the gate has high insulation properties. In addition, the coating of SOG film by spin code method and the deposition of SiO2 by ECR plasma CVD method are different from those of SiN film by plasma CVD method.
The throughput is higher than the deposition of
Cost reduction can be achieved. Therefore, if the TPT of the present invention is used as a switch element, it is possible to miniaturize a TPT active matrix panel with high yield and at low cost.

[Brief explanation of the drawing]

FIG. 1 (al~(1)) shows the transparent conductive film and IT of the present invention.
A block diagram of TPT including a part of O and a manufacturing process diagram of a TPT active matrix panel using the TPT as a sui-nochi element.
A cross-sectional view taken parallel to the drain line near the FT, FIG. 3 is a cross-sectional configuration diagram of a conventional TPT, and FIG. 4 is a partial plan view of a TPT active matrix panel using the conventional TPT as a switch element. FIG. 5 is a cross-sectional view of the conventional TPT active matrix panel taken parallel to the drain line. 21... Transparent substrate, 23... Gate electrode, 26- .-3OC;]]*, 27... Insulating film, 29... Semiconductor film, 30... Transparent conductive film, 31... Source electrode, 32...Drain electrode. Patent applicant Casio Computer Co., Ltd. Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] A gate electrode formed on an insulating substrate, ITO formed on the same plane as the gate electrode, a first insulating layer formed to cover these gate electrodes and ITO, and this first insulating layer. a second insulating layer formed on the second insulating layer, a semiconductor layer formed on the second insulating layer on the gate electrode, a transparent conductive film electrically connected to this semiconductor layer, and a second insulating layer formed on the second insulating layer on the gate electrode; In a thin film transistor having a signal storage capacitor consisting of a drain electrode and a source electrode formed on a layer, the first insulating layer and the second insulating layer are insulating layers made of an SOG film and SiO_2, respectively. A thin film transistor with a signal storage capacitor.