JPH01232824A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce spike-like noise without decreasing an output current by providing plural transistors(TRs) connected in parallel to be used as TRs for output buffers, and controlling their operation or inoperation in a different timing. CONSTITUTION:Drain electrodes of TRs, TR1-TR4 are connected in common to form an output terminal 20 of a semiconductor integrated circuit device 1. Source electrodes of the TR1, TR3 are connected in common to be connected to a power line Vc, and the source electrodes of the TRs TR2, TR4 are connected in common, then connected to a TRs ground line G. The TR1, TR2 and the TRs TR3, TR4 are sequentially turned on or off in a deviated timing by the input of a data signal.

Description

[Detailed Description of the Invention] The five miles above the imperial palace! The present invention relates to a semiconductor integrated circuit device, and particularly to the structure and operation of an output buffer transistor.

When a distorted semiconductor integrated circuit device is mounted in a system, the input capacitance of the connected device and the stray capacitance present in the mounting board are coupled to the output terminal. In addition, inductance components due to the above-mentioned connected devices and mounting substrates are also coupled to the power supply terminal and the ground terminal.

FIG. 4 shows an equivalent circuit of the output buffer portion including the above-mentioned stray capacitance and parasitic inductance.

In the figure, (C1,) is the stray capacitance (hereinafter referred to as "load capacitance"), and (L, ) and (L,) are parasitic inductances connected to the power supply terminal and the ground terminal, respectively. Also, (TR5) and (TR,) are respectively P-type M
They are an O3I-transistor and an N-type MOS transistor, and their respective gate electrodes and drain electrodes are commonly connected to form an output buffer circuit. (Vcc)
is the system power supply, and (GND) represents the system ground. (Vca) and (C;a) represent a power supply line and a ground line inside the semiconductor integrated circuit device, respectively.

Note that (IVI) is an inverter circuit that inverts the data signal (Do) and applies it to the gates of the transistors (TR,) and (TR&).

In the above circuit, when the data signal (DO) becomes 'H' level, the signal is inverted by the inverter circuit (IVI), and the gates of the transistors (TRs) and (TR, ) are inverted. becomes “L” level, the transistor (TR8
) is "on" and (TRY) is "off", and the load capacitance (C1,) is charged by the power supply current supplied via the parasitic inductance (shi) and the transistor (TR,).

At this time, a spike voltage is generated across the parasitic inductance due to the charging current to the load capacitor (C1,), and spike noise is generated in the power supply line (Vca) inside the semiconductor integrated circuit.

Furthermore, when the signal (DO) reaches the "L" level, the signal is inverted by the inverter circuit (IV,) and the transistor (TR5
) and (TRY) become "H" level, the transistor (TRs) becomes "off" and the transistor (TR,) becomes "on", and the charge accumulated in the load capacitance (C, ) is transferred to the transistor. (TR,) and the ground side parasitic inductance (L□). At this time as well, a spike voltage is generated across the parasitic inductance (Lis) due to the discharge current of the load capacitor (C+a), and spike noise is generated in the ground line (Ga) inside the semiconductor integrated circuit.

The signal waveform in this state is shown in FIG.

In this way, the low frequency spike noise (N) generated on the power supply line (Vca) or ground line (Ga) in the semiconductor integrated circuit device due to switching of the output buffer circuit is
Increase the channel resistance by reducing the channel width (gate width of the transistor) of the output buffer transistor or increasing the channel length to reduce the current flowing through the output buffer transistors (TR3) and (TR,). It is possible by

However, if this is done, another problem arises, such as insufficient driving ability when the load device is an element driven by current, such as an LED or a bipolar transistor.

In addition, since the time required to charge and discharge the load capacitance (C0) is long, the operating speed of the semiconductor integrated circuit device becomes slow, making it impossible to increase the speed.

The present invention has been made in view of these points, and it is an object of the present invention to provide a novel semiconductor integrated circuit device that is devised to reduce spike noise without reducing output current.

In order to achieve the above object, the present invention provides a semiconductor integrated circuit device having an output buffer transistor whose one end is connected to a power supply line or a ground line. A plurality of connected transistors are provided, and means for controlling activation or inactivation of the plurality of transistors at different timings is provided.

Effect: According to such a configuration, when the output buffer transistor is turned on, for example, a plurality of transistors are turned on one after another at different timings. Since there are a plurality of transistors, the conduction current shared by each transistor can be set small in advance.

Therefore, when an individual transistor turns on, the spike noise generated in the power line or ground line due to parasitic inductance is small, and the total output current that flows after all transistors connected in parallel have finished turning on is a predetermined amount. The current is sufficient to drive the load device. When all transistors connected in parallel are on and current is flowing through them, each transistor is turned off one after another at different timings, so one transistor is turned off. When this happens, the amount of change in the output current is small, and therefore the spike-like noise generated in the power supply line or ground line due to parasitic inductance is also small.

Back - Shiichi± An embodiment according to the present invention is shown in FIG.

In the figure, (TRI) and (TRY) are divided P-type MO3I-transistors, and (TR,) and (
TR,) is a divided N-type MOS) transistor. The gate electrodes of the transistors (T Rl) and (T R2) are connected in common, and an inverted first data signal (T) is input.

Further, an inverted second data signal (f55.) is applied to the gate electrode of the transistor (TR,), and an inverted third data signal (f55.) is applied to the gate electrode of the transistor (TR,). applied.

The drain electrodes of the transistors (TR+), (TRz), (TRz) and (TR4) are commonly connected to form an output terminal (20) of the semiconductor integrated circuit device (1).

The source electrodes of the transistors (TR,) and (TR,) are commonly connected to the power supply line (Vc) inside the semiconductor integrated circuit device.
), and also connected to transistors (TR2) and (TR
, ) are also commonly connected to a ground line (G) inside the semiconductor integrated circuit device.

(L+) and (L+) are parasitic inductances connected to the power supply line (Vc) and the ground line (G), respectively.

(V cc) and (GND) represent the power supply and ground of the system, respectively, and (C8) represents the sum of parasitic capacitances coupled to the output terminal (20) of the semiconductor integrated circuit device (1). . Hereinafter, this (C1) will be referred to as load capacity.

(9) shown in FIG. 2 is the timing for producing the respective gate signals (IIZ, ), (ff5.), (lfi,) corresponding to the input data signal (DO) that drives the buffer circuit in FIG. This is a signal generation circuit, with inverters (2p) and (2q) connected as shown.
, (2r).

(2s), a NAND circuit (3), and a NOR circuit (4). The first gate signal (2p) is output from the first inverter (2p), and the second gate signal (2p) is output from the first inverter (2p). Third gate signal (I15j!t), (I15j5i)
The signals are output from the N D circuit (3) and the NOR circuit (4), respectively.

Each signal (no), (leap +), (D
I).

(15i5.) and (view 3) are shown in FIG. 3 together with the voltages of the power supply line (Vc) and ground line (G).

Next, the circuit operations of FIGS. 1 and 2 will be explained in detail with reference to FIG. 3.

When the data signal (Do) transitions from “L” to “H”, the inverted data signal (fY5) is generated via the inverter (2p).
transitions from “H” to “L”, the transistor (TR, ) turns on, and the transistor (TRY) turns off. At this point, the third gate signal (leap, ) also changes from “H” to “L”.
” and the transistor (TR4) also turns off.

However, the second gate signal (Ii5.) applied to the transistor (TRs) remains at "H" level, and the transistor (TR,) maintains the off state.

Furthermore, inverter rows (2p), (2q), (2r
), the data signal (Dl) delayed by (2s)
is time 1. Later, the signal reaches the NAND circuit (3), at which point the first gate signal (2) transitions from "H" to "L" and the transistor (TRs) is turned on.

Therefore, there is a time difference between the charging current to the load capacitance (C,) caused by the transistor (TR,) and that caused by the transistor (TR3), and the parasitic inductance (L
The fluctuation of the internal power supply line (Vc) due to 1) has a shape having two dip values (5a) and (5b) as shown in FIG.

In this case, the first gate signal (bacteria) changes from "H" to "
At the time of transition to L”, transistors (TR1) and (T
(Vc
) [(6) in FIG. 3], the voltage fluctuation width can be suppressed to be smaller than the fluctuation of (6) in FIG.

Next, when the data signal (DO) transitions from "H" to "L", the first gate signal (2), which is the inverted data signal, changes from "L" to "H" through the inverter (2p).
”, the transistor (TR2) is turned on, while the transistor (TR, ) is turned off.At this point, the second gate signal (transistor) also transitions from “H” to “L”, and the transistor (TR2) is turned off. TR3) is also turned off.

However, the third gate signal (DOl) applied to the transistor (TR,) remains at "H" level, and the transistor (TRY) maintains the off state.

Furthermore, inverter rows (2p), (2q), (2r
), the data signal (DI) delayed by (2s)
It's time t! Later, it reaches the NOR circuit (4), at which point the third gate signal (bacteria) transitions from "L" to "H",
The transistor (TR,) is turned on.

Therefore, a time difference occurs between the discharge current from the load capacitor (C1) due to the transistor (TR, ) and that due to the transistor (TR,), and the parasitic inductance (
The fluctuation of the internal ground line (G) due to L8) has a shape having two peak values (7a) and (7b) as shown in FIG. In this case as well, the first gate signal αtun) is “
At the time of transition from “L” to “H”, the transistor ('rR
z) and transistor (TR1) are turned on at the same time [(8 in Fig. 3)
)], it is possible to suppress the voltage fluctuation range to a smaller value.

In this embodiment, the load capacitance (C
2) is connected [Thus, for example, after the load capacitance (C1) is charged, the transistor (TR,)
, (TR3)], but there is an LED driven by current at the output terminal (20).
or if a bipolar transistor is connected, for example a transistor (TR,).

While (TR,) is on, current flows through these transistors, so in this state the transistor (
Even when R+) and (T Ri) are turned off, spike-like noise occurs on the power supply line (Vc) due to parasitic inductance. Therefore, when a load driven by the power supply is connected, when the transistor is deactivated, By shifting the cutoff timing of each transistor connected in parallel, spike-like noise can be reduced.

In the above embodiment, a plurality of transistors are connected to the power supply line (Vc) and a plurality of transistors are connected to the ground line (G), but one transistor is connected to one of the transistors as in the conventional example. This is because it is not necessarily necessary to provide a plurality of transistors related to the parasitic inductance, which can be ignored with respect to spike noise, to take the above-mentioned measures.

It goes without saying that the present invention can also be applied to an output buffer circuit that only has a transistor on either the power line side or the ground line side, regardless of the magnitude of the parasitic inductance.

According to the present invention, it is possible to reduce spike-like noise superimposed on the power supply line and the ground line inside the semiconductor integrated circuit device, and therefore, the output has high noise resistance and high driving ability. A semiconductor integrated circuit device having a buffer circuit can be realized.

Furthermore, system design using this semiconductor integrated circuit device becomes easier.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
Figure 3 showing a circuit that generates a signal that drives the circuit shown in Figure 3.
The figure is a diagram for explaining the timing in the circuits of FIGS. 1 and 2. FIG. 4 is a circuit diagram showing a conventional example, and FIG. 5 is a timing diagram thereof. (9) --- Timing signal generation circuit. (20) - Output terminal, (c+)' - Load capacitance. (TRI), (TRI)--P channel type MO3
) Langista. (TRz), (TR4)---N-channel type MO
3) Ranjistor. (L, ), (Lri...parasitic inductance. (Vc)--power line, CG)--ground line.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device having an output buffer transistor whose one end is connected to a power supply line or a ground line, a plurality of transistors connected in parallel to each other as the output buffer transistors are provided, and the plurality of transistors are connected to each other in parallel. 1. A semiconductor integrated circuit device comprising means for controlling activation or deactivation at different timings.