JPH01232764A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make possible the high-speed operation of a semiconductor device by a method wherein a semiconductor layer is buried in the lower part of a hole (a trench groove or the like) formed on the side of one main surface of a semiconductor substrate and a high-temperature treatment is eliminated in such a way that the lower electrode of a vertical type semiconductor element on the side of the hole is led out through a diffused region diffused from this semiconductor layer. CONSTITUTION:An N-type well diffused region 22 is formed on the side of one main surface of a P-type Si substrate 21, an N<+> poly Si layer 30 containing an N-type impurity in a high concentration is buried in the lower part of a trench groove 20 formed in this well region and an N<+> collector region 27 is formed integrally with the layer 30 on the side of the layer 30 by the self-diffusion of an impurity from the layer 30. An N+ poly Si collector electrode 38 insulated from its periphery with an Si oxide film 35 is adhered at a position right over the layer 30. Accordingly, a high-temperature thermal process is not needed for the formation of the region 27 not it is needed to grow an epitaxial layer. Moreover, the parasitic capacity of the region 27 is reduced and as the electrode 38 reaches up to the same depth as that of the region 27, the parasitic resistance of the region 27 is also small. Thereby, the high-speed operation of a semiconductor device becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device, particularly a vertical bipolar transistor.

2. Prior Art A conventional vertical bipolar transistor has a structure as shown in FIG. 8, for example. That is, P- type is formed in the N- type epitaxial layer 2 formed on the P-type silicon substrate 1.
A type base region 3 is formed by diffusion 1, and an N+ type emitter region 4 and a PF type base electrode extraction region 5 are respectively diffused and formed in this base region. An N+ type collector region 7 is formed by diffusion to a depth that reaches the ten-shaped buried layer 6.

Therefore, in this NPN type vertical bipolar transistor, the collector region 7 and the base region 3 are connected via the buried layer 6. In the figure, 8 is an emitter electrode, 9 is a base electrode, 10 is a collector electrode, 11 is a field oxide film, 12 is a P- type well diffusion region, and 13 is a P+ type channel stopper region.

According to the structure shown in FIG. 8, it is connected to the collector region 7 through the buried layer 6, but the following drawbacks arise due to the formation of such a buried layer.

(1) High temperature diffusion treatment and growth of the epitaxial layer 2 are required when forming the buried layer.

(2) Since the buried portion N6 exists over a considerable area, the parasitic capacitance and parasitic resistance become large, and the operating speed decreases.

(3) In addition to this, lateral impurity diffusion may occur in the buried layer 6 during the subsequent heat treatment process (diffusion of impurities into the collector region 7, etc.), which increases the area of the element region.
Its miniaturization is difficult.

(4) Due to the heat during impurity diffusion in the collector region 7,
Impurity diffusion in the P-type well cap 12 occurs and the impurity concentration in that region decreases, and this spreads the depletion layer and facilitates conduction between adjacent device regions. This also hinders the miniaturization of elements.

C.5 Purpose of the Invention An object of the present invention is to provide a semiconductor device that does not require high-temperature processing, can operate at high speed, and is suitable for miniaturization.

28 Structure of the Invention That is, in the present invention, a semiconductor layer with a high impurity concentration is embedded in the lower part of a hole formed at a predetermined depth on one main surface side of a semiconductor substrate, and a vertical type is formed at a side position of the hole. A semiconductor device comprising a semiconductor element, wherein a lower electrode of the semiconductor element is taken out from the hole to a position directly above the semiconductor layer via an impurity diffusion region formed by impurity diffusion from the semiconductor layer and the semiconductor layer. It is related to the device.

E, Example The present invention will be explained in detail below.

1 to 3 show a first embodiment of the present invention.

As shown in FIGS. 1 and 2, the vertical bipolar transistor according to this example has an N-type well diffusion region 22 formed at a predetermined depth on one main surface side of a P-type silicon substrate 21, and inside this well region. The structure is such that the collector electrode 38 is taken out using the trench groove 20 formed to a predetermined depth.

That is, an N+ type polysilicon layer 30 containing a high concentration of N type impurities is embedded in the bottom side (lower part) of the trench groove 20.
By self-diffusion of impurities from this polysilicon layer (during a low-temperature thermal process described later), an N++ collector region 2 is formed on the side of the polysilicon layer.
7 is diffusely formed in the body. For this self-diffusion, a silicon oxide film 31 is formed on the side surface of the polysilicon layer 30.
was removed by Oberer and 7chi, which will be described later. Immediately below the polysilicon layer 30, a non-doped polysilicon layer 32 containing no impurities is formed in advance during deposition.
is buried on the bottom surface of trench 2o via silicon oxide film 31.

The polysilicon layer 30 forms a part of the collector region, and a collector electrode 38 of N medium size polysilicon insulated from the surroundings by a silicon oxide film 33 is deposited directly above it. Further, at a side position of the trench groove 20, an N++ emitter region 24 and a P+ type contact region 25 are formed in a P- type base region 23 formed by impurity diffusion in the well region 22.
- Base region 23 - Collector region 27 constitute an NPN type vertical bipolar transistor.

In addition, 28 in the figure is an emitter electrode, 29 is a base electrode,
41 is a field oxide film.

As described above, according to the first embodiment of the present invention, the collector region 27 or the collector electrode 38 is not connected via the Nt-type buried layer as in the conventional case, but is connected to the bottom side of the trench groove 20. Collector electrode 38 is formed through N+ type region 27 and polysilicon layer 30 due to self-diffusion of
Since the collector electrode is provided directly above the polysilicon layer 30 from the groove 20, the following remarkable effects can be obtained.

(1) Since the diffusion region 27 which becomes the collector region is formed by self-diffusion from polysilicon, a high-temperature thermal process is not required, and since it is not a so-called buried type, there is no need to grow an epitaxial layer. This is advantageous as it allows the use of large diameter wafers.

(2) Since this diffusion region 27 can be selectively formed in a narrow area, its parasitic capacitance is reduced, and the diffusion region 2
Since the polysilicon electrode 38 reaches the same depth as 7, the parasitic resistance is also small (this makes high-speed operation possible).

(In case of 31, L, the collector part surrounding the diffusion region 27 utilizes the trench groove 20 formed next to the vertical bipolar transistor structure, so the area occupied by this transistor element itself is considerably reduced. This is very advantageous for miniaturization and high integration.

(4) Also, since the above self-diffusion is performed in a low-temperature process described below, it does not cause any negative effects on other semiconductor regions.
Stabilizing device characteristics and further promoting miniaturization.

Next, a method for manufacturing a transistor according to this example will be explained with reference to FIG.

First, as shown in FIG. 3A, an N-type well region 22 is diffused into a P-type silicon substrate 21 by a known technique, and P-type impurity (for example, boron) ions 42 are diffused into a device region surrounded by a field oxide film 41. is implanted to form a P- type semiconductor region 23.

Next, as shown in FIG. 3B, a trench groove 20 is selectively formed in the well region 22 by a known dry etching technique, and then a silicon oxide film 31 is grown on the entire surface including the groove 20 by a thermal oxidation method.

Next, non-doped polysilicon is coated on the entire surface including the groove 20 using CVD (Chemical Vapor
After the polysilicon is deposited on the entire surface by dry etching, the polysilicon 32 is left only on the bottom surface of 'a20' as shown in FIG. 3C.

Next, as shown in FIG. 3D, the oxide film 31 is over-etched. Next, doped polysilicon (containing a high concentration of N-type impurities, such as As) is deposited on the entire surface including the over-notch portion 43 by CVD, and is etched back to form a highly concentrated polysilicon layer 30 as shown in FIG. 3E. Leave on the bottom of 120.

Next, as shown in Fig. 3F, Si is deposited on the entire surface by CVD.
S is deposited only in the groove 20 by etching.
The in2 layer 33 is left. After this, a thermal oxidation process (not shown) is performed on the surface, and the heat at this time causes the N-type impurity to self-diffuse laterally from the polysilicon layer 30 on the lower sidewall of the groove 20, resulting in N+ type diffusion as shown in the figure. Region 27 is selectively formed.

Next, as shown in Figure 3G, after thermal oxidation of the surface, 5inz
The layer 33 is selectively etched so that only the walls of the groove 20 are etched.
in, leaving the membrane 33. Then, open the emitter window 44 (however, you can do this later).

Next, as shown in FIG. 3H, the doped polysilicon (containing a high concentration of N-type impurities, such as As) deposited on the entire surface by CVD is patterned by photoetching to form grooves 20.
The polysilicon is left only in the interior and window 44 as 38 (collector electrode) and 28 (emitter electrode). On this occasion,
N type impurities are diffused from the window 44 to form an N + type emitter region 24 in the P − type region 23 .

Next, although not shown, a window for the base electrode is opened, polysilicon containing a high concentration of P-type impurities (for example, boron) is deposited by CVD, and then buttered to form the polysilicon base electrode 29 and contact? il area 25 (
(see Figure 1).

After this, insulating film coating, multilayer wiring, etc. are applied by known methods to complete the device.

As is clear from the manufacturing method described above, the vertical bipolar transistor according to this example can be manufactured by selectively providing the collector head in a narrow area without using high-temperature heat treatment. Especially for this type of transistor,
Extracting the collector electrode using trench grooves and self-diffusion is an innovative means.

4 and 5 show an embodiment that is suitable for further miniaturization and realizes a combination of bipolar technology and MO3 technology (bi-MO3).

In this example, as shown in FIG.
Each P-type well region 50,51, N-type well region 2
2.52 are formed, and these wells are separated by trench isolation method and divided into respective element regions. That is, deep trench grooves 60 are formed in the substrate 21, and each groove is filled with polysilicon 54 via a silicon oxide film 53. The N-type well region 22 is provided with an NPN box-shaped bipolar transistor having the same configuration as described in FIG. In addition, I)-type well region 50
In this case, the N++ diffusion region 6.1.62 is connected to the source or drain.
An N-channel Mo5t transistor is provided in the in-range region. This and P channel Mo that constitutes CMOS
The 5t transistor is provided in the N-'' type well region 52, and 63.64 is a P+ type source or drain region. 65.66 is a source electrode!-167, 68 is a train electrode, and 69.70 is a goo. [It is an electrode.

The device shown in FIG. 4 has the same advantages as the device chair shown in FIG.
Since 0 is used, it is possible to increase the miniaturization of the IC between layers, which is very advantageous in providing a CMO3?W composite element as shown in the figure.

Next, the manufacturing method will be described. First, as shown in FIG. 5A, well regions 22, 50, 51, and 52 are formed by performing diffusion on one main surface of the silicon substrate 21 by a known method. Then, the space between each well region is processed by dry etching to form each trench groove 60, and a silicon oxide film 53 is further grown.

Next, after depositing polysilicon 54 on the entire surface by CVD, polysilicon 54 is left in each groove by etch hacking as shown in FIG. 5B. Next, the oxide film on the surface of the N-type well region 22 is removed by etching, and then the P-type impurity 42 is etched away.
A P-type region 23 is formed by implanting.

Next, as shown in FIG. 5C, a trench groove 20 is formed by dry etching to penetrate the P-type region 23, and the surface is oxidized.

Next, as shown in FIG. 5D, the polysilicon 32 is processed to remain at the bottom of the trench groove 20, and then the oxide film 31 is over-etched as shown in FIG. 5E.

Next, as shown in FIG. 5F, N++ polysilicon 30 is deposited only in the groove 20 as in FIG. 3E.

Next, as in FIG. 5G, 5102 as in FIG. 3F.
A layer 33 is deposited by CVD and self-diffused from the polysilicon 30 to the trench sides to form an N-type collector region 27.

Next, as shown in Fig. 5H, the oxide film 33 on the surface is etched.
Notch and open windows at each location. However, it is preferable to remove the oxide film on the well region 50 by etching in a later step and reapply it to form a gate oxide film.

Then, as shown in FIG. 51, N++ polysilicon is deposited to form each electrode 38, 28, 65, 66. At this time, by simultaneous diffusion of N-type impurities, each N+ type region 4.61
．． 62 can be formed.

FIG. 6 shows another embodiment of the invention.

Here, compared to the example shown in FIG. 1, the collector region 27 and the collector electrode 38 are made common, and a plurality of emitter regions 24 and a plurality of base contact Bl regions 25 are formed, so that the N P
It has a structure in which N bipolar transistors are connected in parallel. Therefore, the current drive capability can be doubled, and in this case, the occupied area does not increase much.

FIG. 7 shows an example of a multi-emitter structure, in which the emitter region 24 (therefore, the emitter/electrode 28) is divided into a plurality of parts compared to FIG. This device can be further modified, for example by using TTLO.

For example, a similar semiconductor material may be used in place of the polysilicon 30 described above, and the method of forming it may also be changed.

Various dry etching methods can be used to form the trenches. Further, self-diffusion is possible even if the above-mentioned process (Fig. 3D) is not necessarily performed.

Further, the emitter/7 contact region and the base contact region do not have to be formed during the above-mentioned polysilicon deposition (as shown in FIG. 3H), but may be formed by ordinary ion implantation.

Further, these electrodes may also be formed of metal such as aluminum instead of polysilicon. Such changes in processes and materials are also possible in the example shown in FIG. 5 (FIG. 5I, etc.).

Note that the conductivity type of each semiconductor region described above may be reversed,
Of course, the shape, arrangement, etc. of each area can also be changed. Further, the present invention can be applied to devices or elements other than hyperpolar disks.

1. Functions and Effects of the Invention As described above, the present invention provides the following effects: Since the lower electrode of the vertical half-body element on the side of the hole is taken out, there is no need for the conventional high-temperature process, and there is no need for an evixial layer. Furthermore, since the diffusion region is selectively formed in a narrow region, the parasitic capacitance and parasitic resistance are small (and high-speed operation is possible).Moreover, the lower electrode can be taken out through the hole directly above it. Therefore, the area occupied by the element itself is reduced, making it suitable for miniaturization of devices.

[Brief explanation of the drawing]

1 to 7 show embodiments of the present invention, and FIG. 1 shows an NPN vertical bipolar E-type according to the first embodiment.
2 is a plan view of FIG. 1 (however, the field oxide film is omitted - the cross section taken along the line 1-1 in FIG. 2 is shown in FIG. 1), FIG. 3A, FIG. 3B , Figure 3C, Figure 3D, Figure 3E,
3F, 3G, and 3H are sectional views sequentially showing the main steps of the method for manufacturing the transistor shown in FIG. 1; FIG. 4 is a sectional view of a device according to another embodiment; FIG. 5A, and 5B. 5C, 5D, 5E, 5F, 5G, 511, and 51 are cross-sectional views sequentially showing the main steps of the method for manufacturing the device shown in FIG. 7 are sectional (perspective) views of the second side of the device according to still another embodiment. FIG. 8 is a cross-sectional view of a conventional NPN vertical bipolar transistor. In addition, in the symbols shown in the drawings, 20.60...Trench groove 21...Silicon substrate 22.50.51.52...Well region 23...Base region 24...Emitter Region 25...Base contact region 27.
...Emitter region 28 ...Emitter electrode 29 ...Base electrode 30 ...N÷ type polysilicon layer 31.33.
... Oxide film 32 ... Non-doped polysilicon layer 38
...Collector electrode. Agent Patent Attorney Aisaka Youngest Brother 1 Figure 2 Figure 27 (Fe> 3゜ Figure 3A Figure 3B Figure 3C Figure 3D Figure 3F jj Jl Figure 6 Figure 7

Claims (1)

[Claims] 1. A semiconductor layer with a high impurity concentration is embedded in the lower part of a hole formed to a predetermined depth on one main surface side of a semiconductor substrate, and a vertical semiconductor element is configured at a side position of the hole, A semiconductor device, wherein a lower electrode of the semiconductor element is taken out from the hole to a position directly above the hole through the semiconductor layer and an impurity diffusion region formed by impurity diffusion from the semiconductor layer.