JPH01232394A - Scan converter device - Google Patents

Abstract

PURPOSE:To execute high-speed interpolation computation with simple circuits without using a multiplier circuit by changing the amplitude set voltages of two D/A converters according to the weight coeffts. outputted from a decoder. CONSTITUTION:The video signal of a 1st horizontal frequency fHK is digitized and is stored in a video signal memory means 12. The p-th scanning line video signal A(p) and (p+1)th scanning line video signal A(p+1) obtd. by this memory means 12 are supplied to the D/A converters 18, 19. Control power supplies 1-K and K which control amplitudes according to the horizontal frequencies hHK and fH are then supplied from an amplitude control power supply generating means 27 to the D/A converters 18, 19 respectively. The outputs A(p) and A(p+1) of the converters 18, 10 are added by an adder means 20 in succession thereof and the video signal of the 2nd horizontal frequency fH is obtd. on the output side thereof.

Description

[Detailed Description of the Invention] [Industrial Application Field J] The present invention is used for viewing a video signal having a horizontal frequency of 2'/15kHz on a monitor having a horizontal deflection frequency of 63.35kllz, for example. The present invention relates to a scan converter device.

[Summary of the invention]

In the present invention, for example, a video signal with a horizontal frequency of 2'/15 kllz is converted into a video signal with a horizontal deflection frequency of 63.35 kllz, for example.
A scan converter device used for viewing on a monitor, comprising a video signal storage means for digitally converting and storing a first horizontal frequency video signal, and a second video signal storage means obtained from the video signal storage means. first and second digital-to-analog conversion circuits to which the scanning line video signal and the p+1th scanning line video signal are supplied, respectively; an amplitude-controlled power supply generating means for supplying a power supply whose amplitude is sequentially controlled in accordance with the first horizontal frequency and the second horizontal frequency of the output video signal, and the output signals of the first and second digital-to-analog conversion circuits; The video signal of the second horizontal frequency is obtained on the output side of the adding means, so that a smooth and natural output video signal can be captured with a simple configuration. This is what I did.

[Conventional technology]

Conventionally, for example, Broadcasting Technology 1986.2 PP 119-1
As disclosed in Japanese Patent No. 22, a scan converter device is known that obtains an output video signal with twice the horizontal frequency of an input video signal. In this device, in order to obtain an output video signal, the negative scanning line signal of the input signal of each field is
An interpolation circuit was used that simply sent out the output scan line repeatedly.

However, recently, there has been a demand for a scan converter device that allows a single monitor with a fixed horizontal scanning frequency to receive various human-powered video signals having various horizontal frequencies, and the Honda 1-Uto is specially designed for this purpose. Tosho 61-25059
In No. 2, we proposed a scan converter device for use in a monitor system as shown in Figure 4. In FIG. 4, +11 is a TV tuner, (2) is a high-density computer, and (3) is another computer, and the horizontal frequencies are f Hl = 15.75 kllZ, E 82 =
24 kHz and f H3 = 27.15 kHz. Further, the video signals from the high-density personal computer (2) and computer (3) are separated into R, G, and B components. The video ti signals from these devices are appropriately input to the scan converter device (4). Further, (9) is a monitor for video observation in which the horizontal frequency fH is fixed at 63.35 kHz.

Here, the scan converter device (4) is a human power processing board (5) that A/D converts the video signal in synchronization with the horizontal synchronization signal of the human video signal and converts the horizontal frequency to fH.
, a frame memo 6) that stores the A/D conversion value of the video signal for each frame of video, and a video signal for the output scanning line from the values compiled from this frame memo 6). An interpolation processing board (7) to generate the video signal, and an output processing port (8) to perform analog processing such as superimposing a synchronization signal on the generated video signal and output it to an external monitor (9).
) and more.

[Problem to be solved by the invention]

In Fig. 4, when converting a human video signal from the computer (3) to a video signal for the monitor (9), the ratio of the horizontal frequency fH3 of the computer (3) to the horizontal frequency (s) of the monitor (9) is f 81: f H=27.15kHz: 63.3
Since 5kHz = 3: '/, part of the scanning line of the human input image to the scan converter device (4) is shown in Figure 5A.
Assuming that, the scanning line of the corresponding output image will be as shown in FIG. 5B. That is, three human scanning lines (A-C
), seven output scanning lines (a-g) are required,
Thereafter, seven output scanning lines (a' to g') are required for three input scanning lines (A' to C').

In order to obtain a smooth and natural output image, when the output scanning signal is generated by a weighted average of adjacent input scanning signals, the phases of the input scanning line A and the output scanning line a are equal. Then, the output scanning line a may be the input scanning line A itself, which is expressed as a=A.

Then, the signal on the output scan line is transmitted over a distance of 1 as shown in FIG.
1 and 12, the weighted average of the manual scanning lines A and B is determined by the following formula.

11 +12 It +12 Similarly, c= (1/7) A+ (6/7) Bg= (37
1) c'+ (4/7) A'a'"'A'" These calculations are executed when reading data from the frame memory in synchronization with the output horizontal frequency fH, so the horizontal Assuming that the resolution in the scanning direction is 640, one calculation must be performed within 640 pixels, and when a multiplication circuit is used, a large-scale and expensive circuit that operates at high speed is required.

Moreover, instead of the scan converter W (41) shown in FIG. 4, which has a frame memory corresponding to all the input scanning line signals, a system having a frame memory corresponding to all the output scanning line signals is used. Even in this case, crystal speed multiplication is required when writing to frame memory,
After all, a large-scale and expensive circuit is required.

The present invention has been made in view of the above, and an object thereof is to provide a scan converter device that has a simple configuration and can perform smooth and natural interpolation.

(Means for Solving the Problems J) A scan converter device according to the present invention includes, for example, as shown in FIG. 1, a video signal storage unit (12) that digitally converts and stores a video signal of a first horizontal frequency fHK; The first and second digital analog signals are supplied with the ninth scanning line video signal A (p) and the p+1st scanning line video signal A (p+1) obtained from the video signal storage means (12), respectively. Conversion circuit (hereinafter referred to as D/A converter)
(1B) and (19) and this first and second D/A
Transducers (18) and (19) each have a first horizontal frequency f.
HK and the second horizontal frequency [8 of the output video signal.
The output signal A(p
) and A(p+1), and the video signal of the second horizontal frequency fo is obtained on the output side of the adding means (20).

[Effect]

According to the present invention, the D/^ converter (18) and (1
Since the amplitude setting voltage of 9) is changed according to the stopping coefficient K output from the decoder (24), the output analog signals of these D/A converters (18) and (19) are output scanned, respectively. The signal a (can be expressed as [r(q)A (p), f2(q)A (p+1)) using the functions E1 (q) and f2 (q) of line number q in (1). Therefore, these can be expressed as The signal of output scanning line a (q) obtained by adding is a (Q) = ft (Q) A (p) + fz (q) A
(P+1), and interpolation calculation is performed without using a multiplication circuit.

C Embodiment] Hereinafter, one embodiment of the scan converter device of the present invention will be described with reference to the drawings.

FIG. 1 shows the scan converter device of this embodiment.
10) is an input terminal, and the frequency f H of the human input video signal is
K horizontal synchronizing signal H5YI is supplied. This horizontal synchronizing signal H8Yt is input to the frequency conversion circuit (11) proposed by the applicant in Japanese Patent Application No. 61-250592, and the output side horizontal synchronizing signal HSY2 of frequency rH is
is converted to Here, the frequency f) IK and fH are expressed as rnK: [H=n: m (fH=mfHK/
n)...Since (1) is set so that it holds true, as shown in Figure 2, the scanning line of the output video signal is m pieces (FIG. 2B) are generated. Here, it is assumed that the input video signal is non-interlaced, but in the case of interlace, the combination of two fields of video before and after is equivalent to FIG. 2A.

Also, in Figure 1, (12), (13) and (
14) Each frame memory is a frame memory, and the input video signal is divided into R, G, and B components and written for one frame each by a write circuit (not shown) via a data bus (15). . In order to obtain the final output video signal, it is necessary to perform interpolation processing on each of these RlG and B components in parallel, but in this example, interpolation processing is performed on the component written in the frame memory (12). Let's do it.

Next, (16) and (17) respectively show launch circuits, in which the signal A (p) of the pth scanning line of the input video signal in the frame memory (12) is launched via the data bus (15). When launched into circuit (16), (p+1)
The signal "4A (p+1) of the th scanning line is the latch circuit (17
) is now available for lunch. Here, if the resolution in the horizontal scanning direction is 640 dots, the signal A (p) is 640 dots.
It is a collection of individual digital data. Then, the output signal A (p) of the launch circuit (16) is converted into analog by the D/A converter (18) and sent to one input of the adder circuit (20), and the output signal A (p+1) of the latch circuit (19). ) is D/
＾Converter (19) converts it into analog and adder circuit (20)
The addition circuit (20) generates a sum signal a(q). This signal a (Q)
becomes the signal of the q-th scanning line of the output image (g), and is outputted from the output terminal (22) to the subsequent processing circuit via the low-pass filter (L'F) <21).

In addition, in FIG. 1, (23) is a central processing unit (CP
U), and CPLJ (23) first connects the address bus (
24) outputs the address of A (p) in the input video signal, causes the latch circuit (16) to latch the signal A (p) using the control line (23a), and then outputs the address of A (p+1) to It operates to output the address and use the control line (23b) to cause the latch circuit 1m (17) to latch the signal A (p+1). C.P.L.J.
(23) uses the data bus (25), control bus (23c) and (23d) in the decoder (2).
6) Set the interpolation coefficient K. In this example, the decoder (26
) consists of RAM, and the decoder (26) is preloaded with a CPU.
(23), each scanning line a (q) of the output video signal
Interpolation coefficients Kq corresponding to are stored in order. Then, when generating an output video signal while performing interpolation, the stored interpolation coefficient Kq is sent from the decoder (26) in synchronization with the output side horizontal synchronizing signal Hsy2.
The signal is output to the 1/A converter (27). Therefore, C
The control lines (23c) and (23d) of the PLJ (23) are connected to the write terminal W and reset terminal RES of the decoder (26), respectively, and the output side horizontal synchronizing signal HGY2 is connected to the read terminal R of the decoder (26) manually. has been done.

And the amplitude setting terminal Vr of the two-phase IJ/A converter (27)
The unit voltage of the unit 1 source (28) is supplied to 8f'l, and the 2-phase D/A converter (27) supplies the analog voltage K to the amplitude setting terminal Vref2 of the 1]/8 converter (19). ,
Further, the analog voltage (1+K) is supplied to the amplitude setting terminal Vret1 of the D/A converter (18), respectively. Therefore, D/
The analog output of the A converter (18) is (1-K)A (p
), and the analog output of the D/A converter (19) is KA
(p+1).

Here, to explain how to determine the stopping coefficient, as shown in FIG. 2, n scanning lines of the human input video signal correspond to m scanning lines of the output video signal. Therefore, q between the pth and (p+1)th manual scanning signals A (p) and A(p+1)
If there is a th output scanning signal a(q), then Fig. 2A
Therefore, signal a (q) is equal to signal A (p) and ＼(p+
It is expressed as the weighted average of 1). In equation (2), by putting However, in this example, due to periodicity, the coefficient KQ of the q-th output scanning line and the coefficient K q+m of the (q+m)-th output scanning line are equal, and Kq=Kq+m holds true.

Next, when the values of n and m in Figure 2 are given, the weighting coefficient Kq for the interpolation calculation of the q-th output scanning line (line number q) is calculated in advance by C)'U (23) in Figure 1. The third step is to calculate the calculation and create a table in the decoder (26).
This will be explained with reference to the figure. First, in step (100), the CPU (23) connects the control line (23d
) to reset the decoder (24), the decoder (
24) is in a state where it is possible to read or write from the first location of the RAM area.

Next, in step (101), input scanning lines and output scanning lines are initialized. Next, in step (102), p/n2q/m<(p+1)/n...
・Determine whether (5) is true, but this is the second
As shown in the figure, the q-th output scanning line is connected to the p-th and (p
+1)th manual scanning line. When formula (5) is satisfied, step (1
03), the stopping coefficient Kq is calculated from equation (3). However, as shown in FIG. 2A, using the constant ri holds true, so Equation (3) can be expressed as follows. Next, in step (104), the decoder (2
4) Control line (23) is placed at address q in the RAM area.
c) and write the weighting coefficient Kq using step (1
05), the line number p of the manual scanning signal is written to address q of the built-in RAM of the CPU (23).

After that, in step (106), the line number j of the output scanning line is determined.
+q is increased by 1 and the process returns to step (102).

In addition, if formula (5) is not satisfied in step (102), the process moves to step (107), where the line number p of the manual scanning line is increased by 1, and in step (10B), the line number p is set to the upper limit. It is determined whether M max has been reached. If M raax has not been reached, the process returns to step (102), and if Mmax has been reached, the setting of the weighting coefficient kq is completed. In reality, this procedure can be completed more quickly by using the relationship Icq=kq+m.

After setting the market coefficient K (set of Kq) in this way,
The interpolation circuit shown in FIG. 1 generates an output video signal as follows.

First, the CPU (23) is the control line (23d)
Reset the decoder (26) via the . Next, after the output side horizontal synchronization signal HSY 2 rises, the decoder (
26) outputs the molding coefficient Kq for interpolation calculation at address "0" (q=O) in the RAM area, and C)'U (23) outputs the built-in RA
Using the line number p stored in the rOJ address of M, the signal A (p) of line number p is stored in the frame memory (
12) to the launch circuit (16), and almost simultaneously, the signal A(p+1) of the line number (p+■) is sequentially latched from the frame memory (12) to the launch circuit (17).

At this time, the output scanning line of line rOJ expressed by equation (41 (q=0)) is generated from the adder circuit (20).

Similarly, (q+1) of the output side horizontal synchronizing signal HGY 2
In synchronization with the fkth rising edge, the decoder (26) outputs q as the stop coefficient, and the latch circuits (16) and (17) store it in the q address of the built-in RAM of the CPU (23). Using line number p, signal A (p) of line number p and signal A of line number (p+1), respectively.
(p+1) is output. Therefore, from the adder circuit (20), the q-th output scanning signal a expressed by equation (4)
(q) is generated.

As explained above, in the scan converter device of this example, the multiplication in equation (4) can be performed by changing the voltages supplied to the amplitude setting terminals Vreft and Vref2 of the D/A converters (18) and (19). Since this is used as a substitute, there is an advantage that accurate interpolation calculations can be performed at extremely high speed with a simple configuration.

In addition, in the scan configuration device of this example, the D/A
The supply voltage to the converters (18) and (19) is
1-K) and K, and by setting one value K as the stopping coefficient, the insulating circuit can be further simplified. However, the gist of the present invention is not limited to this, and it is also possible to use fl (q) and fl (q) in the form of general functions as the stopping coefficient for the q-th output scanning signal. be.

Further, although the scan converter device of this example has a configuration that performs interpolation calculation on the input video signal stored in the frame memory, the present invention is not limited to this. The present invention can similarly be applied to a scan converter device configured to capture a signal into a line memory and generate an output video signal by multiplying the signal held in the line memory by a weighting coefficient. Furthermore, when the input signal is interlaced, the present invention can be applied to a field memory instead of a frame memory. The input video signals are R, G,
B-separated signals as well as Y.

C-separated signals can also be used in the same way.

As described above, the scan converter device of the present invention is not limited to the embodiment shown in FIG. 1, and various modifications can be made without departing from the gist of the present invention.

〔Effect of the invention〕

Since the scan converter device of the present invention is configured as described above, it is possible to perform high-speed interpolation calculations using an inexpensive and simple circuit, and to obtain smooth and natural output images.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the scan converter device of the present invention, FIG. 2 is a diagram for explaining the interpolation effect in the example in FIG. 1, and FIG. 3 is a setting for the stop coefficient in the example in FIG. 1. A flowchart showing the procedure, FIG. 4 is a partially cutaway perspective view of a monitor system using the scan converter device of the applicant's earlier application, and FIG. 5 is an input/output scanning line in the monitor system of FIG. 4. FIG. (12) is a frame memory, (16) and (17) are launch circuits, (18) and (19) are converters to D/8, (2
0) is an adder circuit, (23) is a CPU, (26) is a decoder, and (27) is a two-phase D/A converter.

Claims (1)

[Scope of Claims] Video signal storage means for digitally converting and storing a video signal of a first horizontal frequency, and a p-th scanning line video signal and a p+1-th scanning line obtained from the video signal storage means. first and second digital-to-analog conversion circuits to which video signals are supplied, respectively; and the first horizontal frequency and the second horizontal frequency of the output video signal to the first and second digital-to-analog conversion circuits, respectively. an amplitude-controlled power supply generating means for supplying a power supply whose amplitude is sequentially controlled in accordance with the above, and an adding means for adding the output signals of the first and second digital-to-analog conversion circuits, and an output of the adding means. A scan converter device characterized in that a video signal of the second horizontal frequency is obtained on the side.