JPH0122768B2 - - Google Patents

Info

Publication number
JPH0122768B2
JPH0122768B2 JP21672183A JP21672183A JPH0122768B2 JP H0122768 B2 JPH0122768 B2 JP H0122768B2 JP 21672183 A JP21672183 A JP 21672183A JP 21672183 A JP21672183 A JP 21672183A JP H0122768 B2 JPH0122768 B2 JP H0122768B2
Authority
JP
Japan
Prior art keywords
circuit
frequency
signal
circuits
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21672183A
Other languages
Japanese (ja)
Other versions
JPS60109306A (en
Inventor
Akira Yamaguchi
Hiroshi Mobara
Hidemi Izeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP21672183A priority Critical patent/JPS60109306A/en
Priority to DE8484113778T priority patent/DE3474597D1/en
Priority to EP84113778A priority patent/EP0142171B1/en
Priority to DE8787117485T priority patent/DE3486061T2/en
Priority to EP87117485A priority patent/EP0308540B1/en
Priority to US06/672,478 priority patent/US4599580A/en
Publication of JPS60109306A publication Critical patent/JPS60109306A/en
Publication of JPH0122768B2 publication Critical patent/JPH0122768B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
    • H03K4/023—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform by repetitive charge or discharge of a capacitor, analogue generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/005—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing phase or frequency of 2 mutually independent oscillations in demodulators)
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/02—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using spectral analysis, e.g. transform vocoders or subband vocoders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • Computational Linguistics (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Human Computer Interaction (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To detect a frequency shift by comparison with high precision by providing two circuits which have their resistance values set according to the frequency of an input signal and also have a positive and a negative equivalent resistance, integrating their composite value and obtaining an output voltage, and varying the DC bias of one circuit. CONSTITUTION:A negative switched capacitor circuit 10 has its resistance value set according to a frequency to be compared with a reference frequency and also has the negative equivalent resistance, and a positive switched capacitor circuit 20 has its resistance value set according to the reference frequency and also has the positive equivalent resistance. When a DC bias is supplied to one- side terminals of both circuits 10 and 20, the composite value of output currents of both circuits 10 and 20 is integrated 35 to obtain the output voltage, and the DC bias of the positive swithced capacitor circuit is varied according to the output voltage of an integrating circuit 35. Consequently, a frequency shift is detected from the constant output voltage of the integration circuit 35.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、２つの信号の周波数の大小比較を
行なう周波数比較回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frequency comparison circuit that compares the frequencies of two signals.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

最近、デイジタル技術を用いて音声合成を行な
う装置が開発、実用化されている。この装置では
たとえば、インパルスや白色雑音を音源として用
いて、この音源からの信号をいくつかのデイジタ
ル・フイルタ回路を通過させることによつてアナ
ログ音声信号を得るようにしている。そして、上
記各デイジタル・フイルタ回路における条件設定
は、そのときに得るべきアナログ音声信号に対応
して行なわれる。また上記デイジタル音声合成装
置における各デイジタル・フイルタ回路の条件設
定は、実際の音声を分析し認識した結果に基づい
て行なわれる。 Recently, devices that perform speech synthesis using digital technology have been developed and put into practical use. In this device, for example, an impulse or white noise is used as a sound source, and the signal from this sound source is passed through several digital filter circuits to obtain an analog audio signal. The conditions for each digital filter circuit are set in accordance with the analog audio signal to be obtained at that time. Further, the conditions for each digital filter circuit in the digital speech synthesizer are set based on the results of analyzing and recognizing actual speech.

第１図は上記音声認識を行なう音声認識回路の
一般的な構成を示す回路図である。第１図におい
て、１はマイクアンプである。このマイクアンプ
１は、図示しないマイクロフオンによつて変換さ
れたアナログ信号を増幅するためのものである。
上記マイクアンプ１の出力はたとえば４個のバン
ドパスフイルタ回路（BPF）２Ａ，２Ｂ，２Ｃ，
２Ｄに並列的に供給される。さらに上記バンドパ
スフイルタ回路２Ａ，２Ｂ，２Ｃ，２Ｄを通過し
た信号は４個の検出回路（DET）３Ａ，３Ｂ，
３Ｃ，３Ｄそれぞれによつて検出され、各検出信
号は４個の各ローパスフイルタ回路（LPF）４
Ａ，４Ｂ，４Ｃ，４Ｄに供給される。上記ローパ
スフイルタ回路４Ａ，４Ｂ，４Ｃ，４Ｄを通過し
た信号はマルチプレクサ（MPX）５を介してア
ナログ／デイジタル変換回路（Ａ／Ｄ）６に選択
的に供給される。そして上記アナログ／デイジタ
ル変換回路６からのデイジタル出力が前記マイク
ロフオンからの入力音声に対する認識結果とな
る。 FIG. 1 is a circuit diagram showing a general configuration of a speech recognition circuit that performs the above-mentioned speech recognition. In FIG. 1, 1 is a microphone amplifier. This microphone amplifier 1 is for amplifying an analog signal converted by a microphone (not shown).
The output of the microphone amplifier 1 is transmitted through, for example, four bandpass filter circuits (BPF) 2A, 2B, 2C,
2D in parallel. Furthermore, the signals that have passed through the band pass filter circuits 2A, 2B, 2C, and 2D are sent to four detection circuits (DET) 3A, 3B,
3C and 3D, and each detection signal is sent to each of four low-pass filter circuits (LPF) 4.
It is supplied to A, 4B, 4C, and 4D. The signals that have passed through the low-pass filter circuits 4A, 4B, 4C, and 4D are selectively supplied to an analog/digital conversion circuit (A/D) 6 via a multiplexer (MPX) 5. The digital output from the analog/digital conversion circuit 6 becomes the recognition result for the input voice from the microphone.

ところで、最近の音声認識回路では、スイツチ
ドキヤパシタ・フイルタ技術を用いることによつ
て回路の高集積度化および高精度化が図られるよ
うになつてきており、前記マイクアンプ１、バン
ドパスフイルタ回路２およびローパスフイルタ回
路４はすべてスイツチドキヤパシタ回路を用いて
構成されている。このスイツチドキヤパシタ回路
を用いた回路では、各スイツチドキヤパシタ回路
を制御するために、発振回路と、この発振回路の
出力から種々のクロツクパルスを形成するための
クロツク発生回路が必要となり、各スイツチドキ
ヤパシタ回路ひいては音声認識回路の精度はこの
クロツクパルスの精度に依存している。 By the way, in recent speech recognition circuits, higher integration and higher accuracy have been achieved by using switched capacitor filter technology, and the microphone amplifier 1, bandpass filter The circuit 2 and the low-pass filter circuit 4 are all constructed using switched capacitor circuits. A circuit using this switched capacitor circuit requires an oscillation circuit and a clock generation circuit to form various clock pulses from the output of this oscillation circuit in order to control each switched capacitor circuit. The accuracy of the switched capacitor circuit and thus the speech recognition circuit depends on the accuracy of this clock pulse.

ところで、上記発振回路における正確な発振周
波数が求められた場合に、その正確な発振周波数
に対する実際の発振周波数の大小関係、ずれもし
くは両周波数の比を正確に知ることができれば、
実際の発振周波数を正確なものに一致させること
ができる。しかしながら、従来では上記周波数の
大小関係、ずれもしくは周波数比を正確に検出す
る手段としてはたとえばPLL回路等があるが、
このPLL回路は回路構成が複雑であり集積回路
化には適していない。このため従来から存在して
いる回路構成が簡単なものでは正確な発振周波数
を得ることができず、上記スイツチドキヤパシタ
回路自体ひいては音声認識回路の精度を悪化させ
ている。 By the way, if the exact oscillation frequency of the above oscillation circuit is found, if it is possible to accurately know the magnitude relationship, deviation, or ratio of the actual oscillation frequency to the exact oscillation frequency,
The actual oscillation frequency can be accurately matched. However, in the past, PLL circuits and the like have been used as means for accurately detecting the magnitude relationship, deviation, or frequency ratio of the frequencies.
This PLL circuit has a complicated circuit configuration and is not suitable for integrated circuit implementation. For this reason, it is not possible to obtain an accurate oscillation frequency with the conventional simple circuit configuration, which deteriorates the accuracy of the switched capacitor circuit itself and the speech recognition circuit.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような事情を考慮してなされ
たものであり、その目的は、２つの信号の周波数
の大小関係を高精度に比較検出することができ、
しかも回路構成も簡単な周波数比較回路を提供す
ることにある。 This invention was made in consideration of the above-mentioned circumstances, and its purpose is to be able to compare and detect the frequency relationship of two signals with high precision,
Moreover, it is an object of the present invention to provide a frequency comparison circuit with a simple circuit configuration.

〔発明の概要〕[Summary of the invention]

この発明による周波数比較回路では、基準周波
数と比較すべき周波数に応じてその抵抗値が設定
され、負の等価抵抗を有する負性のスイツチドキ
ヤパシタ回路および上記基準周波数に応じてその
抵抗値が設定され、正の等価抵抗を有する正性の
スイツチドキヤパシタ回路が設けられ、上記２個
のスイツチドキヤパシタ回路の各一端には一定の
直流電圧が並列的に供給され、上記２個のスイツ
チドキヤパシタ回路の出力電流の合成電流を得る
ようにその各他端が共通接続され、この合成され
た電流を積分する積分回路が設けられている。 In the frequency comparison circuit according to the present invention, the resistance value is set according to the frequency to be compared with the reference frequency, and the resistance value is set according to the negative switched capacitor circuit having a negative equivalent resistance and the reference frequency. A positive switched capacitor circuit having a positive equivalent resistance is provided, and a constant DC voltage is supplied in parallel to one end of each of the two switched capacitor circuits. The other ends of the switched capacitor circuits are commonly connected to obtain a combined current of the output currents of the switched capacitor circuits, and an integrating circuit is provided to integrate the combined current.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照してこの発明の実施例を説明す
る。第２図はこの発明の周波数比較回路の一実施
例に係る構成を示す回路図である。図において１
０はキヤパシタ１１と４個のスイツチ１２ないし
１５とを有し、その周波数を比較すべき一方の信
号たとえば発振回路からの発振信号SSの周波数S
に応じて抵抗値が設定されかつ負の等価抵抗を持
つスイツチドキヤパシタ回路である。上記スイツ
チドキヤパシタ回路１０において、キヤパシタ１
１の一端にはスイツチ１２および１３の各一端が
接続されており、さらにスイツチ１２の他端はア
ース点に接続されている。上記キヤパシタ１１の
他端にはスイツチ１４および１５の各一端が接続
されており、さらにスイツチ１４の他端はアース
点に接続されている。そして上記４個のスイツチ
１２ないし１５のうちそれぞれ２個ずつのスイツ
チ１２，１５および１３，１４が、信号SSに応じ
て交互にオン状態にされる。２０はキヤパシタ２
１と４個のスイツチ２２ないし２５とを有し、周
波数が一定した基準信号SCのその周波数Cに応じ
て抵抗値が設定されかつ正の等価抵抗を持つスイ
ツチドキヤパシタ回路２０である。このスイツチ
ドキヤパシタ回路２０において、キヤパシタ２１
の一端にはスイツチ２２および２３の各一端が接
続されており、さらにスイツチ２３の他端はアー
ス点に接続されている。上記キヤパシタ２１の他
端にはスイツチ２４および２５の各一端が接続さ
れており、さらにスイツチ２５の他端はアース点
に接続されている。そして上記４個のスイツチ２
２ないし２５のうちそれぞれ２個ずつのスイツチ
２２，２４および２３，２５が、信号SCに応じて
交互にオン状態にされる。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of an embodiment of the frequency comparison circuit of the present invention. In the figure 1
0 has a capacitor 11 and four switches 12 to 15, and one signal whose frequency is to be compared, for example, the frequency S of an oscillation signal S S from an oscillation circuit.
This is a switched capacitor circuit whose resistance value is set according to the negative equivalent resistance. In the switched capacitor circuit 10, the capacitor 1
1 is connected to one end of each of switches 12 and 13, and the other end of switch 12 is connected to a ground point. One end of each of switches 14 and 15 is connected to the other end of the capacitor 11, and the other end of switch 14 is connected to a ground point. Of the four switches 12 to 15, two switches 12, 15 and 13, 14 are alternately turned on in response to the signal SS . 20 is capacitor 2
1 and four switches 22 to 25, the resistance value is set according to the frequency C of a reference signal S C having a constant frequency, and the switched capacitor circuit 20 has a positive equivalent resistance. In this switched capacitor circuit 20, a capacitor 21
One end of each of switches 22 and 23 is connected to one end of the switch 23, and the other end of switch 23 is connected to a ground point. One end of each of switches 24 and 25 is connected to the other end of the capacitor 21, and the other end of switch 25 is connected to a ground point. And the above four switches 2
Two switches 22, 24 and 23, 25 among switches 2 to 25 are alternately turned on in response to the signal SC .

上記一方のスイツチドキヤパシタ回路１０内の
スイツチ１３の他端と他方のスイツチドキヤパシ
タ回路２０内のスイツチ２２の他端とが共通接続
され、この接続点ａには直流電源Ｖの正極側が接
続されている。上記直流電源Ｖの負極側はアース
点に接続されている。また上記一方のスイツチド
キヤパシタ回路１０内のスイツチ１５の他端と他
方のスイツチドキヤパシタ回路２０内のスイツチ
２４の他端とが共通接続され、この接続点ｂには
積分回路３０の入力端が接続されている。この積
分回路３０は、反転入力端子、非反転入力端子お
よび出力端子を有する差動増幅回路３１とキヤパ
シタ３２を備えており、キヤパシタ３２は差動増
幅回路３１の反転入力端子と出力端子との間に接
続され、差動増幅回路３１の非反転入力端子はア
ース点に接続されている。また上記差動増幅回路
３１は正極性の電源電圧VDDと負極性の電源電圧
VSSとの間の電圧で動作するようになつており、
前記アース点の電位は上記両電圧VDDとVSSの中
間電位たとえば0Vに設定されている。そしてこ
の積分回路３０では、差動増幅回路３１の反転入
力端子が上記入力端として用いられ、また出力端
子からは前記２つの周波数SとCの大小関係に応
じた信号OUTが出力されるようになつている。 The other end of the switch 13 in one of the switched capacitor circuits 10 and the other end of the switch 22 in the other switched capacitor circuit 20 are commonly connected, and the positive side of the DC power supply V is connected to this connection point a. It is connected. The negative pole side of the DC power supply V is connected to a ground point. Further, the other end of the switch 15 in one of the switched capacitor circuits 10 and the other end of the switch 24 in the other switched capacitor circuit 20 are commonly connected, and this connection point b is connected to the input of the integrating circuit 30. The ends are connected. The integrating circuit 30 includes a differential amplifier circuit 31 having an inverting input terminal, a non-inverting input terminal, and an output terminal, and a capacitor 32. The capacitor 32 is connected between the inverting input terminal and the output terminal of the differential amplifier circuit 31. The non-inverting input terminal of the differential amplifier circuit 31 is connected to the ground point. Further, the differential amplifier circuit 31 has a positive polarity power supply voltage V DD and a negative polarity power supply voltage V DD .
It is designed to operate at a voltage between V SS and
The potential of the ground point is set to an intermediate potential between the two voltages VDD and VSS , for example 0V. In this integrating circuit 30, the inverting input terminal of the differential amplifier circuit 31 is used as the input terminal, and the output terminal outputs a signal OUT according to the magnitude relationship between the two frequencies S and C. It's summery.

このような構成において、一方のスイツチドキ
ヤパシタ回路（以下SC回路と略称する）１０の
等価抵抗値R1は、キヤパシタ１１の値をC1とす
ると次式で与えられる。 In such a configuration, the equivalent resistance value R 1 of one switched capacitor circuit (hereinafter abbreviated as SC circuit) 10 is given by the following equation, assuming that the value of the capacitor 11 is C 1 .

R1＝−１／C2・S …(1) 同様に他方のSC回路２０の等価抵抗値R2は、
キヤパシタ２１の値をC2とすると次式で与えら
れる。 R 1 =-1/C 2 · S (1) Similarly, the equivalent resistance value R 2 of the other SC circuit 20 is
Letting the value of the capacitor 21 be C2 , it is given by the following equation.

R2＝１／C2・C …(2) いま２個のSC回路１０，２０の各一端すなわ
ちスイツチ１３，２２の他端はａ点を介して直流
電源Ｖの正極側に共通接続されているので、各
SC回路１０，２０には直流電源Ｖから正極性の
バイアスが供給され、それぞれに所定の直流電流
が流される。ここで一方のSC回路１０は負の等
価抵抗値R1を持つためにその電流I1の向きは第２
図中左方向となる。また他方のSC回路２０は正
の等価抵抗値R2を持つためにその電流I2の向きは
第２図中右方向となる。すなわち、電流I1，I2の
方向は互いに逆方向となる。そして積分回路３０
にはこの両電流I1，I2の合成電流が供給される。
いま、この合成電流が０の場合、積分回路３０の
出力信号OUTはアース電位にされる。また、電
流I1の値がI2よりも大きく、この両電流の差に相
当する電流が積分回路３０から流れ出る場合、積
分回路３０の出力信号OUTは低レベル（VSSレベ
ル）にされる。上記とは逆に電流I2の値がI1より
も大きく、この両電流の差に相当する電流が積分
回路３０に流れ込む場合、積分回路３０の出力信
号OUTは高レベル（VDDレベル）にされる。ここ
で仮に一方のSC回路１０内のキヤパシタ１１の
値C1と他方のSC回路２０内のキヤパシタ２１の
値C2とが等価に設定されているとすれば、発振
信号SSの周波数Sが基準信号SCの周波数Cと一致
したときに積分回路３０の出力信号OUTはアー
ス電位にされ、周波数SがCよりも大きいときに
積分回路３０の出力信号OUTは低レベルにされ、
さらに周波数SがCよりも小さいときに積分回路
３０の出力信号OUTは高レベルにされる。すな
わち、積分回路３０の出力信号OUTは２つの周
波数SとCの大小関係に対応したものとなつてい
るので、この信号OUTを確認することによつて
SとCの大小関係を比較することができる。しか
も２個のSC回路１０，２０における等価抵抗の
値がR1，R2は前記(1)，(2)式に示すように、C1，
C2の値がそれぞれ一定であれば周波数S，Cのみ
によつて決定され、キヤパシタC1，C2の値は抵
抗等に比べてはるかに高い精度で設定することが
できるので、各周波数S，Cは高精度で抵抗値
R1，R2に変換される。さらに積分回路３０はこ
の両抵抗値R1，R2に応じて流れる電流の合成値
を積分することによつて信号OUTを得るように
しているので、差動増幅回路３１自体のスルーレ
ートやゲインにばらつきが存在していても、Sと
Cとの比較を高精度で行なうことができる。 R 2 =1/C 2・C (2) Now, one end of each of the two SC circuits 10 and 20, that is, the other ends of the switches 13 and 22, are commonly connected to the positive side of the DC power supply V via point a. Since there are
A positive polarity bias is supplied to the SC circuits 10 and 20 from a DC power supply V, and a predetermined DC current is passed through each of the SC circuits 10 and 20. Here, since one SC circuit 10 has a negative equivalent resistance value R 1 , the direction of the current I 1 is the second one.
The direction is to the left in the figure. Furthermore, since the other SC circuit 20 has a positive equivalent resistance value R 2 , the direction of its current I 2 is toward the right in FIG. That is, the directions of currents I 1 and I 2 are opposite to each other. and integrating circuit 30
A composite current of these two currents I 1 and I 2 is supplied to .
Now, when this combined current is 0, the output signal OUT of the integrating circuit 30 is set to the ground potential. Further, when the value of current I 1 is larger than I 2 and a current corresponding to the difference between the two currents flows out of the integrating circuit 30, the output signal OUT of the integrating circuit 30 is set to a low level (V SS level). Contrary to the above, when the value of current I 2 is larger than I 1 and a current corresponding to the difference between the two currents flows into the integrating circuit 30, the output signal OUT of the integrating circuit 30 goes to a high level (V DD level). be done. Here, if the value C 1 of the capacitor 11 in one SC circuit 10 and the value C 2 of the capacitor 21 in the other SC circuit 20 are set equal, the frequency S of the oscillation signal S S is When the frequency C of the reference signal S C matches, the output signal OUT of the integrating circuit 30 is set to ground potential, and when the frequency S is greater than C , the output signal OUT of the integrating circuit 30 is set to a low level.
Further, when the frequency S is smaller than C , the output signal OUT of the integrating circuit 30 is set to a high level. In other words, since the output signal OUT of the integrating circuit 30 corresponds to the magnitude relationship between the two frequencies S and C , by checking this signal OUT,
The magnitude relationship between S and C can be compared. Moreover, the equivalent resistance values of the two SC circuits 10 and 20 are R 1 and R 2 , as shown in equations (1) and (2) above, C 1 ,
If the values of C 2 are constant, they are determined only by the frequencies S and C , and the values of the capacitors C 1 and C 2 can be set with much higher precision than resistors, etc., so each frequency S , C is the resistance value with high precision
Converted to R 1 and R 2 . Furthermore, since the integrating circuit 30 obtains the signal OUT by integrating the combined value of the currents flowing according to both resistance values R 1 and R 2 , the slew rate and gain of the differential amplifier circuit 31 itself Even if there is variation in S and
Comparisons with C can be made with high accuracy.

このようにこの実施例によれば、発振回路から
の発振信号SSの周波数Sと基準信号SCの周波数C
との大小関係を高精度で比較検出することができ
る。このため、その出力信号OUTを用いて、周
波数Sを基準の周波数Cに高精度に一致させるこ
とが可能である。また、この実施例において、２
個のSC回路１０，２０内のキヤパシタ１１，２
１は値C1，C2の設定を変えることにより、基準
信号SCの見かけ上の周波数を実際の値Cと異なら
せることも可能である。たとえば、C1＝２・C2
の関係を満たすようにキヤパシタ１１，２１の値
を設定すれば、この回路では２・CとSとの大小
関係が比較検出される。 In this way, according to this embodiment, the frequency S of the oscillation signal S S from the oscillation circuit and the frequency C of the reference signal S C
It is possible to compare and detect the magnitude relationship with high accuracy. Therefore, using the output signal OUT, it is possible to match the frequency S with the reference frequency C with high precision. In addition, in this example, 2
Capacitors 11 and 2 in SC circuits 10 and 20
1 , it is also possible to make the apparent frequency of the reference signal S C different from the actual value C by changing the settings of the values C 1 and C 2 . For example, C 1 = 2・C 2
If the values of the capacitors 11 and 21 are set so as to satisfy the relationship, the magnitude relationship between 2· C and S can be compared and detected in this circuit.

第３図はこの発明の周波数比較回路の他の実施
例に係る構成を示す回路図である。この実施例回
路は、第２図の実施例回路に比べて、積分回路３
０内のキヤパシタ３２に対して抵抗３３を並列接
続した点が異なるのみであり、他の構成は第２図
と同様である。 FIG. 3 is a circuit diagram showing the configuration of another embodiment of the frequency comparison circuit of the present invention. This embodiment circuit is different from the embodiment circuit shown in FIG.
The only difference is that a resistor 33 is connected in parallel to the capacitor 32 in FIG. 2, and the other configurations are the same as in FIG.

この実施例回路では、２個のSC回路１０，２
０の出力電流I1，I2の合成値が０のときに出力信
号OUTがアース電位に設定される点は第２図の
ものと同様であるが、合成値が０でない場合に出
力信号OUTはそのときの合成電流の極性に応じ
て、VDDもしくはVSSレベルまで達しない途中の
電位に設定される。 In this example circuit, two SC circuits 10, 2
The point that the output signal OUT is set to the ground potential when the combined value of the output currents I 1 and I 2 is 0 is similar to that in Figure 2, but when the combined value is not 0, the output signal OUT is set to the ground potential. is set to an intermediate potential that does not reach the V DD or V SS level, depending on the polarity of the combined current at that time.

第４図および第５図はそれぞれ前記各実施例回
路で用いられている２個のSC回路１０，２０そ
れぞれを具体的に示す回路図である。なお、第４
図および第５図において、前記第２図もしくは第
３図と対応する箇所には同一符号を付して説明す
る。また前記信号SS，SCとして実際には、第６図
のタイミングチヤートに示すように互いに位相が
異なる２相の信号SS1，SS2もしくはSC1，SC2が用
いられる。 FIGS. 4 and 5 are circuit diagrams specifically showing two SC circuits 10 and 20 used in each of the embodiment circuits. In addition, the fourth
In FIG. 5 and FIG. 5, parts corresponding to those in FIG. 2 or 3 will be described with the same reference numerals. Further, as the signals S S and S C , two-phase signals S S1 and S S2 or S C1 and S C2 having mutually different phases are actually used as shown in the timing chart of FIG. 6.

負の等価抵抗値を有する一方のSC回路１０内
のスイツチ１２ないし１５は第４図に示すよう
に、ＮチヤネルMOSFET４１ないし４４それぞ
れとＰチヤネルMOSFET４５ないし４８それぞ
れと並列接続してなるCMOSスイツチ５２ない
し５５で構成されている。そして上記Ｎチヤネル
MOSFET４１，４４のゲートには第６図中の信
号SS1が、ＰチヤネルMOSFET４５，４８のゲー
トにはCMOSインバータ４９を介して上記信号
SS1がそれぞれ供給され、上記Ｎチヤネル
MOSFET４２，４３のゲートには第６図中の信
号SS2が、ＰチヤネルMOSFET４６，４７のゲー
トにはCMOSインバータ５０を介して上記信号
SS2がそれぞれ供給されている。 Switches 12 to 15 in one SC circuit 10 having a negative equivalent resistance value are CMOS switches 52 to 15 connected in parallel with N-channel MOSFETs 41 to 44, respectively, and P-channel MOSFETs 45 to 48, respectively, as shown in FIG. It consists of 55. And the above N channel
The signal S S1 in FIG. 6 is applied to the gates of MOSFETs 41 and 44, and the above signal is applied to the gates of P-channel MOSFETs 45 and 48 via a CMOS inverter 49.
S S1 is supplied respectively, and the above N channels
The signal S S2 in FIG. 6 is applied to the gates of MOSFETs 42 and 43, and the above signal is applied to the gates of P-channel MOSFETs 46 and 47 via a CMOS inverter 50.
S S2 are supplied respectively.

このような構成において、いまCMOSスイツ
チ５３の他端に直流電圧V1を供給し、CMOSス
イツチ５５の他端にはアース電位を供給した状態
で各CMOSスイツチ５２ないし５５を信号SS1，
SS2に応じてスイツチ制御した場合について説明
する。いま、信号SS2が高レベルのときには
CMOSスイツチ５３，５４がオン状態にされる。
このとき、キヤパシタ１１の他端（第４図のｃ
点）には−C1・V1の電荷が蓄積される。次に信
号SS1が高レベルのときにはCMOSスイツチ５２，
５５がオン状態にされる。このとき、上記ｃ点に
は予め蓄積されている負の電荷を打消すように、
アース点からCMOSスイツチ５５を介して正の
電荷＋C1・V1が供給される。このような動作が
１秒間当りS回繰り返されるので、ｃ点から
CMOSスイツチ５５を介してアース点に流れる
電流の向きを正とした場合にこのSC回路に流れ
る電流の値Ｉは次式で与えられる。 In such a configuration, with the DC voltage V 1 being supplied to the other end of the CMOS switch 53 and the ground potential being supplied to the other end of the CMOS switch 55, each of the CMOS switches 52 to 55 is connected to the signals S S1 ,
A case where switch control is performed according to S S2 will be explained. Now, when the signal S S2 is at a high level,
CMOS switches 53 and 54 are turned on.
At this time, the other end of the capacitor 11 (c in FIG.
A charge of −C 1 · V 1 is accumulated at the point ). Next, when the signal S S1 is at a high level, the CMOS switch 52,
55 is turned on. At this time, in order to cancel the negative charge that has been accumulated in advance at the point c,
Positive charge +C 1 ·V 1 is supplied from the ground point via the CMOS switch 55 . This kind of operation is repeated S times per second, so from point c
When the direction of the current flowing through the CMOS switch 55 to the ground point is positive, the value I of the current flowing through this SC circuit is given by the following equation.

−Ｉ＝C1・V1・S …(3) このSC回路における等価抵抗Ｒの値は、供給
電圧V1を上記電流Ｉで割つたものであるので、
このＲは次式で与えられる。 -I= C1・V1・S ...(3) The value of the equivalent resistance R in this SC circuit is the supply voltage V1 divided by the above current I, so
This R is given by the following formula.

Ｒ＝V1／−C1・V1・S＝−１／C1・S …(4) この(4)式の右辺は前記(1)式の右辺と同じであ
り、第４図のSC回路が周波数Sに応じた負の等
価抵抗を持つ回路であることがわかる。 R=V 1 /−C 1・V 1・S =−1/C 1・S …(4) The right side of this equation (4) is the same as the right side of the above equation (1), and the SC in Fig. 4 It can be seen that the circuit has a negative equivalent resistance depending on the frequency S.

正の等価抵抗値を有する他方のSC回路２０内
のスイツチ２２ないし２５は第５図に示すよう
に、ＮチヤネルMOSFET６１ないし６４それぞ
れとＰチヤネルMOSFET６５ないし６８それぞ
れとを並列接続してなるCMOSスイツチ７２な
いし７５で構成されている。そして上記Ｎチヤネ
ルMOSFET６１，６３のゲートには第６図中の
信号SC1が、ＰチヤネルMOSFET６５，６７のゲ
ートにはCMOSインバータ６９を介して上記信
号SC1がそれぞれ供給され、上記Ｎチヤネル
MOSFET６２，６４のゲートには第６図中の信
号SC2が、ＰチヤネルMOSFET６６，６８のゲー
トにはCMOSインバータ７０を介して上記信号
SC2がそれぞれ供給されている。 The switches 22 to 25 in the other SC circuit 20 having a positive equivalent resistance value are, as shown in FIG. 75. The signal S C1 shown in FIG. 6 is supplied to the gates of the N-channel MOSFETs 61 and 63, and the signal S C1 is supplied to the gates of the P-channel MOSFETs 65 and 67 via a CMOS inverter 69.
The signal S C2 in FIG. 6 is applied to the gates of MOSFETs 62 and 64, and the above signal is applied to the gates of P-channel MOSFETs 66 and 68 via a CMOS inverter 70.
S C2 is supplied respectively.

このように構成において、いまCMOSスイツ
チ７２の他端に直流電圧V2を供給し、CMOSス
イツチ７４の他端にはアース電位を供給した状態
で各CMOSスイツチ７２ないし７５を信号SC1，
SC2に応じてスイツチ制御した場合について説明
する。いま信号SC1が高レベルのときにはCMOS
スイツチ７２，７４がオン状態にされる。このと
き、キヤパシタ２１にはC2・V2なる電荷が蓄積
される。次に信号SC2が高レベルになると、今度
はCMOSスイツチ７３，７５がオン状態にされ、
いままでキヤパシタ２１に蓄えられていた電荷は
アース点に放出される。このような動作が１秒間
当りC回繰り返されるので、キヤパシタ２１の他
端（第５図のｄ点）からCMOSスイツチ７４を
介してアース点に流れる電流の向きを正とした場
合にこのSC回路に流れる電流の値Ｉは次式で与
えられる。 In this configuration, with the DC voltage V 2 being supplied to the other end of the CMOS switch 72 and the ground potential being supplied to the other end of the CMOS switch 74, each of the CMOS switches 72 to 75 is connected to the signals S C1 ,
The case where switch control is performed according to S C2 will be explained. If the signal S C1 is currently at a high level, the CMOS
Switches 72 and 74 are turned on. At this time, charges C 2 ·V 2 are accumulated in the capacitor 21 . Next, when the signal S C2 becomes high level, the CMOS switches 73 and 75 are turned on.
The charge that has been stored in the capacitor 21 is released to the ground point. Such an operation is repeated C times per second, so if the direction of the current flowing from the other end of the capacitor 21 (point d in Figure 5) to the ground point via the CMOS switch 74 is positive, this SC circuit The value I of the current flowing through is given by the following equation.

Ｉ＝C2・V2・C …(5) またこのSC回路における等価抵抗Ｒの値は、
供給電圧V2を上記電流Ｉで割つたものであるの
で、このＲは次式で与えられる。 I=C 2・V 2・C …(5) Also, the value of the equivalent resistance R in this SC circuit is
Since it is the supply voltage V 2 divided by the current I, this R is given by the following equation.

Ｒ＝V2／C2・V2・C＝１／C2・C …(6) この(6)式の右辺は前記(2)式の右辺と同じであ
り、第５図のSC回路が周波数Cに応じた正の等
価抵抗を持つ回路であることがわかる。 R=V 2 /C 2・V 2・C = 1/C 2・C …(6) The right side of equation (6) is the same as the right side of equation (2) above, and the SC circuit in Figure 5 is It can be seen that the circuit has a positive equivalent resistance depending on the frequency C.

第７図はこの発明の応用例の構成を示す回路図
である。この応用例回路は前記第２図と同様に構
成された２個の周波数比較回路１００，２００
と、これら両出力信号OUT1，OUT2が並列的に
入力されるANDゲート３００とで構成されてい
る。また、一方の周波数比較回路１００内の負の
等価抵抗を持つSC回路（第２図中の１０）は高
い基準周波数Caを持つ信号SCaで制御されてお
り、正の等価抵抗を持つSC回路（第２図中の２
０）は比較される周波数Sを持つ信号SSで制御さ
れている。他方の周波数比較回路２００内の負の
等価抵抗を持つSC回路（第２図中の１０）は低
い基準周波数Cbを持つ信号SCbで制御されてお
り、正の等価抵抗を持つSC回路（第２図中の２
０）は上記信号SSで制御されている。 FIG. 7 is a circuit diagram showing the configuration of an applied example of the present invention. This application example circuit consists of two frequency comparator circuits 100 and 200 configured in the same manner as in FIG.
and an AND gate 300 to which both output signals OUT 1 and OUT 2 are input in parallel. Furthermore, the SC circuit (10 in FIG. 2) having a negative equivalent resistance in one frequency comparator circuit 100 is controlled by the signal S Ca having a high reference frequency Ca , and the SC circuit having a positive equivalent resistance (2 in Figure 2
0) is controlled by a signal S S with a frequency S to be compared. The SC circuit (10 in FIG. 2) with a negative equivalent resistance in the other frequency comparison circuit 200 is controlled by the signal S Cb with a low reference frequency Cb , and the SC circuit (10 in FIG. 2) with a positive equivalent resistance is controlled by the signal S Cb with a low reference frequency Cb. 2 in 2 diagrams
0) is controlled by the signal S S mentioned above.

この回路において、各SC回路内のキヤパシタ
の値がすべて等しく設定されているならば、上記
信号SCa，SCb，SSの周波数Ca，Cb，S間でCa＞
S＞Cbの関係が成立するときのみに２個の周波
数比較回路１００，２００の出力信号OUT1，
OUT2が高レベルとなり、ANDゲート３００の
出力が高レベルにされる。すなわちこの回路で
は、比較すべき周波数Sが高い方の基準周波数
Caと低い方の基準周波数Cbとの間の範囲の値で
あるか否かを検出することができる。 In this circuit, if the values of the capacitors in each SC circuit are all set equal, Ca > between the frequencies Ca , Cb , and S of the signals S Ca , S Cb , and S S.
Only when the relationship S > Cb holds true, the output signals OUT 1 ,
OUT 2 becomes high level, and the output of AND gate 300 becomes high level. In other words, in this circuit, the frequency S to be compared is the higher reference frequency.
It is possible to detect whether the value is in the range between Ca and the lower reference frequency Cb .

なお、この発明は上記各実施例に限定されるも
のでは種々の変形が可能である。たとえば上記第
２図および第３図の各実施例回路では２個のSC
回路１０，２０に直流電流を流すために共通の直
流電源Ｖを用いる場合について説明したが、これ
は異なる直流電源を用いるようにしてもよい。そ
して異なる直流電源を用いた場合にその電圧値を
異ならせることによつて、キヤパシタ１１と２１
の値を異ならせたときと同様に基準信号SCの見か
け上の周波数を実際の値Cと異ならせることもで
きる。また、上記各実施例回路では、負の等価抵
抗を持つ一方のSC回路１０を信号SSで制御し、
正の等価抵抗を持つ他方のSC回路２０を信号SC
で制御する場合について説明したが、これは互い
に他方の信号で制御するように構成してもよい。 Note that this invention is not limited to the above embodiments and can be modified in various ways. For example, in each of the embodiment circuits shown in FIGS. 2 and 3 above, two SC
Although a case has been described in which a common DC power supply V is used to flow DC current through the circuits 10 and 20, different DC power supplies may be used. By changing the voltage value when using different DC power supplies, capacitors 11 and 21
It is also possible to make the apparent frequency of the reference signal S C different from the actual value C in the same way as when the values of C are made different. Furthermore, in each of the above embodiment circuits, one SC circuit 10 having a negative equivalent resistance is controlled by the signal S S ,
The other SC circuit 20 with positive equivalent resistance is connected to the signal S C
Although a case has been described in which the signals are controlled by the signals of the other, the control may be performed using the signals of the other.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明によれば、２つの
信号の周波数の大小関係をPLL回路に比べ簡単
な回路構成で高精度に比較検出することができる
周波数比較回路が提供できる As explained above, according to the present invention, it is possible to provide a frequency comparison circuit that can compare and detect the magnitude relationship between the frequencies of two signals with a simpler circuit configuration than a PLL circuit with high precision.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は音声認識回路の一般的な構成を示す回
路図、第２図はこの発明に係る周波数比較回路の
一実施例の構成を示す回路図、第３図はこの発明
の他の実施例の構成を示す回路図、第４図および
第５図はそれぞれ上記第２図回路および第３図回
路で用いられているスイツチドキヤパシタ回路を
具体的に示す回路図、第６図は第４図および第５
図の回路で用いられる信号のタイミングチヤー
ト、第７図はこの発明の応用例の構成を示す回路
図である。 １０，２０…スイツチドキヤパシタ回路（SC
回路）、１１，２１…キヤパシタ、１２〜１５，
２２〜２５…スイツチ、３０…積分回路、３１…
差動増幅回路、５２〜５５，７２〜７５…
CMOSスイツチ。 FIG. 1 is a circuit diagram showing the general configuration of a speech recognition circuit, FIG. 2 is a circuit diagram showing the configuration of one embodiment of a frequency comparison circuit according to the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. 4 and 5 are circuit diagrams specifically showing the switched capacitor circuits used in the circuits of FIG. 2 and FIG. 3, respectively, and FIG. Figure and 5th
FIG. 7 is a timing chart of signals used in the circuit shown in the figure. FIG. 7 is a circuit diagram showing the configuration of an applied example of the present invention. 10, 20...Switched capacitor circuit (SC
circuit), 11, 21...capacitor, 12-15,
22-25...Switch, 30...Integrator circuit, 31...
Differential amplifier circuit, 52-55, 72-75...
CMOS switch.

Claims (1)

【特許請求の範囲】 １ 第１の信号の周波数に応じてその抵抗値が設
定され、負の等価抵抗を有する第１の手段と、第
２の信号の周波数に応じてその抵抗値が設定さ
れ、正の等価抵抗を有する第２の手段と、上記第
１、第２の手段に直流バイアスを供給して第１、
第２の手段に直流電流を流す第３の手段と、上記
第１、第２の手段の出力電流の合成電流を積分す
る第４の手段とを具備したことを特徴とする周波
数比較回路。 ２ 前記第１、第２の手段が、キヤパシタと複数
のスイツチを含むスイツチドキヤパシタ回路でそ
れぞれ構成されている特許請求の範囲第１項に記
載の周波数比較回路。 ３ 前記第３の手段が、前記第１、第２の手段に
一定の直流電圧を供給する直流電圧源で構成され
ている特許請求の範囲第１項に記載の周波数比較
回路。 ４ 前記第４の手段が、差動増幅回路とこの差動
増幅回路の入出力端子間に接続される積分用キヤ
パシタとで構成されている特許請求の範囲第１項
に記載の周波数比較回路。 ５ 前記積分用キヤパシタに対して抵抗が並列接
続されている特許請求の範囲第４項に記載の周波
数比較回路。[Claims] 1. The resistance value of the first signal is set according to the frequency of the first signal, and the resistance value is set according to the frequency of the first means having a negative equivalent resistance and the second signal. , a second means having a positive equivalent resistance, and a DC bias is supplied to the first and second means, and the first,
A frequency comparison circuit comprising: third means for passing a direct current through the second means; and fourth means for integrating a combined current of the output currents of the first and second means. 2. The frequency comparison circuit according to claim 1, wherein the first and second means are each constituted by a switched capacitor circuit including a capacitor and a plurality of switches. 3. The frequency comparison circuit according to claim 1, wherein the third means is constituted by a DC voltage source that supplies a constant DC voltage to the first and second means. 4. The frequency comparison circuit according to claim 1, wherein the fourth means comprises a differential amplifier circuit and an integrating capacitor connected between input and output terminals of the differential amplifier circuit. 5. The frequency comparison circuit according to claim 4, wherein a resistor is connected in parallel to the integrating capacitor.
JP21672183A 1983-11-17 1983-11-17 Frequency comparing circuit Granted JPS60109306A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP21672183A JPS60109306A (en) 1983-11-17 1983-11-17 Frequency comparing circuit
DE8484113778T DE3474597D1 (en) 1983-11-17 1984-11-14 Frequency comparing circuit
EP84113778A EP0142171B1 (en) 1983-11-17 1984-11-14 Frequency comparing circuit
DE8787117485T DE3486061T2 (en) 1983-11-17 1984-11-14 OSCILLATOR CIRCUIT.
EP87117485A EP0308540B1 (en) 1983-11-17 1984-11-14 Oscillator circuit
US06/672,478 US4599580A (en) 1983-11-17 1984-11-16 Circuit for comparing two or more frequencies

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21672183A JPS60109306A (en) 1983-11-17 1983-11-17 Frequency comparing circuit

Publications (2)

Publication Number Publication Date
JPS60109306A JPS60109306A (en) 1985-06-14
JPH0122768B2 true JPH0122768B2 (en) 1989-04-27

Family

ID=16692877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21672183A Granted JPS60109306A (en) 1983-11-17 1983-11-17 Frequency comparing circuit

Country Status (1)

Country Link
JP (1) JPS60109306A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251808A (en) * 1988-03-30 1989-10-06 Nec Corp Frequency discriminating circuit

Also Published As

Publication number Publication date
JPS60109306A (en) 1985-06-14

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