JPH01226167A - Manufacture of semiconductor device substrate - Google Patents
Manufacture of semiconductor device substrateInfo
- Publication number
- JPH01226167A JPH01226167A JP5299488A JP5299488A JPH01226167A JP H01226167 A JPH01226167 A JP H01226167A JP 5299488 A JP5299488 A JP 5299488A JP 5299488 A JP5299488 A JP 5299488A JP H01226167 A JPH01226167 A JP H01226167A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon wafer
- silicon film
- ion implantation
- boron ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 229910052796 boron Inorganic materials 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 239000010453 quartz Substances 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 6
- -1 boron ions Chemical class 0.000 claims abstract description 5
- 238000003486 chemical etching Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 239000007864 aqueous solution Substances 0.000 claims 1
- LUMVCLJFHCTMCV-UHFFFAOYSA-M potassium;hydroxide;hydrate Chemical compound O.[OH-].[K+] LUMVCLJFHCTMCV-UHFFFAOYSA-M 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＳＯｘ（Ｓｉ］−１ｃｏｎ Ｏｎ工ｎ５ｕｌａ
ｔｏｒ ）基板の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to SOx(Si)-1conon5ula
tor) relates to a method of manufacturing a substrate.
（従来の技術〕
従来、ＳＯｘ基板は、石英板あるいは酸化膜被覆シリコ
ン・ウェーハ上にシリコン書ウェーハの表面を接着し、
該シリコン・ウェーハの裏面から機械的な研削、研摩を
施し、次で機械、化学研摩により鏡面に仕上げて、薄い
シリコン膜を絶縁体上に残存せしめる手段をとっていた
。(Prior Art) Conventionally, SOx substrates are produced by bonding the surface of a silicon wafer onto a quartz plate or an oxide film-coated silicon wafer.
The backside of the silicon wafer is mechanically ground and polished, and then mechanically and chemically polished to a mirror finish, leaving a thin silicon film on the insulator.
しかし、上記従来技術によると薄いシリコン膜厚のバラ
ツキが大きいと云う問題点があろた。However, the above-mentioned conventional technique has a problem in that the thickness of the thin silicon film varies greatly.
本発明は、かかる従来技術の問題点をなくし、ＳＯｘ基
板の薄いシリコン膜の厚さバラツキを小さくするＳＯｘ
基板の製造方法を提供する事を目的とする。The present invention eliminates the problems of the prior art and reduces the variation in the thickness of the thin silicon film of the SOx substrate.
The purpose is to provide a method for manufacturing substrates.
上記問題点を解決するために１本発明は、半導体装置基
板の製造方法に関し、シリコン・ウェーハ基板の表面か
らボロン・イオン打込みを行ない、アニール後、該シリ
コン・ウェーハ基板の表面と石英板又は酸化膜被覆シリ
コン・ウェーハとを接着し、前記シリコン・ウェーハ基
板の裏面からＫＯＨ水溶欣等による化学エツチングをボ
ロン・イオン打込み層を機械・化学研摩により除去し、
薄いシリコン膜を絶縁体上に残存せしめる手段をとる。In order to solve the above problems, the present invention relates to a method for manufacturing a semiconductor device substrate, in which boron ions are implanted from the surface of a silicon wafer substrate, and after annealing, the surface of the silicon wafer substrate and a quartz plate or oxidized A film-coated silicon wafer is bonded to the silicon wafer substrate, and the boron ion implantation layer is removed by chemical etching using KOH water solution or the like from the back side of the silicon wafer substrate, and the boron ion implantation layer is removed by mechanical/chemical polishing.
Measures are taken to leave a thin silicon film on the insulator.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示すＳＯ工基板の製造工程
である。すなわち、
（α）シリコン・ウェーハ基板１、あるいは酸化膜を形
成したシリコン・ウェーハ基板の鏡面表面（通＞Ｋシリ
コン・ウェーハは鏡面表面に対し、裏面は、粗面となっ
ている）から、
（ｂ）扁エネルギー・イオン打込み装置によりシリコン
表面に対し、α３μｍから２〜３μｍ１ｊＪ度の深さか
あるいはそれ以上の深さに、ボロン・イオンを１０１４
／ｃＩＡ以上打込んでボロン・イオン打込み層２を形成
し、該ボロン・イオン打込み層の活性化とイオン打込み
誘起欠陥の除去を目的として９００℃で５０分程度のア
ニール処理を窒素雰囲気中で行ない、
（Ｃ）酸化膜等の絶縁膜４を被覆したシリコン・ウェー
ハの鏡面表面か、鏡面研摩した石英板の表面に、前記、
ボロン・イオン打込みノー２を形成したシリコン・ウェ
ーハ基板１の鏡面表面とを拳に合わせズ、加熱すること
によりシラノール反応により接着させることができ、接
着させる。FIG. 1 shows the manufacturing process of an SO-processed substrate showing an embodiment of the present invention. That is, (α) From the mirror surface of the silicon wafer substrate 1 or the silicon wafer substrate on which an oxide film has been formed (the back surface of a silicon wafer is rough compared to the mirror surface), ( b) Boron ions are deposited at a depth of 1014 degrees from α3 μm to 2 to 3 μm 1JJ degrees or more into the silicon surface using a flat energy ion implantation device.
/cIA or more is implanted to form a boron ion implantation layer 2, and annealing treatment is performed at 900° C. for about 50 minutes in a nitrogen atmosphere for the purpose of activating the boron ion implantation layer and removing ion implantation-induced defects. (C) The mirror surface of a silicon wafer coated with an insulating film 4 such as an oxide film, or the surface of a mirror-polished quartz plate,
By placing the mirror surface of the silicon wafer substrate 1 on which the boron ion implantation No. 2 has been formed on the mirror surface of the silicon wafer substrate 1 in a fist and heating it, the silanol reaction can be carried out to cause the bonding.
（ｄ）次で前記ボロン・イオン打込み層２を形成したシ
リコン・ウェーハ基板１の裏面から、まず粗研摩を通常
の機械的な研削、研摩にてボロン・イオン打込み層２の
現出する直近進行ない、次で、ＫＯＨ水溶奴等のシリコ
ンの化学エツチング液に浸漬する事により粗研摩を残存
せるボロン・イオン打込みＭ ２迄のシリコンを除去す
ることができる。すなわち、ボロン・イオン打込み層は
化学エツチングのストッパーとしての作用があり、粗研
摩で残存せるシリコン層の厚さのバラツキには関係なく
、薄いシリコン膜の厚さが均一（イオン・打込みの深さ
バラツキは非常に小さいので）に残存せしめる事が出来
る。(d) Next, from the back side of the silicon wafer substrate 1 on which the boron ion implantation layer 2 has been formed, first rough polishing is performed by ordinary mechanical grinding and polishing to expose the boron ion implantation layer 2. Next, silicon up to M2 can be removed by boron ion implantation that leaves rough polishing by immersion in a silicon chemical etching solution such as KOH water soluble. In other words, the boron ion implantation layer acts as a stopper for chemical etching, and the thickness of the thin silicon film is uniform (the depth of the ion implantation Since the variation is very small, it is possible to make it remain.
（１次で、前記ボロン・イオン打込み層の除去と鏡面仕
上げを目的として、Ｓｉｎ、微粒をアルカリ溶液に入れ
た研摩液を用いてバフ研摩をすする機械、化学研摩を行
なうことにより結晶欠陥のない、且つ、厚さの均一な薄
いシリコン膜５を残存させる事ができ、ＳＯ工基板とな
す事が出来る。(In the first step, for the purpose of removing the boron ion-implanted layer and achieving a mirror finish, crystal defects are removed by mechanical polishing and chemical polishing using a polishing solution containing Sin and fine particles in an alkaline solution.) Moreover, a thin silicon film 5 having a uniform thickness can be left, and an SO-processed substrate can be obtained.
本発明により、例えば従来薄いシリコン膜厚のバラツキ
が１．０μｍｔｈα５μ隅と１μｍ程度のバラツキがあ
ったのに対し、本性によるとバラツキは１．０μｍ±α
１μｍとｏ、２μｍ以下に押える事が出来る効果があり
、ひいては薄いシリコン膜の厚さが１５μｍ以下でも製
作可能となり、極めて薄いシリコン膜から成るＳＯ工基
板が提供出来ると共に該ＳＯ工基板を用いた高集積の誘
電体素子分離による高速の集積回路が製作出来る効果等
もある。With the present invention, for example, conventionally the variation in thin silicon film thickness was about 1.0μmthα5μ corner and about 1μm, but according to the originality, the variation is 1.0μm±α
It has the effect of being able to suppress the thickness to 1 μm and 2 μm or less, and as a result, it is possible to manufacture a thin silicon film with a thickness of 15 μm or less, and it is possible to provide an SO-processed substrate made of an extremely thin silicon film and to use the SO-processed substrate. Another advantage is that high-speed integrated circuits can be manufactured by separating highly integrated dielectric elements.
第１図（α）〜（−）は本発明の一実施例を示すＳＯ工
基板の製造工程順の断面図である。
１・・・・・・・・・シリコン９ウエーハ基板２・・・
・・・・・・ボロン・イオン打込み層３…・・・・φ・
シリコン・ウェーハ
４・・・・・・・・・絶縁膜
５・・・・・・・・・薄いシリコン膜
以上
出願人 セイコーエプソン株式会社FIGS. 1(α) to 1(-) are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps of an SO-processed substrate. 1... Silicon 9 wafer substrate 2...
...Boron ion implantation layer 3...φ・
Silicon wafer 4... Insulating film 5 Thin silicon film or more Applicant Seiko Epson Corporation
Claims (1)
込みを行ない、アニール後、該シリコン・ウェーハ基板
の表面と石英板又は酸化膜被覆シリコン・ウェーハとを
接着し、前記シリコン・ウェーハ基板の裏面からＫＯＨ
水溶液等による化学エッチングをボロン・イオン打込み
層迄行ない、その後該ボロン・イオン打込み層を機械、
化学研摩により除去し、薄いシリコン膜を、絶縁体上に
残存せしめる事を特徴とする半導体装置基板の製造方法
。Boron ions are implanted from the surface of a silicon wafer substrate, and after annealing, the surface of the silicon wafer substrate is bonded to a quartz plate or a silicon wafer coated with an oxide film, and KOH is implanted from the back surface of the silicon wafer substrate.
Chemical etching with an aqueous solution or the like is performed up to the boron ion implantation layer, and then the boron ion implantation layer is etched mechanically.
A method of manufacturing a semiconductor device substrate, characterized in that a thin silicon film is removed by chemical polishing and left on an insulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5299488A JPH01226167A (en) | 1988-03-07 | 1988-03-07 | Manufacture of semiconductor device substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5299488A JPH01226167A (en) | 1988-03-07 | 1988-03-07 | Manufacture of semiconductor device substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01226167A true JPH01226167A (en) | 1989-09-08 |
Family
ID=12930478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5299488A Pending JPH01226167A (en) | 1988-03-07 | 1988-03-07 | Manufacture of semiconductor device substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01226167A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
| US5213986A (en) * | 1992-04-10 | 1993-05-25 | North American Philips Corporation | Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning |
| US5231045A (en) * | 1988-12-08 | 1993-07-27 | Fujitsu Limited | Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers |
| US5244817A (en) * | 1992-08-03 | 1993-09-14 | Eastman Kodak Company | Method of making backside illuminated image sensors |
| JPH06331559A (en) * | 1993-05-18 | 1994-12-02 | Hitachi Ltd | Method and apparatus for inspection of foreign body |
| US5395788A (en) * | 1991-03-15 | 1995-03-07 | Shin Etsu Handotai Co., Ltd. | Method of producing semiconductor substrate |
| US5672518A (en) * | 1990-10-16 | 1997-09-30 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having stacked layered substrate |
| WO1998042010A1 (en) * | 1997-03-17 | 1998-09-24 | Genus, Inc. | Bonded soi wafers using high energy implant |
| KR100251817B1 (en) * | 1990-08-31 | 2000-05-01 | 비센트 비.인그라시아 | Method of fabricating integrated silicon and non-silicon semiconductor device |
| JP2002509367A (en) * | 1998-01-20 | 2002-03-26 | ラム リサーチ コーポレーション | Cleaning / buffing polishing equipment used in wafer processing equipment |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
-
1988
- 1988-03-07 JP JP5299488A patent/JPH01226167A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231045A (en) * | 1988-12-08 | 1993-07-27 | Fujitsu Limited | Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers |
| US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
| KR100251817B1 (en) * | 1990-08-31 | 2000-05-01 | 비센트 비.인그라시아 | Method of fabricating integrated silicon and non-silicon semiconductor device |
| US5926699A (en) * | 1990-10-16 | 1999-07-20 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having stacked layer substrate |
| US5672518A (en) * | 1990-10-16 | 1997-09-30 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having stacked layered substrate |
| US5759878A (en) * | 1990-10-16 | 1998-06-02 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having epitaxially grown semiconductor single crystal film |
| US6040200A (en) * | 1990-10-16 | 2000-03-21 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having stacked-layered substrate |
| US5395788A (en) * | 1991-03-15 | 1995-03-07 | Shin Etsu Handotai Co., Ltd. | Method of producing semiconductor substrate |
| US5213986A (en) * | 1992-04-10 | 1993-05-25 | North American Philips Corporation | Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning |
| US5244817A (en) * | 1992-08-03 | 1993-09-14 | Eastman Kodak Company | Method of making backside illuminated image sensors |
| JPH06331559A (en) * | 1993-05-18 | 1994-12-02 | Hitachi Ltd | Method and apparatus for inspection of foreign body |
| WO1998042010A1 (en) * | 1997-03-17 | 1998-09-24 | Genus, Inc. | Bonded soi wafers using high energy implant |
| JP2002509367A (en) * | 1998-01-20 | 2002-03-26 | ラム リサーチ コーポレーション | Cleaning / buffing polishing equipment used in wafer processing equipment |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| US8389385B2 (en) | 2009-02-04 | 2013-03-05 | Micron Technology, Inc. | Semiconductor material manufacture |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4774196A (en) | Method of bonding semiconductor wafers | |
| JP3395661B2 (en) | Method for manufacturing SOI wafer | |
| CN1894795B (en) | Laminated semiconductor substrate and process for producing the same | |
| KR101057140B1 (en) | Silicon-on-Insulator Substrates with Fine Buried Insulation Layers | |
| JP3684401B2 (en) | Manufacturing method of SOI wafer | |
| EP1710836A1 (en) | Method for manufacturing soi wafer | |
| EP0706714A1 (en) | Soi substrate fabrication | |
| US9496130B2 (en) | Reclaiming processing method for delaminated wafer | |
| JPH01226167A (en) | Manufacture of semiconductor device substrate | |
| JP5261960B2 (en) | Manufacturing method of semiconductor substrate | |
| CN114420834A (en) | Thin film preparation method based on oblique bonding and composite thin film thereof | |
| JP2002184960A (en) | Manufacturing method of soi wafer and soi wafer | |
| TWI251875B (en) | Manufacturing method of bonding wafer | |
| JPH0922993A (en) | Soi wafer and manufacture thereof | |
| CN114388688A (en) | Blackened single crystal piezoelectric composite film based on plasma etching and preparation method thereof | |
| WO2007133604B1 (en) | Method for forming a semiconductor on insulator structure | |
| JP3484961B2 (en) | Method for manufacturing SOI substrate | |
| JP4581349B2 (en) | Manufacturing method of bonded SOI wafer | |
| KR100291515B1 (en) | Method for manufacturing silicon on insulator wafer | |
| JPH01226168A (en) | Manufacture of semiconductor device substrate | |
| JPH01226166A (en) | Manufacture of semiconductor device substrate | |
| TW200409282A (en) | A method of increasing the area of a useful layer of material transferred onto a support | |
| JP2754819B2 (en) | Method for manufacturing dielectric-separated semiconductor substrate | |
| JPH03228326A (en) | Manufacture of semiconductor device | |
| KR100286772B1 (en) | Method for manufacturing silicon on insulator wafer |