JPH01223743A - Manufacture of master slice system semiconductor device - Google Patents

Abstract

PURPOSE:To make the title manufacture suitable for multi-kind and small quantity production while shortening a production period, and to reduce the cost of a chip, by conducting patterning up to the completion of master slice through projection exposure using a photomask and forming a wiring pattern to shape a master slice through direct drawing. CONSTITUTION:A photomask 5 composed of a glass plate 3 and patterns 4 for photoetching shaped to the glass plate 3 is arranged made to correspond to a plurality of chip regions 2 on a wafer 1, light 6 is applied from the upper section of the photomask 5, and patterns 7 are transferred respectively to all chip regions 2. An element forming process is completed, each chip region 2 in master slice 8 is irradiated with light 12 or electron beams through lenses 10, 11 fitted to an aperture 9, and the aperture 9 is moved in the mutually orthogonal XY coordinate directions, thus directly drawing wiring patterns onto respective chip region 2. Accordingly, the wiring patterns different at every chip region can be drawn freely.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a master slice type semiconductor device.

Prior Art ``In recent years, semi-custom ICs have been attracting attention for specific applications such as gate arrays and standard cells. This IC is a master slice that goes through the process of forming elements such as transistors on a semiconductor substrate.

By producing large quantities and changing only the wiring pattern according to the user's specifications, a semiconductor integrated circuit unique to each application can be realized.

Problems to be Solved by the Invention In such master slice type semiconductor devices, a very small amount of evaluation samples are often manufactured prior to mass production. When forming a wiring layer on a master slice to form this evaluation sample, the conventional method is to perform projection exposure on all chips on the master slice (wafer) using a photomask to form a wiring pattern. was being implemented.

This not only lengthens the manufacturing period (lead time), but also causes problems such as all the chips on the master slice are manufactured in the same way for the small amount of chips required, making the cost per chip relatively high. Ta.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a master slice type semiconductor device, which is suitable for high-mix low-volume production, shortens the manufacturing period, and reduces the chip unit price. It is something to do.

Means for Solving the Problems In order to solve the above problems, the method for manufacturing a master slice type semiconductor device of the present invention performs patterning until the completion of the master slice by projection exposure using a photomask, and The wiring pattern is formed by direct drawing.

Effect With the above configuration, patterning is performed by projection exposure suitable for mass production up to the process of manufacturing the master slice, and patterning is performed by direct writing suitable for small quantity production in the wiring formation process to the master slice. The manufacturing period for master slice type semiconductor devices can be shortened through the process, and direct writing allows the wiring pattern to be minutely changed for each chip on the master slice, so different wiring patterns can be created on the same master slice. It is also easy to draw two or more types of chips. Therefore, when producing samples of a wide variety of types in very small quantities, the number of master slices can be reduced, and the chip unit price can be reduced.

EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 shows a method for manufacturing a master slice semiconductor device according to an embodiment of the present invention.
It is a diagram explaining the patterning method up to the process of
A glass plate 3 and a photo-etching pattern formed thereon corresponding to a plurality of chip areas 2 on a wafer 1 (here, it is simplified and shown as a pattern of the English letters rFJ)
A photomask 5 consisting of a photomask 4 is arranged, and light 6 is irradiated from above the photomask 5 to transfer an rFJ pattern 7 onto the entire chip area 2, respectively. This patterning process includes a diffused layer, a separate diffused layer, a base layer, and a buried layer.
It is used in all steps of the device fabrication process until master slicing is completed, such as resistor diffusion layer and emitter/collector expansion. Of course, this projection exposure method is not limited to the method shown in FIG. 1, and methods such as a contact method, a processing method, and a stepper can be used.

Figure 2 shows the patterning method used in the wiring formation process to the master slice, and shows the patterning method used in the process of forming interconnects to the master slice. 2, the light 1 is transmitted through the lens 10.11 provided on the Apache 17-9.
2 or an electron beam (not shown) and moves the aperture 9 in mutually perpendicular X and Y coordinate directions, thereby directly drawing a wiring pattern on each chip region 2.

In this way, by controlling the movement vJffl of the aperture 9 in the XY coordinate directions, it is possible to freely draw different wiring patterns for each chip area. Therefore, two or more types of semiconductor integrated circuits can be realized on one master slice 8, which is particularly advantageous when manufacturing a small amount of samples.

Note that in a master slice type semiconductor device using multilayer wiring, the lower layer wiring and the formation of contact holes above it are prepared as a master slice, and only the wiring pattern of the top layer is changed to form a semiconductor integrated circuit. In such a case, it is sufficient to perform patterning by projection exposure using a master slice up to the step of forming the contact hole, and directly write only the R-end wiring forming step.

Effects of the Invention As described above, according to the present invention, until the process of manufacturing a master slice is completed, patterning is performed by projection exposure using a photomask, and the wiring pattern in the process of forming wiring on this master slice is Because direct writing is performed, it is possible to shorten the manufacturing period for high-mix, low-volume production and reduce the chip unit price.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating a patterning method up to the step of manufacturing a master slice in a method for manufacturing a master slice semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a method for manufacturing a master slice semiconductor device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a patterning method in a wiring formation process for a master slice of FIG. 1... Wafer, 3... Glass plate, 4... Pattern, 5... Phytomask, 6.12... Light, 8...
・Master slice, 9...Apatcher, 10.1
1...Lens. Agent Yoshi Morimoto Private use Figure 1 Figure 2

Claims (1)

[Claims] 1. A method for manufacturing a master slice type semiconductor device, characterized in that patterning until the completion of the master slice is performed by projection exposure using a photomask, and formation of a wiring pattern on the master slice is performed by direct drawing.